IGBT (Insulated Gate Bipolar Translator) device integrated with self-biased floating Schottky diode and preparation method
By embedding floating Schottky diodes in the P-body of IGBT devices, the problem of contradiction between on and off losses of IGBT devices is solved, and more efficient power utilization and better short-circuit tolerance are achieved.
Patent Information
- Application Number
- CN202510224526.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-06-13
AI Technical Summary
There are losses contradictions between existing IGBT devices when conducting and shutting down, making it difficult to meet the requirements of higher energy saving and efficient use of electricity.
The IGBT device structure with integrated self-biased floating Schottky diode is adopted, and a series-connected floating self-biased P-type Schottky diode and N-type Schottky diode are embedded in the P-body. The anode is connected through floating metal to optimize the carrier distribution and conductance modulation effect of the device.
Improves the device's conductivity and short-circuit withstandability, reduces saturation current, improves the device's turn-off loss performance, and optimizes the compromise relationship between conductivity and turn-off loss.
Smart Images
Figure CN120152313A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to power semiconductor technology, and particularly to an IGBT device structure integrated with a self-biased floating Schottky diode and a manufacturing process thereof. Background Art
[0002] Power semiconductors, as the core power electronic components for energy control, transmission, and conversion, are an important cornerstone for achieving energy conservation and emission reduction, green manufacturing, and efficient production. As a new type of MOS-gated bipolar power device, IGBT plays a key role in power control, transmission, and conversion, and is also known as the "CPU" of power electronics, with advantages such as low on-state loss, high switching frequency, high power density, and high input impedance. As a minority-carrier device, when IGBT is conducting, a large number of minority carriers exist in the body to obtain the conductivity modulation effect, thereby reducing the on-state resistance and on-state loss of the device; in order to further reduce the on-state loss, the carrier injection efficiency is increased to increase the concentration of minority carriers in the body, thereby enhancing the conductivity modulation effect. However, during turn-off, the large number of minority carriers existing in the body can only disappear through extraction and recombination, resulting in its turn-off loss being greater than that of a majority-carrier device (MOSFET), which leads to a contradiction between on-state loss and turn-off loss. Therefore, in order to improve the trade-off relationship between on-state loss and turn-off loss, the Floating P-body IGBT was proposed.
[0003] The Floating P-body IGBT suppresses the direct inflow of holes into the emitter by introducing a floating P-body at the emitter end, increases the hole concentration at the emitter end, optimizes the carrier distribution in the body, and changes the carrier distribution in the device body from extremely low at the emitter end and high at the collector end in a traditional IGBT to high at the emitter end and low at the collector end, improving the conductivity modulation effect of the device, thereby reducing the on-state loss of the device; at the same time, the carriers at the emitter end can accelerate the extraction of carriers, reduce the hole current tail during device turn-off, and improve the turn-off loss of the device, thereby improving the trade-off relationship between on-state loss and turn-off loss of the device. However, with the continuous development of technology, people's yearning for a better life is constantly increasing, and the dependence on electric energy is also closer. How to achieve more energy-saving and efficient use of electric energy has put forward higher requirements for IGBT, and it is necessary to further reduce the on-state loss and turn-off loss of IGBT. Due to its structural limitations, the Floating P-body IGBT is difficult to meet this higher requirement, and a new IGBT needs to be proposed to meet the application requirements. Based on this, the present invention proposes an IGBT device structure integrated with a self-biased floating Schottky diode, aiming to improve the trade-off relationship between on-state loss and turn-off loss of the device, reduce the saturation current to improve the short-circuit withstand ability of the device, and in addition, a simplified process flow manufacturing diagram of the new structure device is given. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide an IGBT device integrated with a self-biased floating Schottky diode and a manufacturing method thereof.
[0005] To achieve the above object of the invention, the technical solution of the present invention is as follows:
[0006] An IGBT device integrated with a self-biased floating Schottky diode, comprising a collector metal 1, a P-type collector region 2, an N-type buffer layer 3, an N-type drift region 4, a floating P-type region 5, an N-type blocking region 6, a P-body 7, a P+ emitter region 8, an N+ emitter region 9, a trench gate oxide layer 10, a gate polysilicon 11, an emitter metal 12, a floating metal 13, an N-type Schottky contact region 14, an N+ emitter contact region 15, a P+ emitter contact region 16, a gate oxide isolation region 17 and a floating metal oxide isolation region 18;
[0007] The collector metal 1 is located below the P-type collector region 2; the P-type collector region 2 is located between the collector metal 1 and the N-type buffer layer 3; the N-type buffer layer 3 is located below the N-type drift region 4; the N-type drift region 4 is located below the floating P-type region 5, and the N-type blocking region 6 is located below the P-body 7;
[0008] The bottom of the trench gate oxide layer 10 is placed in the floating P-type region 5; the inner surface of the trench gate oxide layer 10 surrounds the gate polysilicon 11 therein, and at the same time, the trench gate oxide layer 10 penetrates through the entire P-body 7 and the N-type blocking region 6, dividing the P-body 7 and the N-type blocking region 6 into left and right parts;
[0009] On the left side of the trench gate oxide layer 10, above the P-body 7 are the P+ emitter region 8 and the N+ emitter region 9, and the right surface of the P+ emitter region 8 is in contact with the N+ emitter region 9; above the P+ emitter region 8 and the N+ emitter region 9 is the emitter metal 12, and the lower surface of the emitter metal 12 is in contact with the P+ emitter region 8 and the N+ emitter region 9; the N-type drift region 4 is in contact with the lower surface of the N-type blocking region 6 on the left side of the trench gate oxide layer 10; the right surface of the N+ emitter region 9 is in contact with the trench gate oxide layer 10;
[0010] On the right side of the trench gate oxide layer 10 and above the P-body 7 are the P+ emitter contact region 16, the N+ emitter contact region 15, and the P+ emitter contact region 14. The N+ emitter contact region 15 is located between the P+ emitter contact region 16 and the P+ emitter contact region 14. The left and right surfaces of the N+ emitter contact region 15 are in contact with the P+ emitter contact region 16 and the N-type Schottky contact region 14 respectively; the lower surfaces of the P+ emitter contact region 14, the N+ emitter contact region 15, and the P+ emitter contact region 16 are in contact with the P-body 7. The right surface of the P+ emitter contact region 14, the right surface of the P-body 7, and the right surface of the N-type blocking region 6 are all in contact with the floating metal 13; the floating P-type region 5 is located below the N-type blocking region 6. The left surface of the floating P-type region 5 is in contact with the N-type drift region 4. The upper surface of the floating P-type region 5 is in contact with the N-type blocking region 6 and the floating metal 13. The lower surface of the emitter metal 12 is in contact with the upper surfaces of the P+ emitter contact region 16 and the N+ emitter contact region 15 in part. The left surface of the P+ emitter contact region 16 is in contact with the trench gate oxide layer 10;
[0011] The trench gate oxide layer 10 is located below the gate oxide isolation region 17. The outer surface of the trench gate oxide layer 10 is in contact with the N+ emitter region 9, the N-type blocking region 6, the P-body 7, the floating P-type region 5, and the P+ emitter contact region 16; the emitter metal 12 is located at the top of the device. The emitter metal 12 is in contact with the floating metal oxide isolation region 17 and the floating metal oxide isolation region 18; the gate oxide isolation region 17 and the floating metal oxide isolation region 18 are located in the emitter metal 12. The lower surface of the gate oxide isolation region 17 is in contact with the trench gate oxide layer 10 and the gate polysilicon 11. The floating metal oxide isolation region 18 is located above the floating metal 13, the N-type Schottky contact region 14, and the N+ emitter contact region 15. The upper surface of the floating metal 13, the upper surface of the N-type Schottky contact region 14, and the upper surfaces of the N+ emitter contact region 15 in part are all in contact with the lower surface of the floating metal oxide isolation region 18.
[0012] As a preferred embodiment, the floating metal 13 forms Schottky contact diodes with the floating P-type region 5, the N-type blocking region 6, the P-body 7, and the N-type Schottky contact region 14. Among them, the floating metal 13 forms an N-type Schottky diode with the N-type blocking region 6 and the N-type Schottky contact region 14, and forms a P-type Schottky diode with the floating P-type region 5 and the P-body 7.
[0013] As a preferred embodiment, the metal of the floating metal 13 is Al, Pt, Ni, AlSiCu, or a metal composite, and its work function is adjusted using different metals.
[0014] As a preferred embodiment, the P-type Schottky diode and the N-type Schottky diode are shorted together at the anode through the floating metal 13.
[0015] As a preferred embodiment, the doping concentration of the floating P-type region 5 is between 1×10 16 cm -3 and 1×10 18 cm -3 .
[0016] As a preferred embodiment, the doping concentration of the N-type blocking region 6 is between 1×10 16 cm -3 and 1×10 18 cm -3 .
[0017] As a preferred embodiment, the doping concentration of the N-type Schottky contact region 14 is between 1×10 13 cm -3 and 1×10 18 cm -3 .
[0018] The second object of the present invention is to provide a method for manufacturing an IGBT device with the integrated self-biased floating Schottky diode, including the following steps:
[0019] (a) First, form the floating P-type region 5 through photolithography, P-type ion implantation, and annealing; next, form the N-type blocking region 6 using N-type ion implantation and annealing; finally, form the P-body 7 using P-type ion implantation and annealing;
[0020] (b) Form the gate communication through photolithography and etching; then, form the trench gate oxide layer 10 through high-temperature oxidation, and the high-temperature oxidation temperature is between 900°C and 1200°C; next, fill the gate polysilicon 11 through chemical deposition, and perform chemical mechanical polishing CMP after deposition;
[0021] (c) Form the P+ emitter region 8 and the P+ emitter contact region 16 through photolithography, P-type ion implantation, and annealing; then, form the N+ emitter region 9 and the N+ emitter contact region 15 through photolithography, N-type ion implantation, and annealing; finally, form the N-type Schottky contact region 14 using photolithography, N-type ion implantation, and annealing again;
[0022] (d) Form the floating metal trench through photolithography and etching, next deposit metal physically to form the floating metal 13, and finally perform chemical mechanical polishing CMP;
[0023] (e) Form the oxide isolation layer through chemical vapor deposition, and then form the gate oxide layer isolation region 17 and the floating metal oxide layer isolation region 18 through photolithography and etching;
[0024] (f) Form the emitter metal 12 by physical deposition and then perform annealing to make the metal contact the silicon surface more closely;
[0025] (g) Thin the wafer to the required thickness by TAIKO or ordinary thinning; Next, perform N-type ion implantation and annealing to form the N-type buffer layer 3, and then perform P-type ion implantation and annealing to form the P-type collector region 2; Finally, perform backside metal sputtering to form the collector metal 1.
[0026] The beneficial effects of the present invention are as follows:
[0027] Compared with the previous Floating P-body IGBT structure, the IGBT proposed in the present invention embeds a series of floating self-biased P-type Schottky diodes and N-type Schottky diodes in the P-body. The anode of the P-type Schottky diode of the device is connected to the anode of the N-type Schottky through a floating metal; when the potential of the floating P-type region is greater than the sum of the turn-on voltages of the two floating Schottky diodes, it will provide a conduction path for the hole current to reduce the saturation current, improve the short-circuit withstand ability of the device, and at the same time accelerate the extraction of holes from the device body to improve the turn-off loss of the device; when the potential of the floating P-type region is less than the sum of the turn-on voltages of the two floating Schottky diodes, the conductivity modulation effect is further enhanced, thereby improving the conduction ability. To sum up, the IGBT device structure integrating a self-biased floating Schottky diode proposed in this method not only improves the short-circuit withstand ability of the device, but also improves the trade-off relationship between the conduction performance and the turn-off loss. Description of the Drawings
[0028] Figure 1 is a schematic diagram of the traditional Floating P-body IGBT structure;
[0029] Figure 2 is a schematic diagram of an IGBT device structure integrating a self-biased floating Schottky diode proposed in the present invention;
[0030] Figure 3 is a comparison diagram of the I-V relationship of an IGBT integrating a self-biased floating Schottky diode proposed in the present invention and a traditional Floating P-body IGBT in the forward conduction state;
[0031] Figure 4 is a comparison diagram of the saturation current of an IGBT integrating a self-biased floating Schottky diode proposed in the present invention and a traditional Floating P-body IGBT;
[0032] Figure 5It is a comparison chart of the short-circuit withstand capabilities of an IGBT integrated with a self-biased floating Schottky diode proposed by the present invention and a traditional Floating P-body IGBT;
[0033] Figure 6 It is a comparison chart of the turn-off waveforms of an IGBT integrated with a self-biased floating Schottky diode proposed by the present invention and a traditional Floating P-body IGBT;
[0034] Figures 7 - 13 It is a key process step in the manufacturing process of an IGBT device integrated with a self-biased floating Schottky diode provided by the present invention;
[0035] 1 - Collector metal, 2 - P-type collector region, 3 - N-type buffer layer, 4 - N-type drift region, 5 - Floating P-type region, 6 - N-type blocking region, 7 - P-body, 8 - P+ emitter region, 9 - N+ emitter region, 10 - Trench gate oxide layer, 11 - Gate polysilicon, 12 - Emitter metal, 13 - Floating metal, 14 - N-type Schottky contact region, 15 - N+ emitter contact region, 16 - P+ emitter contact region, 17 - Gate oxide isolation region, 18 - Floating metal oxide isolation region. Detailed implementation manners
[0036] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] Example 1
[0038] As Figure 2 shown, the present invention proposes an IGBT device structure integrated with a self-biased floating Schottky diode, including collector metal 1, P-type collector region 2, N-type buffer layer 3, N-type drift region 4, floating P-type region 5, N-type blocking region 6, P-body 7, P+ emitter region 8, N+ emitter region 9, trench gate oxide layer 10, gate polysilicon 11, emitter metal 12, floating metal 13, N-type Schottky contact region 14, N+ emitter contact region 15, P+ emitter contact region 16, gate oxide isolation region 17, and floating metal oxide isolation region 18;
[0039] The collector metal 1 is located below the P-type collector region 2; the P-type collector region 2 is located between the collector metal 1 and the N-type buffer layer 3; the N-type buffer layer 3 is located below the N-type drift region 4; the N-type drift region 4 is located below the floating P-type region 5, and the N-type blocking region 6 is located below the P-body 7;
[0040] The bottom of the trench gate oxide layer 10 is placed in the floating P-type region 5; the inner surface of the trench gate oxide layer 10 surrounds the gate polysilicon 11 therein. At the same time, the trench gate oxide layer 10 penetrates through the entire P-body 7 and the N-type blocking region 6, dividing the P-body 7 and the N-type blocking region 6 into left and right parts;
[0041] On the left side of the trench gate oxide layer 10 and above the P-body 7 are the P+ emitter region 8 and the N+ emitter region 9. The right surface of the P+ emitter region 8 is in contact with the N+ emitter region 9; above the P+ emitter region 8 and the N+ emitter region 9 is the emitter metal 12, and the lower surface of the emitter metal 12 is in contact with the P+ emitter region 8 and the N+ emitter region 9; the N-type drift region 4 is in contact with the lower surface of the N-type blocking region 6 on the left side of the trench gate oxide layer 10; the right surface of the N+ emitter region 9 is in contact with the trench gate oxide layer 10;
[0042] On the right side of the trench gate oxide layer 10 and above the P-body 7 are the P+ emitter contact region 16, the N+ emitter contact region 15, and the P+ emitter contact region 14. The N+ emitter contact region 15 is located between the P+ emitter contact region 16 and the P+ emitter contact region 14. The left and right surfaces of the N+ emitter contact region 15 are respectively in contact with the P+ emitter contact region 16 and the N-type Schottky contact region 14; the lower surfaces of the P+ emitter contact region 14, the N+ emitter contact region 15, and the P+ emitter contact region 16 are in contact with the P-body 7. The right surface of the P+ emitter contact region 14, the right surface of the P-body 7, and the right surface of the N-type blocking region 6 are all in contact with the floating metal 13; the floating P-type region 5 is located below the N-type blocking region 6. The left surface of the floating P-type region 5 is in contact with the N-type drift region 4. The upper surface of the floating P-type region 5 is in contact with the N-type blocking region 6 and the floating metal 13. The lower surface of the emitter metal 12 is in contact with the upper surfaces of the P+ emitter contact region 16 and the N+ emitter contact region 15 in part. The left surface of the P+ emitter contact region 16 is in contact with the trench gate oxide layer 10;
[0043] The trench gate oxide layer 10 is located below the gate oxide isolation region 17, and the outer surface of the trench gate oxide layer 10 is in contact with the N+ emitter region 9, the N-type blocking region 6, the P-body 7, the floating P-type region 5, and the P+ emitter contact region 16; the emitter metal 12 is located at the top of the device, and the emitter metal 12 is in contact with the floating metal oxide isolation region 17 and the floating metal oxide isolation region 18; the gate oxide isolation region 17 and the floating metal oxide isolation region 18 are located in the emitter metal 12, the lower surface of the gate oxide isolation region 17 is in contact with the trench gate oxide layer 10 and the gate polysilicon 11, the floating metal oxide isolation region 18 is located above the floating metal 13, the N-type Schottky contact region 14, and the N+ emitter contact region 15, and the upper surface of the floating metal 13, the upper surface of the N-type Schottky contact region 14, and a part of the upper surface of the N+ emitter contact region 15 are all in contact with the lower surface of the floating metal oxide isolation region 18.
[0044] The floating metal 13 forms Schottky contact diodes with the floating P-type region 5, the N-type blocking region 6, the P-body 7, and the N-type Schottky contact region 14. Among them, the floating metal 13 forms an N-type Schottky diode with the N-type blocking region 6 and the N-type Schottky contact region 14, and forms a P-type Schottky diode with the floating P-type region 5 and the P-body 7.
[0045] Preferably, the metal of the floating metal 13 is Al, Pt, Ni, AlSiCu, or a metal composite, and its work function is adjusted using different metals.
[0046] Preferably, the P-type Schottky diode and the N-type Schottky diode are short-circuited at the anode through the floating metal 13.
[0047] Preferably, the doping concentration of the floating P-type region 5 is between 1×10 16 cm -3 ~1×10 18 cm -3 .
[0048] Preferably, the doping concentration of the N-type blocking region 6 is between 1×10 16 cm -3 ~1×10 18 cm -3 .
[0049] Preferably, the doping concentration of the N-type Schottky contact region 14 is between 1×10 13 cm -3 ~1×10 18 cm -3 .
[0050] The working principle of this embodiment is as follows:
[0051] An IGBT device integrated with a self - biased floating Schottky diode provided by the present invention embeds a series - connected floating self - biased P - type Schottky diode and N - type Schottky diode in the P - body.
[0052] When the device is in the forward - conducting state, the P - type collector region injects holes into the device body, and the N+ emitter region injects electrons into the device body, thereby realizing the conductivity modulation effect in the drift region to reduce the on - resistance of the drift region. At the same time, since the potential of the floating P - type region is less than the sum of the turn - on voltages of the P - type Schottky diode (the N - type Schottky contact formed by the floating metal 13 and the floating P - type region 5) and the N - type Schottky diode (the P - type Schottky contact formed by the floating metal 13 and the N+ emitter contact region 15), and the N - type blocking region has a blocking effect on holes, the hole distribution in the device body is further optimized, thereby improving the on - performance of the device.
[0053] When the device is short - circuit - tolerant, due to the large voltage applied across the collector and emitter of the device, the potential of the floating P - type region is greater than the sum of the turn - on voltages of the P - type Schottky diode (the N - type Schottky contact formed by the floating metal 13 and the floating P - type region 5) and the N - type Schottky diode (the P - type Schottky contact formed by the floating metal 13 and the N+ emitter contact region 15). The N - type Schottky diode and the P - type Schottky diode will provide a conduction path for the hole current to reduce the saturation current in the short - circuit state, thereby improving the short - circuit tolerance of the device.
[0054] When the device is turned off, due to the large voltage applied across the collector and emitter of the device, the potential of the floating P - type region is greater than the sum of the turn - on voltages of the P - type Schottky diode (the N - type Schottky contact formed by the floating metal 13 and the floating P - type region 5) and the N - type Schottky diode (the P - type Schottky contact formed by the floating metal 13 and the N+ emitter contact region 15). The N - type Schottky diode and the P - type Schottky diode will provide an extraction path for the hole current, accelerating the outflow of holes from the device body, thereby improving the turn - off loss of the device.
[0055] In summary, an IGBT device integrated with a self - biased floating Schottky diode proposed by the present invention not only improves the on - performance and short - circuit tolerance of the device, but also improves the turn - off performance, and at the same time improves the trade - off relationship between the on - performance and the turn - off loss.
[0056] This embodiment also provides a preparation method for an IGBT device integrated with a self - biased floating Schottky diode, including the following steps:
[0057] 1. A single-crystalline silicon substrate is adopted. First, a floating P-type region 5 is formed by photolithography, P-type ion implantation, and annealing; next, an N-type blocking region 6 is formed by N-type ion implantation and annealing; finally, a P-body 7 is formed by P-type ion implantation and annealing, as Figure 7 shown.
[0058] 2. Trench gate. The gate communication is formed by photolithography and etching; then, a trench gate oxide layer 10 is formed by high-temperature oxidation; next, the gate polysilicon 11 is filled by chemical deposition method, and chemical mechanical polishing CMP is performed after deposition, as Figure 8 shown.
[0059] 3. A P+ emitter region 8 and a P+ emitter contact region 16 are formed by photolithography, P-type ion implantation, and annealing; then, an N+ emitter region 9 and an N+ emitter contact region 15 are formed by photolithography, N-type ion implantation, and annealing; finally, an N-type Schottky contact region 14 is formed by photolithography, N-type ion implantation, and annealing, as Figure 9 shown.
[0060] 4. Floating metal. A floating metal trench is formed by photolithography and etching, and then physical deposition of metal is carried out to form a floating metal 13. Finally, chemical mechanical polishing CMP is performed, as Figure 10 shown.
[0061] 5. Oxide isolation layer. An oxide isolation layer is formed by chemical vapor deposition method, and then photolithography and etching are carried out to form a gate oxide layer isolation region 17 and a floating metal oxide layer isolation region 18, as Figure 11 shown.
[0062] 6. Emitter metal. The emitter metal 12 is formed by physical deposition, and then annealing is carried out to make the contact between the metal and the silicon surface closer, as Figure 12 shown.
[0063] 7. Backside process. The wafer is thinned to the required thickness by TAIKO or ordinary thinning; next, an N-type buffer layer 3 is formed by N-type ion implantation and annealing, and then a P-type collector region 2 is formed by P-type ion implantation and annealing; finally, backside metal sputtering is carried out to form a collector metal 1, as Figure 13 shown.
[0064] An IGBT device integrating a self-biased floating Schottky diode proposed by the present invention is also applicable to devices made of semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide, or silicon germanium.
[0065] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. An IGBT device with an integrated self-biased floating Schottky diode, characterized in that: It comprises a collector metal (1), a P-type collector region (2), an N-type buffer layer (3), an N-type drift region (4), a floating P-type region (5), an N-type barrier region (6), a P-body (7), a P+ emitter region (8), an N+ emitter region (9), a trench gate oxide layer (10), a gate polysilicon (11), an emitter metal (12), a floating metal (13), an N-type Schottky contact region (14), an N+ emitter contact region (15), a P+ emitter contact region (16), a gate oxide layer isolation region (17) and a floating metal oxide layer isolation region (18); The collector metal (1) is located below the P-type collector region (2); the P-type collector region (2) is located between the collector metal (1) and the N-type buffer layer (3); the N-type buffer layer (3) is located below the N-type drift region (4); the N-type drift region (4) is located below the floating P-type region (5); and the N-type barrier region (6) is located below the P-body (7); The bottom of the trench gate oxide layer (10) is placed in the floating P-type region (5); the inner surface of the trench gate oxide layer (10) surrounds the gate polysilicon (11) therein, and the trench gate oxide layer (10) penetrates the entire P-body (7) and the N-type barrier region (6), dividing the P-body (7) and the N-type barrier region (6) into left and right parts; On the left side of the trench gate oxide layer (10), above the P-body (7) are the P+ emitter region (8) and the N+ emitter region (9), and the right surface of the P+ emitter region (8) is in contact with the N+ emitter region (9); above the P+ emitter region (8) and the N+ emitter region (9) is the emitter metal (12), and the lower surface of the emitter metal (12) is in contact with the P+ emitter region (8) and the N+ emitter region (9); the N-type drift region (4) is in contact with the lower surface of the N-type barrier region (6) on the left side of the trench gate oxide layer (10); and the right surface of the N+ emitter region (9) is in contact with the trench gate oxide layer (10); On the right side of the trench gate oxide layer (10), above the P-body (7) are the P+ emitter contact region (16), the N+ emitter contact region (15) and the P+ emitter contact region (14); the N+ emitter contact region (15) is located between the P+ emitter contact region (16) and the P+ emitter contact region (14); the left and right surfaces of the N+ emitter contact region (15) are in contact with the P+ emitter contact region (16) and the N-type Schottky contact region (14) respectively; the lower surfaces of the P+ emitter contact region (14), the N+ emitter contact region (15) and the P+ emitter contact region (16) are in contact with the P-body (7); the P+ emitter contact region (14) is located between the P+ emitter contact region (16) and the N-type Schottky contact region (14) respectively; the lower surfaces of the P+ emitter contact region (14), the N+ emitter contact region (15) and the P+ emitter contact region (16) are in contact with the P-body (7); the P+ emitter contact region (15) is located between the P+ emitter contact region (16) and the N-type Schottky contact region (14) respectively; the lower surfaces of the P+ emitter contact region (14), the N+ emitter contact region (15) and the P+ emitter contact region (16) are ...-body (7); the P+ emitter contact region (16) is located between the P+ emitter contact region (16) and the N-type Schottky contact region (14) respectively; the P+ emitter contact region (16) is located between the P+ emitter contact region (16) and the N-type Schott The right surface of the emitter contact region (14), the right surface of the P-body (7), and the right surface of the N-type barrier region (6) are all in contact with the floating metal (13); the floating P-type region (5) is located below the N-type barrier region (6); the left surface of the floating P-type region (5) is in contact with the N-type drift region (4); the upper surface of the floating P-type region (5) is in contact with the N-type barrier region (6) and the floating metal (13); the lower surface of the emitter metal (12) is in contact with the P+ emitter contact region (16) and a portion of the upper surface of the N+ emitter contact region (15); and the left surface of the P+ emitter contact region (16) is in contact with the trench gate oxide layer (10); The trench gate oxide layer (10) is located below the gate oxide layer isolation region (17), and the outer surface of the trench gate oxide layer (10) is in contact with the N+ emitter region (9), the N-type barrier region (6), the P-body (7), the floating P-type region (5), and the P+ emitter contact region (16); the emitter metal (12) is located at the top of the device, and the emitter metal (12) is in contact with the floating metal oxide layer isolation region (17) and the floating metal oxide layer isolation region (18); the gate oxide layer isolation region (17), the floating metal oxide layer The isolation region (18) is located in the emitter metal (12), the lower surface of the gate oxide layer isolation region (17) is in contact with the trench gate oxide layer (10) and the gate polysilicon (11), the floating metal oxide layer isolation region (18) is located above the floating metal (13), the N-type Schottky contact region (14), and the N+ emitter contact region (15), and the upper surface of the floating metal (13), the upper surface of the N-type Schottky contact region (14), and part of the upper surface of the N+ emitter contact region (15) are all in contact with the lower surface of the floating metal oxide layer isolation region (18).
2. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The floating metal (13) forms a Schottky contact diode with the floating P-type region (5), the N-type barrier region (6), the P-body (7) and the N-type Schottky contact region (14), wherein the floating metal (13) forms an N-type Schottky diode with the N-type barrier region (6) and the N-type Schottky contact region (14), and forms a P-type Schottky diode with the floating P-type region (5) and the P-body (7).
3. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The metal of the floating metal (13) is Al, Pt, Ni, AlSiCu or a metal composite, and its work function is adjusted using different metals.
4. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The anodes of the P-type Schottky diode and the N-type Schottky diode are short-circuited together via a floating metal (13).
5. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The doping concentration of the floating P-type region (5) is 1×10 16 cm -3 ~1×10 18 cm -3 between.
6. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The doping concentration of the N-type barrier region (6) is 1×10 16 cm -3 ~1×10 18 cm -3 between.
7. The IGBT device with integrated self-biased floating Schottky diode according to claim 1, characterized in that: The doping concentration of the N-type Schottky contact region (14) is 1×10 13 cm -3 ~1×10 18 cm -3 between.
8. The method for preparing an IGBT device with an integrated self-biased floating Schottky diode according to any one of claims 1 to 7, characterized in that The steps include: (a) First, a floating P-type region (5) is formed by photolithography, P-type ion implantation, and annealing; next, an N-type barrier region (6) is formed by N-type ion implantation and annealing; finally, a P-body (7) is formed by P-type ion implantation and annealing; (b) forming a gate electrode by photolithography and etching; then forming a trench gate oxide layer (10) by high temperature oxidation; next, filling the gate polysilicon (11) by chemical deposition method, and performing chemical mechanical polishing (CMP) after the deposition is completed; (c) forming a P+ emitter region (8) and a P+ emitter contact region (16) by photolithography, P-type ion implantation, and annealing; then, forming an N+ emitter region (9) and an N+ emitter contact region (15) by photolithography, N-type ion implantation, and annealing; and finally, forming an N-type Schottky contact region (14) by photolithography, N-type ion implantation, and annealing; (d) forming a floating metal groove by photolithography and etching, then physically depositing metal to form a floating metal (13), and finally performing chemical mechanical polishing (CMP); (e) forming an oxide isolation layer by chemical vapor deposition, and then performing photolithography and etching to form a gate oxide layer isolation region (17) and a floating metal oxide layer isolation region (18); (f) forming an emitter metal (12) by physical deposition, followed by annealing to make the metal more closely contact the silicon surface; (g) Thinning the wafer to the required thickness by TAIKO or ordinary thinning; then, performing N-type ion implantation and annealing to form an N-type buffer layer (3), and then performing P-type ion implantation and annealing to form a P-type collector region (2); Finally, back metal sputtering is performed to form the collector metal (1).