Groove type silicon carbide gate turn-off thyristor
By introducing a trench-type structure into SiC MCT, changing the carrier path and enhancing the conductance modulation effect, the problems of reduced current gain and large switching losses are solved, and performance improvement in high-voltage and high-power applications are achieved.
Patent Information
- Application Number
- CN202421670845.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-07-15
AI Technical Summary
Traditional SiC MCT devices have problems such as reduced current gain, increased on-resistance, and high switching losses, which are difficult to meet performance requirements in high voltage and high power applications.
A structure similar to a trench IGBT is introduced on the NPN structure of the traditional SiC MCT, so that free carriers can enhance the conductance modulation effect of the N-drift region through the gate path, and bear high voltage through the MOS structure formed by the gate and P-type base region, suppress high electric fields, and optimize current distribution.
It improves current gain, reduces switching losses and on-voltage drop, improves switching speed and integration of the device, simplifies the driving circuit and reduces costs.
Smart Images
Figure CN223125207U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power semiconductor devices, and particularly to a trench-type silicon carbide gate turn-off thyristor. Background Art
[0002] With the development of industrial technology, higher conversion efficiency and power density are required for power electronic devices. Traditional Si devices are difficult to meet the performance requirements of contemporary industries for power devices. As the third-generation wide bandgap semiconductor material, SiC material has excellent performance in all aspects, which is bringing a new revolution in power electronic technology.
[0003] The working efficiency of traditional unipolar devices will decrease with the increase of on-resistance. In a typical bipolar device, SiC IGBT, due to the problem of insufficient minority carrier accumulation, its forward on-state voltage drop is much higher than that of thyristors. At the same time, triple diffusion process is required in the actual manufacture of Si-based MCT, making it difficult to manufacture. Secondly, it also faces the problem of how to balance on-state voltage drop and turn-off loss.
[0004] Traditional MCT is a planar gate structure, with weak current saturation ability, large on-conduction loss, and the current gain achieved by current SiC MCT cannot be used to control a large area of SiC MCT with a small integrated circuit. Therefore, the design of the drive circuit is more complex and the drive loss is higher. The trench-type silicon carbide gate turn-off thyristor (SiC MCT) belongs to a composite device of trench-type IGBT and thyristor, and has excellent performances such as simple drive circuit, fast switching speed, and high voltage resistance. It not only increases the blocking voltage but also reduces the on-state voltage drop. At the same time, the trench-type SiC MCT also adjusts the current direction, making the device more integrated and reducing the cost. Therefore, among many SiC devices, SiC MCT has attracted much attention in high-voltage and high-power applications.
[0005] Meanwhile, it is found that after the traditional SiC MCT works for a period of time, the current gain of the device will decrease, and the specific on-resistance will also increase. Therefore, in order to reduce the drive loss of the device, a sufficiently high current gain is required. The researchers believe that there are mainly two reasons for the decrease in current gain. One is that the recombination-induced stacking faults will affect the bulk recombination in the base region; the other is that the surface recombination of SiC / SiO2 in the etched region of the outer base region increases the surface recombination current in the base region and degrades the performance of the device. In addition, the conductivity modulation effect plays an important role in bipolar devices. Its existence enables bipolar devices to conduct a large current density at a low turn-on voltage. However, the traditional MCT will only produce the conductivity modulation effect when a large number of free carriers are stored in the base region and the collector region. However, since these carriers need to be provided and removed during the turn-on and turn-off processes, the switching time and transient loss of the traditional MCT will increase. Therefore, how to make the current distribution uniform, increase the current gain, reduce the turn-off loss and the on-state voltage drop is an urgent problem to be solved at present.
[0006] Therefore, a new technical solution needs to be proposed to improve the above technical problems. Summary of the Invention
[0007] Aiming at the defects in the prior art, the purpose of the present invention is to provide a trench-type silicon carbide gate turn-off thyristor.
[0008] A trench-type silicon carbide gate turn-off thyristor provided according to the present invention includes: a collector, an N++ substrate, an N- collector region, a P- base region, an N- emitter region, a P+ contact source region, an N+ contact source region, a source S, a gate G, a gate insulating layer, and a gate dielectric;
[0009] An N++ substrate is provided above the collector; an N- collector region is provided above the N++ substrate; on the left side of the N- collector region, a P- base region and an N- emitter region above the P- base region are included in sequence from bottom to top. The P+ contact source region and the N+ contact source region are arranged in the N- emitter region, and the P+ contact source region is located on both sides of the N+ contact source region; the source S is above the P+ contact source region and the N+ contact source region; a gate G is arranged on the right side of the N- collector region. The gate G is arranged in a corresponding trench above the N++ substrate and forms a gate insulating layer on the side wall of the trench respectively, and a gate dielectric is filled; the trench vertically extends from the P+ contact source region, the N- emitter region, the P- base region to the N- collector region; there are two electrodes, the source S and the gate G, on the front of the trench, and an insulating layer is deposited between the metals of the two electrodes, the source S and the gate G.
[0010] Preferably, the gate dielectric is polysilicon.
[0011] Preferably, the medium of the gate insulating layer is SiO2.
[0012] Preferably, the source S and gate G metals include Al, AlCu, and AlSiCu, and the collector includes Ti, Ni, or TiNiAg.
[0013] Preferably, the materials of the N++ substrate, N- collector region, P- base region, N- emitter region, P+ contact source region, and N+ contact source region are all SiC.
[0014] Preferably, both the P+ contact source region and the N+ contact source region are formed by ion implantation.
[0015] Compared with the prior art, the present utility model has the following beneficial effects:
[0016] 1. By introducing a novel trench-type silicon carbide gate turn-off thyristor, the present utility model introduces a path similar to that of a trench IGBT into the original NPN structure of a traditional SiC MCT, allowing free carriers to pass through the gate path, thereby enhancing the conductivity modulation effect of the N- drift region.
[0017] 2. The novel structure of the present utility model can accelerate the extraction and recombination of electrons and holes in the space charge region, improve the base transport coefficient, and thus has the advantages of increasing the current gain, improving the device switching speed, reducing the switching loss, and lowering the conduction voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Other features, objectives, and advantages of the present utility model will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0019] Figure 1 Schematic diagram of the novel trench-type silicon carbide gate turn-off thyristor structure of the present utility model;
[0020] Figure 2 Schematic diagram of the materials preparation of the present utility model;
[0021] Figure 3 Schematic diagram of the formation of the P+ contact source region 1 by Al ion implantation in the present utility model;
[0022] Figure 4 Schematic diagram of the formation of the N+ contact source region 2 by N ion implantation in the present utility model;
[0023] Figure 5 Schematic diagram of the formation of the gate trench in the present utility model;
[0024] Figure 6 Schematic diagram of the formation of the gate insulating layer 9 in the present utility model;
[0025] Figure 7 Schematic diagram of the formation of the gate dielectric layer 8 in the present utility model;
[0026] Figure 8 Schematic diagram of the insulating layer formed between the source S11 and the gate G10 of the present utility model;
[0027] Figure 9 Schematic diagram of covering the front metal of the present utility model;
[0028] Figure 10 Schematic diagram of forming the source S11 and the gate G10 of the present utility model;
[0029] Figure 11 Schematic diagram of forming the collector 7 of the present utility model. Detailed implementation manners
[0030] The present utility model will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present utility model, but do not limit the present utility model in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present utility model, several changes and improvements can still be made. These all fall within the protection scope of the present utility model.
[0031] Example 1:
[0032] A trench-type silicon carbide gate turn-off thyristor provided by the present utility model includes: a collector, an N++ substrate, an N- collector region, a P- base region, an N- emitter region, a P+ contact source region, an N+ contact source region, a source S, a gate G, a gate insulating layer, and a gate dielectric; an N++ substrate is provided above the collector; an N- collector region is provided above the N++ substrate; the P- base region and the N- emitter region above the P- base region are sequentially included from bottom to top on the left side of the N- collector region, and the P+ contact source region and the N+ contact source region are arranged in the N- emitter region and the P+ contact source region is located on both sides of the N+ contact source region; the source S is above the P+ contact source region and the N+ contact source region; the gate G is arranged on the right side of the N- collector region, the gate G is arranged in a corresponding trench above the N++ substrate and a gate insulating layer is formed on the side wall of the trench respectively, and a gate dielectric is filled; the trench vertically extends from the P+ contact source region, the N- emitter region, the P- base region to the N- collector region from top to bottom; there are two electrodes, the source S and the gate G, on the front of the trench, and an insulating layer is deposited between the metals of the two electrodes, the source S and the gate G.
[0033] The gate dielectric is polysilicon; the dielectric of the gate insulating layer is SiO2; the source S and gate G metals include Al, AlCu, and AlSiCu, and the collector includes Ti, Ni, or TiNiAg; the materials of the N++ substrate, N- collector region, P- base region, N- emitter region, P+ contact source region, and N+ contact source region are all SiC; both the P+ contact source region and the N+ contact source region are formed by ion implantation.
[0034] The present utility model also provides a method for manufacturing a trench-type silicon carbide gate turn-off thyristor. The method is applied to the trench-type silicon carbide gate turn-off thyristor described above, and the method includes the following steps:
[0035] Step S1: Prepare an epitaxial wafer and clean it; the N++ substrate, N- collector region, P- base region, and N- emitter region are all obtained by epitaxial growth. The N- collector region, P- base region, and N- emitter region are sequentially formed on the N++ substrate by epitaxial growth; the doping concentration of the N++ substrate is 1×10 18 ~1×10 19 cm -3 , and the thickness is about 1 μm; the doping concentration of the N- collector region is 3×10 15 ~5×10 15 cm -3 , and the thickness is 15 - 20 μm; the doping concentration of the P- base region is 1×10 17 ~3×10 17 cm -3 , and the thickness is 0.6 - 1 μm; the doping concentration of the N- emitter region is 2×10 19 ~3×10 19 cm -3 , and the thickness is 0.8 - 2 μm.
[0036] Step S2: Inject Al ions to form the P+ contact source region;
[0037] Step S3: Inject N ions to form the N+ contact source region, and perform activation annealing under the protection of a carbon film;
[0038] Step S4: Use a dry etching method to etch the gate trench. The trench passes through the P+ contact source region, N- emitter region, P- base region, and N- collector region; the trench depth is 2 - 2.8 μm, so that the trench penetrates the P+ contact source region, N- emitter region, and P- base region and reaches the N- collector region.
[0039] Step S5: Generate a gate oxide layer on the bottom and side walls of the trench, then perform annealing in a nitrogen atmosphere, and fill polysilicon inside the trench to form the gate dielectric;
[0040] Step S6 deposits an oxide layer on both sides of the gate G above the P+ contact source region under the new photomask, serving as the insulating layer between the two metal electrodes of the source S and the gate G;
[0041] Step S7: Deposit the front metal of the source S and the gate G, and etch the metal to form the source S and the gate electrode G;
[0042] Step S8: Deposit the back metal to form the collector.
[0043] Example 2:
[0044] The present utility model proposes a novel trench-type silicon carbide gate turn-off thyristor. By introducing a structure similar to that of a trench IGBT into the original NPN structure of a traditional SiC MCT, the path of free carriers injected from the collector through the N+ substrate directly to the emitter through the N- drift region will be changed, and the free carriers will instead pass through the gate path. In this process, minority carriers will be quickly removed, reducing the switching loss and enhancing the conductivity modulation effect of the N- drift region. Among them, when the trench-type SiC MCT operates in the blocking state, the gate-source voltage will become zero potential or negative potential. The PN junction formed by the P-type base region and the N- drift region and the MOS structure composed of the gate electrode and the N-type drift region bear the high voltage between the source and the drain, and have a higher breakdown voltage compared with the traditional SiC MCT; when the device operates in the forward conduction state, the P-base region can suppress the high electric field in the gate oxide layer, achieving a strong conductivity modulation effect and reducing the forward conduction voltage.
[0045] At the same time, in a traditional SiC MCT, due to the optimization and development of modern processes, the influence of the surface recombination effect on the current gain has gradually decreased, and currently the current gain is more limited by the emitter injection efficiency and the carrier recombination in the base region. In the novel trench-type silicon carbide gate turn-off thyristor, the structure established in the N- emitter region has the function of a built-in electric field and combines with the P-base region, which can accelerate the electron transit through the P-base region and inhibit the diffusion of holes from the P-base region to the N- emitter region, and can accelerate the extraction and recombination of electrons and holes in the space charge region, improving the base transport coefficient. Therefore, the trench-type SiC MCT can make the current distribution uniform, improve the current gain, reduce the switching loss and the conduction voltage drop.
[0046] What the present utility model aims to solve is to provide a novel trench-type silicon carbide gate turn-off thyristor for the problems of uneven current distribution, reduced current gain, and large losses in the current traditional SiC MCT.
[0047] To solve the above problems, the present utility model proposes a novel trench-type silicon carbide gate turn-off thyristor. By introducing a structure similar to that of a trench IGBT into the original NPN structure of a traditional SiC MCT, the path of free carriers injected from the collector through the N+ substrate directly to the emitter through the N- drift region is changed, and the free carriers are made to pass through the gate path. During this process, minority carriers are rapidly removed, reducing the switching loss and enhancing the conductivity modulation effect of the N- drift region. Among them, when the trench-type SiC MCT is in the blocking state, the gate-source voltage becomes zero or negative potential, and the PN junction formed by the P-type base region and the N- drift region and the MOS structure formed between the gate electrode and the N-type drift region bear the high voltage between the source and the drain, having a higher breakdown voltage than the traditional SiC MCT; when the device is in the forward conduction state, the P-base region can suppress the high electric field in the gate oxide layer, achieving a strong conductivity modulation effect and reducing the forward conduction voltage.
[0048] Meanwhile, in traditional SiC MCTs, due to the optimization and development of modern processes, the influence of surface recombination effects on current gain has gradually decreased, and currently, the current gain is mainly limited by the emitter injection efficiency and carrier recombination in the base region. In the novel trench-type silicon carbide gate turn-off thyristor, the structure established in the N- emitter region has the effect of a built-in electric field and combines with the P-base region, which can accelerate the electron transit through the P-base region and inhibit the diffusion of holes from the P-base region to the N-emitter region, accelerating the extraction and recombination of electrons and holes in the space charge region and improving the base transport factor. Therefore, the trench-type SiC MCT can make the current distribution uniform, increase the current gain, reduce the switching loss and the conduction voltage drop.
[0049] The present utility model introduces a novel trench-type silicon carbide gate turn-off thyristor, introducing a path similar to that of a trench IGBT into the original NPN structure of a traditional SiC MCT, and making the free carriers pass through the gate path, enhancing the conductivity modulation effect of the N- drift region. The novel structure can accelerate the extraction and recombination of electrons and holes in the space charge region, improving the base transport factor, thus having the advantages of increasing the current gain, enhancing the switching speed of the device, reducing the switching loss and the conduction voltage drop.
[0050] Such as Figure 1A novel trench-type silicon carbide gate turn-off thyristor is shown, which includes a collector 7; an N++ substrate 6 above the collector 7; an N- collector region 5 above the N++ substrate 6; a P- base region 4 sequentially included from bottom to top on the left side of the N- collector region 5; an N- emitter region 3 above the P- base region 4, which includes a P+ contact source region 1 and an N+ contact source region 2 arranged in the N- emitter region 3 and the P+ contact source region 1 is located on both sides of the N+ contact source region 2; a source S11 above the P+ contact source region 1 and the N+ contact source region 2; a gate G10 is arranged on the right side of the N- collector region 5, the gate is arranged in a corresponding trench above the N++ substrate 6 and a gate insulating layer 9 is formed on the side wall of the trench respectively, and a gate dielectric 8 is formed by filling with polysilicon; and wherein the trench vertically extends from the P+ contact source region 1, the N- emitter region 3, the P- base region 4 to the N- collector region 5 respectively from top to bottom; due to the two electrodes of the front active source S11 and the gate G10, an insulating layer needs to be deposited between the metals of the two electrodes.
[0051] Preferably: The gate dielectric 8 is polysilicon.
[0052] Preferably: The dielectric of the insulating layer 9 is SiO2.
[0053] Preferably: The metals of the source S11 and the gate G10 can be Al, AlCu, AlSiCu, etc., and the collector can be Ti, Ni or TiNiAg, etc.
[0054] Preferably: The materials of the N++ substrate 6, the N- collector region 5, the P- base region 4, the N- emitter region 3, the P+1 contact source region and the N+ contact source region 2 are all SiC.
[0055] Preferably: The P+ contact source region 1 and the N+ contact source region 2 are both formed by ion implantation.
[0056] As Figures 1 - 11 shown, the present invention provides a method for a novel trench-type silicon carbide gate turn-off thyristor, which includes the following steps:
[0057] The first step: epitaxial wafer preparation, the structure of the epitaxial wafer is as Figure 2 shown, cleaning. Wherein the N++ substrate 6, the N- collector region 5, the P- base region 4, and the N- emitter region 3 are all obtained by epitaxial growth, and the N- collector region 5, the P- base region 4, and the N- emitter region 3 are sequentially formed on the N++ substrate 6 by epitaxial growth.
[0058] Preferably: the doping concentration of the N++ substrate 6 can be 1×1018 to 1×1019 cm-3, and the thickness is about 1 μm; the doping concentration of the N- collector region 5 can be 3×1015 to 5×1015 cm-3, and the thickness is 15 to 20 μm; the doping concentration of the P- base region 4 can be 1×1017 to 3×1017 cm-3, and the thickness is 0.6 to 1 μm; the doping concentration of the N- emitter region 3 can be 2×1019 to 3×1019 cm-3, and the thickness is 0.8 to 2 μm.
[0059] Step 2: As Figure 3 shown, Al ions are implanted to form the P+ contact source region 1.
[0060] Step 3: As Figure 4 shown, N ions are implanted to form the N+ contact source region 2, and activation annealing is performed under the protection of a carbon film.
[0061] Preferably: the carbon film protection is to cover the surface of the SiC wafer with a carbon film as the protection ion implantation window during the annealing process after the ion implantation process to prevent volatilization; the activation annealing process can use laser annealing, and the temperature can be selected from 650 °C to 850 °C for 40 min.
[0062] Step 4: As Figure 5 shown, the gate trench is etched by dry etching, and the trench passes through the P+ contact source region 1, the N- emitter region 3, the P- base region 4, and the N- collector region 5.
[0063] Preferably: the depth of the trench can be 2 to 2.8 μm, so that the trench penetrates the P+ contact source region 1, the N- emitter region 3, and the P- base region 4 and reaches the N- collector region 5.
[0064] Step 5: As Figure 6 shown, a gate oxide layer 9 is formed at the bottom and side walls of the trench, and annealing is performed in a nitrogen atmosphere, and polysilicon is filled into the trench as shown in Figure 7 shown to form the gate dielectric 8.
[0065] Preferably: the gate oxide layer 9 can be prepared by thermal oxidation, and the thickness can be 50 to 100 nm; the annealing temperature can be 1000 °C to 1200 °C for 40 to 60 min.
[0066] Step 6: As Figure 8 shown, an oxide layer is deposited on both sides of the gate G10 above the P+ contact source region 1 under a new photomask as the insulating layer between the source electrode S11 and the gate electrode G10.
[0067] Preferably: the thickness of the gate oxide layer 9 can be 100 to 200 nm.
[0068] Step 7: AsFigure 9 Deposit the front metal of the source electrode S10 and the gate G11 as shown, and as Figure 10 shown, etch the metal to form the source electrode S11 and the gate electrode G10.
[0069] Preferably: the mesa width of the source electrode S11 can be 2-3 μm, so that it covers the entire N+ contact source region and connects the two P+ contact source regions on both sides; the mesa width of the gate G10 can be 1-2 μm, so that it covers the entire gate dielectric.
[0070] The eighth step: Deposit the back metal to form the collector 7 as shown in Figure 11 the figure.
[0071] Preferably: the thickness of the back metal can be 150-200 nm.
[0072] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.
[0073] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.
[0074] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. Without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.
Claims
1. A trench-type silicon carbide gate turn-off thyristor, characterized in that, Comprising: Collector, N++ substrate, N- collector region, P- base region, N- emitter region, P+ contact source region, N+ contact source region, source S, gate G, gate insulating layer and gate dielectric; An N++ substrate is provided above the collector; an N- collector region is provided above the N++ substrate; on the left side of the N- collector region, a P- base region and an N- emitter region above the P- base region are sequentially included from bottom to top. The P+ contact source region and the N+ contact source region are disposed in the N- emitter region, and the P+ contact source region is located on both sides of the N+ contact source region; the source S is above the P+ contact source region and the N+ contact source region; a gate G is disposed on the right side of the N- collector region. The gate G is disposed in a corresponding trench above the N++ substrate and forms a gate insulating layer on the side walls of the trench respectively, and a gate dielectric is filled. The trench vertically extends from the P+ contact source region, the N- emitter region, the P- base region to the N- collector region; there are two electrodes, the source S and the gate G, on the front surface of the trench, and an insulating layer is deposited between the metals of the two electrodes, the source S and the gate G.
2. The trench-type silicon carbide gate turn-off thyristor according to claim 1, wherein The gate dielectric is polysilicon.
3. The trench-type silicon carbide gate turn-off thyristor according to claim 1, wherein The dielectric of the gate insulating layer is SiO2.
4. The trench-type silicon carbide gate turn-off thyristor according to claim 1, wherein The metals of the source S and the gate G include Al, AlCu, AlSiCu, and the collector includes Ti, Ni or TiNiAg.
5. The trench-type silicon carbide gate turn-off thyristor according to claim 1, wherein The materials of the N++ substrate, the N- collector region, the P- base region, the N- emitter region, the P+ contact source region and the N+ contact source region are all SiC.
6. The trench-type silicon carbide gate turn-off thyristor according to claim 1, wherein Both the P+ contact source region and the N+ contact source region are formed by ion implantation.