Formation of doped silicon or boron layers

Abstract

An amorphous silicon layer or an amorphous boron layer may be deposited on a substrate using one or more silicon-containing or boron-containing precursors, respectively. A free radical species is provided from a plasma source or from a controlled reaction chamber atmosphere to convert the amorphous silicon layer into a doped silicon layer with compositionally adjustable properties. An initial layer is deposited on one or more semiconductor device structures having a dielectric layer over a conductive layer. The initial layer may be conformally deposited by a CVD-based process and may include amorphous silicon, doped silicon, amorphous boron, or doped boron.

Description

Incorporation by reference The PCT application form is filed simultaneously with this specification as part of this application. Each application identified in the PCT application form filed simultaneously that this application claims the benefit or priority of is incorporated herein by reference in its entirety and for all purposes. BACKGROUND OF THE INVENTION

[0001] Many semiconductor device manufacturing processes involve forming silicon-based dielectric films. Silicon-based dielectric films can include films containing two elements, such as silicon oxide, silicon carbide, or silicon nitride; or three elements, such as silicon oxynitride, silicon carbonitride, or silicon carbonitride; or four elements, such as silicon carbon oxynitride. Depositing high-quality films with a controlled composition can be particularly challenging. The challenges can also include forming a conformal thin film on high aspect ratio structures.

[0002] Semiconductor device manufacturing processes also include boron-containing films because of their low dielectric constant, adhesion to other films, electromigration properties with copper, barrier properties, etch selectivity, low current leakage, high thermal stability, and other properties. Boron-containing films can include boron nitride, boron carbide, or boron carbonitride.

[0003] The background description provided here is for the purpose of presenting the background of the present disclosure generally. The work of the currently named inventors within the scope described in this background art section and aspects of the specification that were not determined to be prior art at the time of filing the application are neither expressly nor impliedly admitted to be prior art to the present disclosure. SUMMARY OF THE INVENTION

[0004] A method of forming a doped silicon layer on a semiconductor substrate is provided. The method can include forming an amorphous silicon layer on the semiconductor substrate in a reaction chamber and exposing the amorphous silicon layer to a gas plasma stream to convert the amorphous silicon layer into a doped silicon layer.

[0005] In some embodiments, the gas plasma stream includes radicals of nitrogen, oxygen, hydrogen, or carbon.

[0006] In some embodiments, the gas plasma stream includes a remote plasma stream.

[0007] In some embodiments, the method further includes generating a remote plasma of a source gas in a remote plasma source. The method further includes introducing the remote plasma as a remote plasma stream into the reaction chamber through a showerhead. The source gas includes a nitrogen-containing reactant, a hydrogen-containing reactant, a hydrocarbon, an oxygen or oxide reactant, or a combination thereof. The source gas includes nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), hydrazine (N 2 H 4 ), acetylene (C2 H 2 )), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), or a mixture thereof. The composition of the source gas in the remote plasma source is controlled to adjust the composition of the doped silicon layer.

[0008] In some embodiments, forming the amorphous silicon layer includes flowing a silicon-containing precursor to adsorb on the surface of the semiconductor substrate and thermally decomposing the silicon-containing precursor to form the amorphous silicon layer. The silicon-containing precursor has an adhesion coefficient of 0.05 or less. The silicon-containing precursor includes silane, disilane, or trisilane.

[0009] In some embodiments, the amorphous silicon layer has a conformality of at least 90%.

[0010] In some embodiments, the doped silicon layer includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride.

[0011] In some embodiments, the doped silicon layer includes a silicon-nitrogen-containing layer, wherein the gas plasma stream includes one or more of the following gaseous species: nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ).

[0012] In some embodiments, the doped silicon layer includes a silicon-carbon-containing layer, wherein the gas plasma stream includes one or more of the following gaseous species: acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), or propylene (C 3 H 6 ).

[0013] In some embodiments, the gas plasma stream includes one or more of the following gaseous species: hydrogen (H 2 ), or methane (CH 4 ).

[0014] In some embodiments, the doped silicon layer comprises a silicon-containing oxygen layer, wherein the gas stream comprises one or more of the following gaseous species: oxygen (O 2 )), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2 ).

[0015] In some embodiments, the gas plasma stream is generated by an inductively coupled plasma or a capacitively coupled plasma.

[0016] Another aspect of the present invention relates to a method of forming a doped silicon layer. The method includes forming a conformal silicon layer on a substrate in a reaction chamber. The method further includes generating a remote plasma of a source gas in a remote plasma source. The source gas includes one or more of the following: nitrogen, oxygen, hydrogen, or carbon. The method further includes exposing the conformal silicon layer to the remote plasma to convert the conformal silicon layer into a doped silicon layer.

[0017] In some embodiments, the conformal silicon layer comprises an amorphous silicon layer.

[0018] In some embodiments, the doped silicon layer comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride.

[0019] In some embodiments, the doped silicon layer comprises a silicon-nitrogen-containing layer. The source gas includes one or more of the following gaseous species: nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ).

[0020] In some embodiments, the doped silicon layer comprises a silicon-carbon-containing layer. The source gas includes one or more of the following gaseous species: acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), or propylene (C 3 H 6 ).

[0021] In some embodiments, the source gas includes one or more of the following gaseous species: hydrogen (H 2 ), or methane (CH 4 ).

[0022] In some embodiments, the doped silicon layer comprises a silicon-oxygen-containing layer, wherein the gas plasma stream comprises one or more of the following gaseous species: oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2 ).

[0023] Another aspect of the present invention relates to a method for forming a crystalline boron-containing layer. The method includes forming an amorphous boron layer on a substrate in a reaction chamber and heating the substrate to a temperature equal to or greater than about 200 °C. The method further includes exposing the amorphous boron layer to one or more gaseous species to convert the amorphous boron layer into a crystalline boron-containing layer.

[0024] In some embodiments, the crystalline boron-containing layer is selected from the group consisting of boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride.

[0025] In some embodiments, the one or more gaseous species include one or more of the following gaseous species: nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ), acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2 ).

[0026] In some embodiments, forming the amorphous boron-containing layer includes flowing a boron-containing precursor to adsorb on the surface of the substrate and thermally decomposing the boron-containing precursor to form an amorphous boron layer. The boron-containing precursor includes: borane, diborane, triborane, tetraborane, pentaborane, hexaborane, decaborane, or a combination thereof.

[0027] Another aspect of the present invention relates to a method of forming a doped boron layer. The method includes forming an amorphous boron layer on a semiconductor substrate in a reaction chamber. The method further includes exposing the amorphous boron layer to a gas plasma stream to convert the amorphous boron layer into a doped boron layer.

[0028] In some embodiments, the gas plasma stream includes radicals of one or more of nitrogen, oxygen, hydrogen, or carbon.

[0029] In some embodiments, the gas plasma stream includes a remote plasma stream.

[0030] In some embodiments, the doped boron layer includes boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride.

[0031] Another aspect of the present invention relates to a method of forming a crystalline silicon-containing layer. The method includes forming an amorphous silicon layer on a substrate in a reaction chamber and heating the substrate to a temperature equal to or greater than about 200 °C. The method further includes exposing the amorphous silicon layer to one or more gas species to convert the amorphous silicon layer into a crystalline silicon-containing layer.

[0032] Another aspect of the present invention relates to a method of depositing a spacer layer on one or more semiconductor device structures. The method includes providing a semiconductor substrate having one or more semiconductor device structures in a processing chamber, wherein each of the one or more semiconductor device structures includes a dielectric overlay on a conductive layer. The method further includes conformally depositing an amorphous silicon initial layer on the dielectric overlay and the conductive layer of the one or more semiconductor device structures, and depositing a spacer layer on the amorphous silicon initial layer.

[0033] In some embodiments, the conformal deposition of the amorphous silicon initial layer and the deposition of the spacer layer occur in the processing chamber.

[0034] In some embodiments, depositing the spacer layer on the amorphous silicon initial layer includes: exposing the semiconductor substrate to a precursor in the processing chamber; generating radicals of hydrogen from a hydrogen source gas in a remote plasma source upstream of the processing chamber; and introducing the radicals of hydrogen into the processing chamber and toward the semiconductor substrate to react with the precursor to form the spacer layer.

[0035] In some embodiments, conformally depositing the amorphous silicon initial layer includes depositing the amorphous silicon initial layer by thermal chemical vapor deposition (CVD).

[0036] In some embodiments, depositing the amorphous silicon initial layer by thermal CVD includes: exposing the one or more semiconductor device structures to a silane-based precursor; and applying thermal energy to thermally decompose the silane-based precursor to deposit the amorphous silicon initial layer.

[0037] The method further includes: before depositing the spacer layer, exposing the amorphous silicon initial layer to plasma to form a doped silicon layer including silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride.

[0038] In some embodiments, the dielectric capping layer includes silicon nitride and the conductive layer includes tungsten or molybdenum.

[0039] In some embodiments, the spacer layer is deposited substantially uniformly over the dielectric capping layer and the conductive layer.

[0040] In some embodiments, the spacer layer includes silicon carbonitride.

[0041] In some embodiments, each of the one or more semiconductor device structures further includes a semiconductor layer including polysilicon, wherein the conductive layer is located over the semiconductor layer.

[0042] In some embodiments, the amorphous silicon initial layer has a thickness of about to about .

[0043] In some embodiments, conformally depositing the amorphous silicon initial layer includes depositing the amorphous silicon initial layer at a temperature between about 400 °C and about 650 °C.

[0044] In some embodiments, the conductive layer in each of the one or more semiconductor device structures includes bit lines in a memory array.

[0045] Another aspect of the invention relates to a method of depositing a spacer layer on one or more semiconductor device structures. The method includes: providing a semiconductor substrate having one or more semiconductor device structures in a processing chamber, wherein each of the one or more semiconductor device structures includes a conductive layer and a dielectric capping layer over the conductive layer; conformally depositing a silicon-based initial layer over the dielectric capping layer and the conductive layer of the one or more semiconductor device structures, wherein the silicon-based initial layer includes silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride; and depositing a spacer layer over the silicon-based initial layer.

[0046] In some embodiments, conformally depositing the silicon-based initial layer includes: exposing the one or more semiconductor device structures to a silane-based precursor in a processing chamber; applying heat energy in the processing chamber to thermally decompose the silane-based precursor to form an amorphous silicon layer; and exposing the amorphous silicon layer to plasma in the processing chamber to form a silicon-based initial layer over the conductive layer and the dielectric capping layer.

[0047] In some embodiments, applying heat energy to thermally decompose the silane-based precursor to form an amorphous silicon layer includes exposing the semiconductor substrate to a high temperature between about 400 °C and about 650 °C.

[0048] In some embodiments, depositing a spacer layer comprises: exposing the one or more semiconductor device structures to a silicon-containing precursor in a processing chamber; generating hydrogen radicals from a hydrogen source gas in a remote plasma source located upstream of the processing chamber; and introducing the hydrogen radicals into the processing chamber and toward the semiconductor substrate to react with the silicon-containing precursor to form a spacer layer.

[0049] In some embodiments, the dielectric capping layer comprises silicon nitride, the conductive layer comprises tungsten or molybdenum, and the spacer layer comprises silicon oxycarbide.

[0050] In some embodiments, a silicon-based initial layer is deposited substantially uniformly over the dielectric capping layer and the conductive layer.

[0051] Another aspect of the present invention relates to an apparatus. The apparatus includes: a processing chamber; a susceptor configured to support a semiconductor substrate in the processing chamber, wherein the semiconductor substrate includes one or more semiconductor device structures, and wherein each of the one or more semiconductor device structures includes a dielectric capping layer over a conductive layer; a gas supply line configured to deliver a precursor gas to the processing chamber; a remote plasma source disposed upstream of the processing chamber and configured to generate a remote plasma; and a controller configured with instructions to conformally deposit a silicon-based initial layer over the dielectric capping layer and the conductive layer in the processing chamber and to deposit a spacer layer over the silicon-based initial layer in the processing chamber.

[0052] In some embodiments, the silicon-based initial layer comprises amorphous silicon.

[0053] In some embodiments, the controller is further configured with instructions to expose the amorphous silicon to a remote plasma to form a silicon-based initial layer on which a spacer layer is formed, wherein the remote plasma comprises a plasma-activated species of one or more dopant gases comprising one or more of nitrogen, oxygen, hydrogen, or carbon.

[0054] In some embodiments, the dielectric capping layer comprises silicon nitride, the conductive layer comprises tungsten or molybdenum, and the spacer layer comprises silicon oxycarbide.

[0055] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A flowchart depicting operations for forming a doped silicon layer in accordance with some embodiments is presented.

[0057] Figure 2 A flowchart depicting operations for forming a doped silicon layer in accordance with some embodiments is presented.

[0058] Figures 3A - 3BFIG. shows Fourier Transform Infrared Spectroscopy (FTIR) absorption spectra for detecting bond types in a silicon nitride layer and a silicon carbide layer, respectively, according to some embodiments.

[0059] Figure 4A FIG. shows a cross-sectional schematic view of an exemplary semiconductor device structure in which a spacer layer is uniformly deposited on a dielectric capping layer and a conductive layer of a semiconductor device structure.

[0060] Figure 4B FIG. shows a cross-sectional schematic view of an exemplary semiconductor device structure in which a spacer layer is non-uniformly deposited on a dielectric capping layer and a conductive layer of a semiconductor device structure due to a nucleation delay effect.

[0061] Figure 5 FIG. shows a flowchart of an exemplary method for forming a spacer layer on one or more semiconductor device structures according to some embodiments.

[0062] Figure 6 FIG. shows a flowchart of an exemplary method for forming a spacer layer on one or more semiconductor device structures according to some other embodiments.

[0063] Figures 7A - 7C FIG. shows a cross-sectional schematic view of an exemplary semiconductor substrate for spacer formation on a plurality of semiconductor device structures according to some embodiments.

[0064] Figure 8 FIG. shows a schematic view of a semiconductor processing apparatus for performing deposition according to some embodiments.

[0065] Figure 9 FIG. shows a schematic view of an exemplary plasma processing apparatus having a remote plasma source according to some embodiments.

[0066] Figure 10 FIG. shows a schematic view of an exemplary plasma processing apparatus having a remote plasma source according to some embodiments. DETAILED DESCRIPTION

[0067] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0068] In the present invention, the terms "semiconductor wafer", "wafer", "substrate", and "semiconductor substrate" are used interchangeably. Those of ordinary skill in the art should understand that the term "substrate" can refer to a silicon wafer during any one of many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm or 300 mm or 450 mm. The following detailed description assumes that the present invention is implemented on a wafer. However, the present invention is not limited thereto. The workpiece can have various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present invention include various articles, such as printed circuit boards and the like.

[0069] In the present invention, the terms "deposit" and "form" are used interchangeably. In addition, the terms "layer" and "film" are used interchangeably. Those of ordinary skill in the art should understand that due to the reduction of feature sizes in semiconductor devices, "forming" a layer in any one of many stages of integrated circuit manufacturing can refer to "depositing" a thin layer by one of various thin film forming methods, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (hot-wire CVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD).

[0070] As used herein in the present invention, the term "doped silicon" refers to any silicon-containing material (crystalline or amorphous) doped with one, two, three, or more than three elements. Such elements include, but are not limited to, oxygen, nitrogen, carbon, and mixtures thereof. Examples of "doped silicon" can include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and silicon carbon oxynitride. In such instances, "doped silicon" can be synonymous with doped silicon oxide, doped silicon nitride, doped silicon carbide, doped silicon oxycarbide, doped oxynitride, doped silicon carbonitride, and doped silicon carbon oxynitride. The term "doped boron" refers to any boron-containing material (crystalline or amorphous) doped with one, two, three, or more than three elements. Such elements include, but are not limited to, oxygen, nitrogen, carbon, and mixtures thereof. Examples of "doped boron" can include boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, and boron carbon oxynitride. In such instances, "doped boron" can be synonymous with doped boron carbide, doped boron nitride, doped boron oxide, doped boron oxynitride, doped boron oxycarbide, doped boron carbonitride, and doped boron carbon oxynitride.

[0071] The fabrication of semiconductor devices typically involves forming one or more silicon-based thin films on a semiconductor substrate in an integrated manufacturing process. The silicon-based thin films can include silicon oxide, silicon nitride, or doped or undoped silicon carbide. The technology nodes in the integrated circuit manufacturing industry are continuously shrinking. The geometries of the devices also shrink with each technology node, and the pitches become smaller. Such high aspect ratio gaps in the technology nodes may need to be filled with an insulating material, such as an insulating material having a low dielectric constant (low-k). Semiconductor integration operations may involve filling high aspect ratio gaps with a low-k dielectric material. This is the case for shallow trench isolation, inter-metal dielectrics, passivation layers, and the like. In another example, as the device features shrink laterally, when the conductive materials get closer and closer, undesired conductive coupling may occur, which may lead to parasitic capacitance, signal propagation delay, and signal crosstalk due to capacitive effects. A low-k material as the inter-layer dielectric (ILD) for conductive interconnects can reduce parasitic capacitance, signal delay, and signal crosstalk. Some applications, including fin field-effect transistor (finFET) structures and dynamic random access memory (DRAM) bit structures, require a low-k material as the sidewall spacer material.

[0072] Silicon nitride is often used as an insulating material in many integrated circuit applications due to its step coverage, thermal stability, etchability, and etch resistance with high breakdown voltage.

[0073] Silicon oxide has a relatively low dielectric constant, about 4.0, and can provide significantly reduced capacitance as the inter-layer dielectric for conductive interconnects.

[0074] Silicon carbide materials, including doped and undoped silicon carbide materials, can be used as insulating materials in integrated circuit applications, which not only provide a low dielectric constant but also provide step coverage, thermal stability, wet etch resistance, dry etch selectivity to oxides / nitrides, and high breakdown voltage. For example, the incorporation of oxygen atoms and / or nitrogen atoms can modulate the properties of the silicon carbide materials. In some embodiments, an oxygen-doped silicon carbide film can be used as an insulating material in integrated circuit applications, which provides a low dielectric constant, wet etch resistance to withstand device integration operations, and dry etch selectivity to oxides / nitrides.

[0075] In some semiconductor manufacturing processes, PVD, CVD, LPCVD, PECVD, hot-wire CVD, ALD, or PEALD, or any other suitable deposition method may be used to deposit silicon-based thin films. As used herein, the term silicon carbide includes undoped or doped silicon carbide, such as oxygen-doped silicon carbide (also known as silicon oxycarbide), nitrogen-doped silicon carbide (also known as silicon carbonitride), and nitrogen- and oxygen-doped silicon carbide (also known as silicon carbonitride). For many cases, the doped silicon carbide has at most about 50 atomic percent dopant atoms, whether these atoms are oxygen, nitrogen, or atoms of other elements. The doping level provides the desired film properties.

[0076] In some embodiments, a doped silicon layer may be formed as a vertical structure adjacent to a metal or semiconductor structure. For example, the doped silicon layer may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbonitride. Deposition of the doped silicon layer provides excellent step coverage along the sidewalls of the structure to create a vertical structure. PEALD may be suitable for forming a conformal layer. The PEALD process may include two consecutive steps: (a) self-limiting precursor adsorption on the substrate and (b) plasma conversion to the target film composition, which may be separated by a purge operation. Due to its self-limiting absorption and reaction mechanism, PEALD can achieve excellent conformal deposition in high aspect ratio (HAR) structures, including HAR gap filling applications in logic and memory integration, such as S / DTI (shallow / deep trench isolation) and memory holes in 3D-NAND. According to various embodiments, the method can be used to fill challenging structures, including extremely high aspect ratio (HAR) (>200:1) structures, structures with concave sidewall profiles, and smaller-sized structures with low-k dielectric materials. On the other hand, PEALD (or ALD) requires a longer deposition time, which results in lower throughput compared to other deposition processes such as PECVD (or CVD).

[0077] Forming a high-quality doped silicon thin film may pose certain challenges, such as providing a film with excellent step coverage, low dielectric constant, and / or high breakdown voltage. Other challenges may include composition control of the doped silicon layer after deposition. In some examples, the processing window for forming a doped silicon layer with a stoichiometric composition may be relatively narrow. For example, during the deposition process, unwanted oxidation may occur in the doped or undoped silicon carbide layer. Unwanted oxidation in the doped or undoped silicon carbide layer may increase the oxygen content and reduce the content of carbon or other non-oxygen elements in the doped or undoped silicon carbide layer. Deviations from the stoichiometric composition may affect the electrical properties in semiconductor devices containing the doped silicon layer.

[0078] One aspect of the present invention relates to a method of forming an amorphous silicon (a-Si) layer on a semiconductor substrate from one or more silicon-containing precursors by one of a variety of processes such as PVD, CVD, LPCVD, PECVD, hot-wire CVD, ALD, or PEALD. The one or more silicon-containing precursors may include at least one or more Si-Si bonds and / or Si-H bonds. For example, the silicon-containing precursor may include silane. The amorphous Si layer may have excellent step coverage to form a conformal layer. Subsequently, the amorphous Si layer may be exposed to a gas plasma stream generated by a plasma source. The plasma source may be a remote plasma source. The gas species in the gas plasma stream may include free radicals of one or more of carbon, oxygen, hydrogen, or nitrogen. One or more gas species in the gas plasma stream may be adsorbed to treat the amorphous Si layer. It should be understood that "treating" the amorphous-Si layer may be interpreted as doping the amorphous Si layer with one or more ions or free radicals in the gas plasma stream to convert the amorphous Si layer into a doped silicon layer. For example, one or more gas species in the gas plasma stream may be incorporated into the amorphous Si layer to convert the amorphous Si layer into a doped silicon layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride having a stoichiometric or non-stoichiometric composition.

[0079] In another aspect of the present invention, the amorphous Si layer may be exposed to one or more gas species at a high temperature to convert the amorphous Si layer into a crystalline silicon-containing layer. The one or more gas species may include one or more of the following: nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ), acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2)。In some embodiments, the high temperature can be at least about 200 °C, or between about 200 °C and about 650 °C. One or more gaseous species can be adsorbed on the amorphous Si layer to treat the amorphous Si layer. It should be understood that "treating" the amorphous Si layer can be interpreted as doping the amorphous Si layer with one or more gaseous species at a high temperature to convert the amorphous Si layer into a crystalline silicon-containing layer. For example, one or more gaseous species can be incorporated into the amorphous Si layer to convert the amorphous Si layer into a crystalline silicon-containing layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride, having a stoichiometric or non-stoichiometric composition.

[0080] In another aspect of the present invention, the above amorphous Si layer can be replaced with an amorphous boron (a-B) layer. The amorphous boron layer can be treated using a gas plasma stream of one or more gaseous species to convert the amorphous boron layer into a doped boron layer. The doped boron layer can include, for example, boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride having a stoichiometric or non-stoichiometric composition. Alternatively, the amorphous boron layer can be treated at a high temperature using one or more gaseous species to convert the amorphous boron layer into a crystalline boron-containing layer. The crystalline boron-containing layer can include, for example, boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride having a stoichiometric or non-stoichiometric composition.

[0081] Figure 1 Process flow diagram 100 for forming a doped silicon layer according to some embodiments is presented. Process flow diagram 100 depicts some embodiments of forming an amorphous Si layer on a substrate and treating the amorphous Si layer with a plasma source. The treatment can convert the amorphous Si layer into a silicon-based layer having two or more elements. In some embodiments, the silicon-based layer can include at least a partially crystalline structure. In some embodiments, the silicon-based layer can include a fully crystalline structure. It should be understood that, according to some embodiments, the formation of the amorphous Si layer and / or the treatment of the amorphous Si layer with a plasma source can be performed in a device having a remote plasma source or an in-situ plasma source.

[0082] In some embodiments, an amorphous boron (a-B) layer can be formed as an alternative to the amorphous Si layer and subsequently treated with a plasma source to convert the amorphous B layer into a doped boron layer having at least a partially crystalline structure. In some embodiments, the doped boron layer can include a fully crystalline structure.

[0083] In operation 102, a substrate is provided into the reaction chamber by a transfer system. In some embodiments, the substrate can be a semiconductor substrate. At least one or more regions of the substrate can include one or more features in which an amorphous Si layer will be deposited. For some embodiments, the one or more features can include high aspect ratio (HAR) trenches or other recessed features in 3D-NAND or logic devices. The substrate can be optionally cleaned before or after being provided into the reaction chamber and before depositing the amorphous Si layer thereon. For example, diluted hydrofluoric (HF) acid can be used to remove any contaminants or thin oxide layer on the substrate.

[0084] In operation 104, an amorphous Si layer can be formed on the substrate. Examples of techniques for forming the amorphous Si layer can include PVD, CVD, LPCVD, PECVD, hot-wire CVD, ALD, or PEALD. In some embodiments, the thickness of the amorphous Si layer can be controlled according to a predetermined deposition time to achieve a desired thickness. In some embodiments, the deposition time can be between about 5 seconds and about 500 seconds, or between about 10 seconds and about 200 seconds. In some embodiments, the desired thickness of the amorphous Si layer can be between about 0.1 nm and about 50 nm, between about 1 nm and about 30 nm, or between about 1 nm and about 20 nm. The deposition time can correspond to the desired thickness of the amorphous Si layer. The thickness can be controlled such that radicals and / or ions can penetrate sufficiently into the amorphous Si layer from subsequent plasma processing.

[0085] For some embodiments, the deposition of the amorphous Si layer can occur by flowing one or more silicon-containing precursors into the reaction chamber towards the substrate. The one or more silicon-containing precursors can adsorb on the surface of the substrate. The one or more silicon-containing precursors can be thermally decomposed under certain CVD operating conditions (e.g., 400°C - 650°C, 0.1 - 30 Torr) to form the amorphous Si layer. Thermal decomposition decomposes the silicon-containing precursor into atoms and / or molecules at high temperature for deposition on the substrate surface. Plasma-based deposition processes can result in non-conformal deposition of amorphous Si, but thermal decomposition of the silicon-containing precursor at a high enough temperature can provide highly conformal deposition of amorphous Si. For some embodiments, forming the amorphous Si layer by a PECVD process may require controlling the deposition pressure in the range of about 0.1 - 30 Torr, or about 0.5 - 20 Torr, or about 5 - 10 Torr. The substrate temperature during the deposition of the amorphous Si layer can be controlled between about 200°C and about 650°C, or between about 400°C and about 650°C. The amorphous Si layer can be highly conformal. After deposition, the step coverage of the amorphous Si layer can be at least 85%, at least 90%, or at least 98%.

[0086] For some embodiments in CVD or PECVD, a silicon-containing precursor can be continuously delivered to a substrate until a desired layer thickness is obtained. In other embodiments of ALD or PEALD, an amorphous Si layer can be formed by repeating: (1) pulse-delivering one or more silicon-containing precursors for a predetermined time, followed by (2) purging excess precursors. In some embodiments, the amorphous Si layer formed may not include long range order. Instead, the amorphous Si layer can have a continuous random network of silicon atoms.

[0087] As previously described, an amorphous Si layer according to some embodiments can provide a highly conformal amorphous Si layer. Without being bound by any theory, a silicon-containing precursor with a low sticking coefficient may be able to produce a highly conformal silicon layer. "Sticking coefficient" is a term used to describe the ratio of the number of adsorbed species (e.g., fragments or molecules) that adsorb / attach to a surface to the total number of species that impinge on that surface during the same time period. The symbol S c is sometimes used to refer to the sticking coefficient. The value of S c is between 0 (meaning no species adhere) and 1 (meaning all impinging species adhere). Multiple factors affect the sticking coefficient, including the type of impinging species, surface temperature, surface coverage, structural details of the surface, and the kinetic energy of the impinging species. Some substances are inherently "stickier" than others, making it more likely for them to adsorb to the surface each time the species impinges on the surface. These stickier substances have a larger sticking coefficient (all other factors being equal). In some cases, the sticking coefficient of the precursor (under relevant deposition conditions) can be about 0.05 or less, such as about 0.001 or less.

[0088] In some embodiments, the silicon-containing precursor can include at least one or more Si-Si bonds and / or one or more Si-H bonds. Silicon-containing precursors suitable for use according to the disclosed embodiments can include polysilanes (H 3 Si-(SiH 2 ) n -SiH 3 ), where n ≥ 0. Examples of silanes are silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, and the like.

[0089] In some embodiments, the silicon-containing precursor may further include a halosilane. A halosilane contains at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosecond-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane (thexyldimethylchlorosilane), and the like.

[0090] In some embodiments, the silicon-containing precursor may further include an aminosilane. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogen, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H 3 Si(NH 2 ) 2 Si(NH 2 ) 2 HSi(NH 2 ) 3 and Si(NH 2 ) 4 )), as well as substituted mono-, di-, tri-, and tetra-aminosilanes such as tert-butylaminosilane, methylaminosilane, tert-butyl silanamine, bis(tert-butylamino)silane (SiH 2 (NHC(CH 3 ) 3 ) 2 (BTBAS), tert-butylsilylcarbamate, SiH(CH 3 )-(N(CH 3 ) 2 ) 2 , SiHCl-(N(CH 3 ) 2 ) 2 , (Si(CH 3 ) 2 NH) 3 and the like. Further examples of aminosilanes are trisilylamine (N(SiH 3 ))). In some embodiments, an aminosilane having two or more amine groups attached to the central Si atom may be used. These may result in less damage compared to aminosilanes having only a single amine group attached.

[0091] Further examples of silicon precursors include trimethylsilane (3MS); ethylsilane; butasilane; pentasilane; octasilane; heptasilane; hexasilane; cyclobutasilane; cycloheptasilane; cyclohexasilane; cyclooctasilane; cyclopentasilane; 1,4-dioxa-2,3,5,6-tetrasilacyclohexane; diethoxymethylsilane (DEMS); diethoxysilane (DES); dimethoxymethylsilane; dimethoxysilane (DMOS); methyl-diethoxysilane (MDES); methyl-dimethoxysilane (MDMS); octamethoxydodecasiloxane (OMODDS); tert-butoxydisilane; tetramethylcyclotetrasiloxane (TMCTS); tetraoxymethylcyclotetrasiloxane (TOMCTS); triethoxysilane (TES); triethoxysiloxane (TRIES); and trimethoxysilane (TMS or TriMOS).

[0092] In some embodiments, the amorphous B layer can be deposited by any suitable process (including PVD, CVD, LPCVD, PECVD, hot-wire CVD, ALD, or PEALD) by providing one or more boron precursors. The deposition of the amorphous B layer can be carried out by flowing one or more boron precursors into the reaction chamber towards the substrate. The one or more boron precursors can adsorb on the surface of the substrate. The one or more boron precursors can thermally decompose the amorphous B layer under certain CVD operating conditions.

[0093] The boron-containing precursor can be a borane precursor that generally has the chemical formula B x H y In some embodiments, the borane precursor is borane (BH 3 ). In some embodiments, the borane precursor is diborane (B 2 H 6 ). In some embodiments, the borane precursor is a higher-order borane, such as triborane (B 3 H 7 ), tetraborane (B 4 H 10 ), pentaborane (B 5 H 9 ), hexaborane (B 6 H 10 ) or decaborane (B 10 H 14 ).

[0094] Boranes can form stable complexes, such as borane-amine complexes. For example, the borane-amine complex can include a dimethylamine borane complex ((CH 3 ) 2 NH:BH 3 ). Borane-amine complexes generally can have the chemical formula NR 3 :BH 3 , where R can be H or any combination of alkyl, allyl, alkenyl, alkynyl, alkaryl, aralkyl, phenyl, olefin, and alkyne ligands.

[0095] In some embodiments, the boron-containing precursor can be borazine that generally has the chemical formula B x H y N z . For example, the borazine precursor can have the chemical formula B 3 H 6 N 3 .

[0096] In addition to the gaseous substances, an inert carrier gas or a dilution gas can also flow to the environment adjacent to the substrate. Examples of the inert carrier gas or the dilution gas include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and nitrogen (N 2 ). In some embodiments, a gas mixture of one or more source gases and one or more inert carrier gases or dilution gases can be provided in a remote plasma source.

[0097] In operation 106, the amorphous Si layer can be exposed to a gas plasma stream to convert the amorphous Si layer into a doped silicon layer. In some embodiments, the gas plasma stream includes radical species and / or ions that can be generated in a remote plasma source. The remote plasma source can be separate from the reaction chamber. The remote plasma stream including the gas plasma stream can be introduced into the reaction chamber through a showerhead toward the surface of the substrate to convert the amorphous Si layer into a doped silicon layer. The doped silicon layer includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. The amorphous Si layer can be exposed to the gas plasma stream generated in the plasma source. In some embodiments, the plasma source can be an in-situ plasma source. In some embodiments, the plasma source can be a remote plasma source.

[0098] Source gases can be provided in the plasma source. The source gases can include gaseous species that include: nitrogen-containing reactants, which include nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ); hydrogen-containing reactants, which include hydrogen (H 2 ) or methane (CH 4 ); hydrocarbons, which include acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), or propylene (C 3 H 6 ); oxygen or oxide reactants, which include oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2 ), or a mixture thereof. The gaseous species can be determined based on one or more doping elements required to form the doped silicon layer. For example, nitrogen-containing reactants can be delivered to form a silicon nitride layer. In another example, carbon-containing reactants can be delivered to form a silicon carbide layer. For example, carbon- and nitrogen-containing reactants can be delivered to the amorphous Si layer to form silicon carbonitride. In another example, a silicon carbon oxide layer can be formed by exposing the amorphous Si layer to oxygen- and carbon-containing reactants. In yet another example, oxygen-, carbon-, and nitrogen-containing reactants can be delivered to the amorphous Si layer to form a silicon carbon oxynitride layer.

[0099] In one example, silicon nitride can be formed from the amorphous Si layer by providing one or more nitrogen-containing source gases (such as nitrogen (N 2 ), ammonia (NH 3 ), diazene (N2 H 2 ) hydrazine (N 2 H 4 ), or a combination thereof) to a remote plasma source such that nitrogen radicals are supplied to the amorphous Si layer to obtain. In another example, one or more carbon-containing reactants (e.g., hydrocarbons such as acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), or propylene (C 3 H 6 ), or a combination thereof) are supplied to the amorphous Si layer to obtain a silicon carbide layer. The resulting silicon nitride layer or silicon carbide layer does not necessarily include any unwanted phases, such as a silicon oxide layer, as confirmed by qualitative analysis such as Fourier transform infrared spectroscopy (FTIR).

[0100] When it is desired to obtain a doped silicon layer doped with two or more dopants, two or more different source gases can be supplied to the plasma source to generate a radical species containing different gaseous species. For example, carbon- and nitrogen-containing reactants can be supplied to convert the amorphous Si layer into a doped silicon layer doped with carbon and silicon. The relative amounts of carbon-silicon bonds and nitrogen-silicon bonds in the doped silicon layer can determine the composition of the doped silicon (e.g., silicon carbonitride) layer. The relative amounts of carbon-silicon bonds and nitrogen-silicon bonds can be determined by the composition and flow rate of the source gases, pressure, conversion time, RF power, or the like. In one example, the plasma conditions (e.g., RF power and / or frequency) can be adjusted to have an oxygen-doped silicon carbide layer with different oxygen contents, or a nitrogen- and oxygen-doped silicon carbide layer with different nitrogen contents.

[0101] In some embodiments, the composition of one or more source gases in the remote plasma can be controlled to adjust the composition of the doped silicon layer. For example, oxygen or an oxide reactant (e.g., oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), or a combination thereof) and the flow rate ratio of the carbon-containing reactant (e.g., acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 )) can be selected to be about (0.01 - 0.2):1, or about (0.05 - 1):1, or about 0.1:1 to obtain a silicon oxycarbide containing about 1 - 50% carbon (C) and about 1 - 50% oxygen (O).

[0102] In another example, to form a silicon carbonitride layer, a carbon-containing reactant (e.g., a hydrocarbon such as acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ) or a combination thereof) and a nitrogen-containing reactant (e.g., nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), hydrazine (N 2 H 4 ) or a combination thereof) may have a flow rate ratio of about (0.01 - 1):1 or about (0.05 - 1):1, or about (0.1 - 1):1, or about (0.5 - 1):1 to convert the amorphous Si layer into a silicon carbonitride layer containing about 1 - 40% carbon (C) and about 5 - 45% nitrogen (N). The resulting silicon carbonitride layer can be formed without introducing any unwanted oxide phases during the conversion, thus preventing degradation of the electrical properties for semiconductor devices.

[0103] In another example, to form a silicon oxynitride layer, an oxygen or oxide reactant (e.g., oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ) or a combination thereof) and a nitrogen-containing reactant (e.g., nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), hydrazine (N 2 H 4 ) or a combination thereof) may have a flow rate ratio of about (0.01 - 0.7):1, or about (0.02 - 0.5):1, or about (0.04 - 0.4):1 to convert the amorphous Si layer into a silicon oxynitride layer containing about 1 - 50% oxygen (O) and about 5 - 40% nitrogen (N).

[0104] In yet another example, to form a silicon carbon oxynitride layer, an oxygen or oxide reactant (e.g., oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ) or a combination thereof) and a carbon-containing reactant (e.g., a hydrocarbon such as acetylene (C 2 H 2 ), ethylene (C 2H 4 )), propylene (C 3 H 6 )) or a combination thereof) and a nitrogen-containing reactant (such as nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), hydrazine (N 2 H 4 ), or a combination thereof) can be optionally in a flow rate ratio of about (0.01 - 10):(1 - 10):10, or about (0.01 - 7):(1 - 8):10, or about (0.01 - 5):(1 - 5):10 (oxygen source: carbon source: nitrogen source) to obtain a silicon carbonitride oxide layer containing about 1 - 20% carbon (C), about 1 - 30% nitrogen (N), and about 1 - 40% oxygen (O).

[0105] In some embodiments of the present invention, the conformal silicon layer can be converted into a doped silicon layer. In some embodiments, the conformal silicon layer is a conformal amorphous silicon layer. One or more source gases containing one or more of nitrogen, oxygen, hydrogen, or carbon can be supplied to a remote plasma source to generate a gas plasma stream including free radical species and / or ions of one or more of nitrogen, oxygen, hydrogen, or carbon. The gas plasma stream can be generated in a remote plasma source separate from the reaction chamber. The remote plasma stream including the gas plasma stream can be introduced into the reaction chamber through a showerhead towards the surface of the substrate to convert the conformal silicon layer into a doped silicon layer. The doped silicon layer can be conformal.

[0106] The pressure in the reaction chamber of operation 106 can be adjusted to increase the ionization of one or more gaseous species in the source gas and reduce the residence time of free radicals. Reducing the residence time will reduce the effect of free radical recombination. Lower pressure makes the molecules move faster, which results in increased ionization of the source gas, reduced residence time, and reduced free radical recombination. In some embodiments, the pressure can be between about 0.2 Torr and about 10 Torr, or between about 1 Torr and about 3 Torr. However, it should be understood that the pressure in the reaction chamber during exposure to the gas plasma stream can be greater than 3 Torr or greater than 10 Torr, where other process conditions (e.g., inert carrier gas) result in sufficient ionization and reduced residence time.

[0107] The amorphous Si layer on the substrate can be exposed to the gas plasma stream for a predetermined time. In some embodiments, the predetermined time can be between about 2 seconds and about 100 seconds, or between about 5 seconds and about 50 seconds. The determination of the processing time can depend on the thickness of the amorphous Si layer, where a thicker layer may require a longer exposure time to the gas plasma stream.

[0108] In addition to time and pressure during exposure to the gas plasma stream, one or more process conditions can be controlled by adjusting one or more of RF power, source gas flow, source gas composition, and other process conditions can be adjusted during operation 106 to affect the characteristics of the remote plasma, which can thus result in different bond densities in the amorphous Si layer before or during conversion.

[0109] Deposition and conversion of the amorphous Si layer can be achieved using a cycle of deposition and conversion. Alternatively, deposition (operation 104) and conversion (operation 106) of the amorphous Si layer can be achieved using alternating cycles of deposition and conversion. Deposition and conversion can be performed in a layer-by-layer manner to allow each plasma conversion cycle to fully convert the deposited amorphous Si layer such that substantially the entire deposited amorphous Si layer is doped with radical species. In this way, the entire amorphous Si layer stack can be uniformly converted into a doped silicon layer and have a more uniform distribution of gaseous species across the thickness of the doped silicon layer. Thus, it should be understood that the deposition and conversion cycles to form the doped silicon layer can be continuously repeated until the desired thickness of the doped silicon layer is reached at operation 108.

[0110] For some embodiments, the conversion of the amorphous Si layer into a doped silicon layer can occur substantially simultaneously with exposing the amorphous Si layer to a gas plasma stream comprising one or more radical species. In some embodiments, radical species from one or more source gases are supplied to the surface of the amorphous Si layer, where bonds can form between silicon and gaseous species such as carbon, oxygen, hydrogen, or nitrogen. To form a nitrogen-doped silicon layer, nitrogen radicals in the gas plasma stream can adsorb to the surface of the amorphous Si surface. Subsequently, one or more nitrogen radicals can displace silicon atoms bonded to adjacent silicon atoms in the amorphous Si. Amorphous Si is a continuous irregular network of silicon atoms, where there is no long-range order and not all silicon atoms have a tetrahedral coordination. The amorphous Si layer can have short-range order of silicon atoms, and the bond energy between adjacent silicon atoms may not be as high as the Si–Si bonds in crystalline silicon. A small percentage of silicon atoms can be hydrogenated. Subsequently, nitrogen radicals can insert into the Si atom network and form Si–N bonds. Thus, nitrogen radicals from the gas plasma stream can be a source of dopants for the amorphous Si layer, thereby forming Si–N bonds in the amorphous Si layer. In the case of an amorphous Si layer doped with two different dopants (e.g., nitrogen and carbon), a gas plasma stream comprising carbon and nitrogen radicals can be transported to the surface of the amorphous Si layer, where the bonds between silicon atoms can be broken and carbon or nitrogen atoms will insert into the silicon network. Subsequently, Si–C bonds and Si–N bonds will form. The dopant density in the amorphous Si can depend on parameters such as the duration of the gas plasma stream on the substrate, the flow rate and concentration of the reactant gas, the plasma power, the pressure in the reaction chamber, and the temperature in the reaction chamber. For example, the number of silicon–dopant bonds can increase proportionally with the duration of the gas plasma stream on the substrate.

[0111] During the conversion from the amorphous Si layer into a doped silicon layer, the temperature in the environment adjacent to the substrate can be any suitable temperature that promotes the conversion reaction by doping one or more gaseous species into the amorphous Si layer, but is sometimes limited by the application of the device containing the doped silicon layer. In some embodiments, the temperature in the environment adjacent to the substrate can be controlled primarily by the temperature of the pedestal on which the substrate is supported during plasma processing. In some embodiments, the operating temperature can be between about 50 °C and about 650 °C. For example, in many integrated circuit applications, the operating temperature can be between about 250 °C and about 400 °C. In some embodiments, increasing the temperature can result in an increase in the number of bonds between silicon atoms and dopant atoms and a decrease in the number of Si–Si bonds. Increasing the temperature can also result in an increase in the crystallinity of the doped silicon layer.

[0112] In some embodiments, amorphous boron (a-B) can also be converted into a doped boron layer. The amorphous B layer can be deposited by suitable deposition methods, including PVD, CVD, LPCVD, PECVD, hot-wire CVD, ALD, or PEALD. In some embodiments, the amorphous B layer can be deposited by flowing one or more boron-containing precursors to adsorb on the substrate surface and thermally decomposing the one or more boron-containing precursors to form the amorphous B layer. The amorphous B layer can be exposed to a gas plasma stream including one or more of the radical species described herein to convert the amorphous B layer into a doped boron layer. In some embodiments, the amorphous B layer is exposed to a remote plasma stream. Specifically, exposure to a remote plasma stream involves at least generating a remote plasma of a source gas in a remote plasma source separate from the reaction chamber and introducing the remote plasma as a remote plasma stream into the reaction chamber through a showerhead. The source gas can include a nitrogen-containing reactant, a hydrogen-containing reactant, a hydrocarbon, an oxygen or oxide reactant, or a combination thereof. Due to exposure to the gas plasma stream, the amorphous B layer is converted into a doped boron layer. The doped boron layer can include boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride.

[0113] In some embodiments, the amorphous Si layer or the amorphous B layer can be converted into a doped silicon layer or a doped boron layer, respectively, by exposure to one or more of the gas species described herein in a controlled environment at elevated temperature. This can be done with or without exposure to plasma. Figure 2FIG. 200 presents a process flow diagram for forming a doped silicon layer according to some embodiments. Although FIG. 200 is described for forming a doped silicon layer by thermal conversion, it should be understood that FIG. 200 can also be applied to convert an amorphous B layer into a doped boron layer. In operation 202, a substrate is provided in a reaction chamber. In some embodiments, the substrate is a semiconductor substrate. In operation 204, an amorphous Si layer can be formed on the substrate by a suitable deposition process as described herein. In some embodiments, the amorphous Si layer can be deposited by flowing one or more silicon-containing precursors to adsorb on the surface of the substrate and thermally decomposing the one or more silicon-containing precursors to form the amorphous Si layer. The amorphous Si layer can be highly conformal. After deposition, the step coverage of the amorphous Si layer can be at least 85%, at least 90%, or at least 98%. In operation 206, the amorphous Si layer can be exposed to a controlled atmosphere at an elevated substrate temperature. For example, the amorphous Si layer can be exposed to one or more source gases, which include nitrogen, oxygen, hydrogen, carbon, or a combination thereof. The substrate temperature can be equal to or greater than about 200 °C, or can be in the range between about 200 °C and about 650 °C. The substrate on the pedestal can be heated by controlling one or more heating elements in the pedestal. The substrate can be heated to the desired temperature before providing one or more gas species to the substrate surface. The atmosphere can be controlled to include one or more gas species that reach and react with the amorphous Si layer on the substrate. After a predetermined period of time at a high temperature, the amorphous Si layer can be converted into a doped silicon layer. The doped silicon layer can be partially crystalline or fully crystalline. Thus, the doped silicon layer can be a crystalline silicon-containing layer. Operations 204 and 206 can be repeated until a doped silicon layer with the desired thickness in operation 208 is formed. In operation 208, the doped silicon layer can be a stack of partially or fully crystalline doped silicon layers. Although the process flow diagram 200 is shown to convert an amorphous Si layer into a doped silicon layer, it should be understood that the amorphous Si layer can be replaced with an amorphous B layer, and the doped silicon layer can be replaced with a doped boron layer.

[0114] In some embodiments, the composition of the doped layer can be determined by the composition and flow rate of one or more source gases. The doped silicon layer can include silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon nitrogen oxide, silicon carbon nitride, or silicon carbon nitrogen oxide. The doped boron layer can include boron carbide, boron nitride, boron oxide, boron nitrogen oxide, boron carbon oxide, boron carbon nitride, or boron carbon nitrogen oxide.

[0115] Upon thermal conversion, the gas species can dissociate to produce free atoms or gas molecules. For example, in forming boron nitride (BN), free atoms (N) and / or gas molecules (N 2) can be doped into the amorphous B layer to form a boron nitride layer. The conversion can start from the outermost layer of the amorphous layer and convert the amorphous layer into an at least partially crystalline layer. The thickness of the doped silicon or doped boron layer on the substrate can be adjusted by controlling the time period of the thermal conversion.

[0116] Figure 3A A figure showing a Fourier transform infrared (FTIR) absorption spectrum with vibration peaks, which is used to detect the bond types in silicon nitride layers processed under different conditions. Figure 3A Two Si-N peaks with different intensities are shown, both indicating the formation of Si-N bonds in silicon nitride. The increase in the Si-N peak intensity (B) compared to the Si-N peak (A) may be due to an increase in nitrogen-containing radicals and / or ions impinging on the surface of the amorphous Si layer. That is, a higher peak intensity can correspond to a greater number of Si-N bonds per volume. An increase in carbon-containing radicals and / or ions can be obtained by controlling various parameters such as plasma power (current and / or voltage), treatment duration, source gas flow rate, etc. For example, as the plasma power increases, more nitrogen-containing radicals can impinge on and dope the amorphous Si layer. Figure 3B A Fourier transform infrared (FTIR) absorption spectrum with vibration peaks is shown, which is used to detect the bond types in silicon carbide layers processed under different treatment conditions. Similar to Figure 3A the silicon nitride layer shown, Figure 3B the increased Si-C peak intensity (in the direction of the arrow) corresponds to an increased Si-C bond density in the silicon carbide layer processed by a remote plasma source.

[0117] The conversion of an amorphous Si layer into a doped silicon layer according to some embodiments can have the following advantages. The doped silicon layer obtained according to some embodiments can form a conformal layer required for manufacturing HAR features in semiconductor devices. Tunability of the composition in the processed silicon layer doped with two or more dopants is also possible. For example, silicon oxide can be thermodynamically stable and is typically formed during the deposition of silicon-based layers. On the other hand, according to some embodiments, depending on the desired composition of the doped silicon, the formation of the silicon oxide phase in the doped silicon layer can be controlled. Further, forming a doped silicon layer according to some embodiments of the present invention has a faster throughput than conventional ALD processes.

[0118] The methods described herein can also be used on memory arrays for programmable data storage. For example, dynamic random access memory (DRAM) is commonly used for programmable memory storage. DRAM typically will be formed as an array of individual memory cells, where each memory cell includes a transistor and a memory storage device. The memory storage device will typically be a capacitor. The transistor will be formed within a word line that extends through the DRAM array. A series of bit lines will also be provided over the DRAM array. By activating a particular combination of word lines and bit lines, information bits are written to or read from the memory storage device of an individual DRAM cell. Thus, each memory device of the DRAM array can be specifically addressed using an appropriate combination of word lines and bit lines.

[0119] In the production of DRAM applications, a deposition process can be utilized to form bit line interconnects made of a conductive material. The conductive material can be formed over a semiconductor material such as polysilicon. In some embodiments, the conductive material is shaped as a conductive wire by being formed within a trench. After forming the bit line interconnects, an insulating cap can be formed over the bit line interconnects. The conductive wires or bit lines can be separated from each other at least by a dielectric spacer material.

[0120] Although some aspects described herein are particularly useful in DRAM array fabrication, it should be understood that the present invention is not limited to DRAM arrays. The present invention can be applied to other semiconductor manufacturing processes that would be recognized by one of ordinary skill in the art.

[0121] Figure 4A A cross-sectional schematic view of an exemplary semiconductor device structure is shown with a spacer layer uniformly deposited over a dielectric cover layer and a conductive layer of a semiconductor device structure. The semiconductor device structure 400 can be part of a memory device such as, for example, a DRAM array. In some examples, the semiconductor device structure 400 can be a bit line interconnect structure within a DRAM array. The semiconductor device structure 400 can include a stack of materials formed on a semiconductor substrate. The stack can include a semiconductor layer 402, a conductive layer 404 over the semiconductor layer 402, and a dielectric cover layer 406 over the conductive layer 404. The semiconductor layer 402 can be composed of polysilicon or other suitable semiconductor material. The conductive layer 404 can include a conductive material such as, for example, tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), hafnium (Hf), cobalt (Co), chromium (Cr), nickel (Ni), platinum (Pt), ruthenium (Ru), copper (Cu), aluminum (Al), or an alloy thereof. In some embodiments, the conductive layer 404 includes tungsten or tungsten nitride. In some embodiments, the conductive layer 404 includes tungsten or molybdenum. As used herein, a conductive layer includes having 1×10 at room temperature -5Any material with a resistivity of Ω-m or less. The conductive layer 404 can be used as a bit line conductive layer. The dielectric capping layer 406 can include an electrically insulating material, such as a nitride or an oxide. Examples include silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ) or a combination thereof. Other examples include amorphous carbon (a-C) hard masks or silicon-based hard masks, such as silicon carbide (SiC) or silicon oxycarbide. In some embodiments, the dielectric capping layer 406 includes silicon nitride. The dielectric capping layer 406 can be used as a bit line hard mask.

[0122] A stack of the semiconductor layer 402, the conductive layer 404, and the dielectric capping layer 406 can be formed as non-planar features or vertical structures on a semiconductor substrate. The spacer layer 408 can be deposited on the semiconductor device structure 400 including the exposed surfaces of the semiconductor layer 402, the conductive layer 404, and the dielectric capping layer 406. The spacer layer 408 can also be referred to as a capping layer or a capping film. In some embodiments, the spacer layer 408 includes a low-k dielectric material, where the low-k dielectric material has a dielectric constant equal to or less than about 5.0. In some embodiments, the spacer layer 408 includes a silicon-containing material, such as a silicon nitride film, a silicon carbide film, a silicon oxide film, a silicon oxycarbide film, or a silicon carbonitride film. For example, the spacer layer 408 can be composed of a silicon oxycarbide film, where the silicon oxycarbide film can have a dielectric constant between about 2.5 and about 4.5 or between about 3.5 and about 4.4.

[0123] The spacer layer 408 can be conformally deposited on the semiconductor device structure 400. The conformal deposition of the spacer layer 408 results in the spacer layer 408 being deposited relatively uniformly on the sidewalls and the top surface of the semiconductor device structure 400. The conformal deposition can be performed using any suitable deposition technique (e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD)). Thus, the spacer layer 408 can be deposited substantially uniformly on the conductive layer 404 and the dielectric capping layer 406. As device dimensions shrink and the aspect ratio becomes increasingly high, the uniform deposition of the spacer layer 408 on the semiconductor device structure 400 (e.g., a memory device structure) becomes increasingly important.

[0124] However, the spacer layer may be deposited non-uniformly on the dielectric capping layer relative to the conductive layer due to the effect of nucleation delay. The growth of some spacer materials may have a different nucleation delay on a dielectric surface (such as silicon nitride) than on a conductive surface (such as tungsten). The difference in nucleation delay results in a different amount of material growth on the dielectric surface relative to the conductive surface. In fact, when depositing a spacer material (such as silicon oxycarbide), there is a greater nucleation delay on the tungsten surface than on the silicon nitride surface. This can occur even when applying conformal deposition techniques (such as ALD).

[0125] Figure 4B A cross-sectional schematic view of an exemplary semiconductor device structure is shown in which a spacer layer is deposited non-uniformly on a dielectric capping layer and a conductive layer of a semiconductor device structure due to the effect of nucleation delay. The semiconductor device structure 410 can be part of a memory device such as a DRAM array. In some cases, the semiconductor device structure 410 can be a bit line interconnect structure in a DRAM array. The semiconductor device structure 410 can include a stack of materials formed on a semiconductor substrate. The stack can include a semiconductor layer 412, a conductive layer 414 above the semiconductor layer 412, and a dielectric capping layer 416 above the conductive layer 414.

[0126] The stack of the semiconductor layer 412, the conductive layer 414, and the dielectric capping layer 416 can be formed as a non-planar feature or a vertical structure on the semiconductor substrate. A spacer layer 418 can be deposited on the semiconductor device structure 410 including the exposed surfaces of the semiconductor layer 412, the conductive layer 414, and the dielectric capping layer 416. In some embodiments, the spacer layer 418 includes a low-k dielectric material such as silicon oxycarbide. The spacer layer 418 can be deposited on the exposed surface of the conductive layer 414 (such as tungsten) and the exposed surface of the dielectric capping layer 416 (such as silicon nitride), where the average thickness of the spacer layer 418 on the dielectric capping layer 416 is greater than the average thickness of the spacer layer 418 on the conductive layer 414. Even when using a conformal deposition technique (such as ALD) to deposit the spacer layer 418, the effect of nucleation delay may still result in non-uniform deposition of the spacer layer 418 on the dielectric capping layer 416 relative to the conductive layer 414. In some embodiments, the effect of nucleation delay can alternatively or additionally result in non-uniform deposition of the spacer layer 418 on the semiconductor layer 412 relative to the conductive layer 414. Thus, the deposition rate of the spacer layer 418 on the conductive layer 414 is slower relative to one or both of the dielectric capping layer 416 and the semiconductor layer 412. In some cases, this may be partly due to the slow nucleation rate on the tungsten surface. Nucleation delay not only causes non-uniform deposition of the spacer material on the semiconductor device structure 400, but nucleation delay may also ultimately lead to a reduction in device performance or even device failure.

[0127] To reduce the effect of nucleation delay for certain spacer materials, an initial layer can be deposited on the exposed surfaces of the dielectric capping layer and the conductive layer. In some cases, the initial layer can also be deposited on the exposed surface of the semiconductor layer. The initial layer can be a thin or ultra-thin layer conformally deposited on a stack including at least the dielectric capping layer and the conductive layer to provide a uniform and consistent surface on which the spacer material can grow. In other words, since the surface on which the spacer material grows is the same, the spacer material can grow uniformly on the initial layer.

[0128] Not all types of initial layers perform equally. Some initial layers may still result in non-uniform growth of the spacer material on the dielectric capping layer relative to the conductive layer. For example, depositing silicon oxycarbide as the spacer material on a silicon dioxide initial layer may still result in more deposition (i.e., greater thickness) on the silicon nitride capping layer relative to the tungsten conductive layer. Thus, some silicon dioxide initial layers may not be sufficient to reduce the effect of nucleation delay. Additionally, some initial layers may degrade the electrical properties of the conductive layer. For example, depositing silicon oxycarbide as the spacer material on a silicon nitride initial layer can sufficiently reduce the effect of nucleation delay, but the silicon nitride initial layer may degrade the electrical properties of the tungsten conductive layer due to nitridation.

[0129] In addition to the performance limitations of certain initial layers, conformal deposition techniques (such as ALD) can be slow and reduce throughput. As device structures shrink and high aspect ratio features become common in the semiconductor industry, the ability to deposit conformal films will continue to be important. ALD is a very suitable film deposition technique for depositing conformal films. ALD utilizes surface-mediated deposition reactions to deposit films in a layer-by-layer manner. Although ALD can achieve a highly conformal initial layer in high aspect ratio features, it can be too slow to obtain the desired thickness compared to other deposition techniques.

[0130] The present invention relates to conformal deposition of an initial layer, where the initial layer can be amorphous silicon, amorphous boron, doped silicon, or doped boron. Doped silicon can be converted from amorphous silicon, and doped boron can be converted from amorphous boron. The initial layer is a layer deposited on at least two different materials such that subsequent materials grow on the surface of the same material. Amorphous silicon or amorphous boron is conformally deposited by CVD (such as thermal CVD). Amorphous silicon or amorphous boron is deposited on one or more semiconductor device structures of a semiconductor substrate, where each semiconductor device structure includes at least a dielectric layer on a conductive layer. In some embodiments, each semiconductor device structure further includes a semiconductor layer, where the conductive layer is formed on the semiconductor layer. In some embodiments, the one or more semiconductor device structures are memory device structures, where the conductive layer includes tungsten or molybdenum, and the dielectric layer includes silicon nitride. A spacer layer is deposited on the initial layer, where the spacer layer can be deposited substantially uniformly on the dielectric layer and the conductive layer of each semiconductor device structure. The deposition of the spacer layer and amorphous silicon or amorphous boron can occur in the same processing chamber, where the spacer layer and amorphous silicon or amorphous boron are deposited by a CVD-based process. In some embodiments, amorphous silicon is used as the initial layer. In some other embodiments, doped silicon is used as the initial layer, where the doped silicon is formed by exposing amorphous silicon to a plasma to convert the amorphous silicon into silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride. In some embodiments, amorphous boron is used as the initial layer. In some other embodiments, doped boron is used as the initial layer, where the doped boron is formed by exposing amorphous boron to a plasma to convert the amorphous boron into boron carbide, boron nitride, boron oxide, boron oxynitride, boron carbonitride, or boron carbon oxynitride.

[0131] The initial layer of the present invention offers many advantages. In particular, the initial layer provides an improved surface for growing spacer materials (such as low-k dielectric spacer materials (e.g., silicon carbonitride)). Thus, the low-k dielectric spacer materials can be deposited relatively uniformly on the dielectric material and the conductive material. The initial layer also does not deteriorate the electrical properties of the underlying conductive material (such as tungsten). Additionally, the initial layer of the present invention can be conformally deposited at a deposition rate faster than conventional conformal deposition techniques (such as ALD).

[0132] In some embodiments of the present invention, the initial layer disposed on one or more semiconductor device structures for depositing / growing spacer materials is conformal amorphous silicon, which is described in the process flow of Figure 5 In alternative embodiments of the present invention, the initial layer disposed on one or more semiconductor device structures for depositing / growing spacer materials is conformal doped silicon rather than conformal amorphous silicon, which is described in the process flow of Figure 6 In some other alternative embodiments of the present invention, the initial layer disposed on one or more semiconductor device structures for depositing / growing spacer materials is conformal amorphous boron or conformal doped boron.

[0133] Figure 5 A flowchart showing an exemplary method of forming a spacer layer on one or more semiconductor device structures in accordance with some embodiments is shown. The operations of process 500 may be performed in a different order and / or with different, fewer, or additional operations. One or more operations of process 500 may be performed using Figure 9 or Figure 10 the substrate processing apparatus shown. In some embodiments, the operations of process 500 may be implemented at least in part in accordance with software stored in one or more non-transitory computer-readable media.

[0134] In block 510 of process 500, a semiconductor substrate is provided having one or more semiconductor device structures, where each semiconductor device structure includes at least a dielectric overlay above a conductive layer. In some embodiments, each semiconductor device structure includes a semiconductor layer such as polysilicon, where the conductive layer is located above the semiconductor layer. The semiconductor substrate is provided in a processing chamber. The semiconductor substrate may be supported on a substrate support or pedestal in the processing chamber. The semiconductor substrate may be a patterned substrate having one or more features. The one or more features may be high aspect ratio features, where a high aspect ratio feature has an aspect ratio of depth to width that is equal to or greater than about 10:1, equal to or greater than about 15:1, equal to or greater than about 20:1, equal to or greater than about 25:1, equal to or greater than about 30:1, equal to or greater than about 40:1, equal to or greater than about 50:1, or equal to or greater than about 100:1. In some instances, each of the one or more features may be a recessed feature formed between paired semiconductor device structures. For some embodiments, the one or more recessed features include high aspect ratio trenches in 3D-NAND.

[0135] The processing chamber provides a sealed space for depositing an initial layer on a substrate. In some cases, the processing chamber is also used to deposit a spacer layer on the initial layer. Using the same processing chamber for depositing the initial layer and the subsequent spacer layer minimizes the air break between substrate transfer and handling. The chamber walls in the processing chamber can be made of stainless steel, aluminum, plastic, ceramic, or other suitable materials. The processing chamber can include a substrate support (e.g., a pedestal or an electrostatic chuck) on which a semiconductor substrate is supported. In some embodiments, the processing chamber can include one or more heating elements for controlling the temperature of the substrate, where the one or more heating elements can be infrared (IR) lamps, light-emitting diodes (LEDs), or resistive heaters located in the substrate support. The processing chamber can include one or more gas lines for delivering gases into the processing chamber. For example, the one or more gas lines can include a showerhead for supplying process gases toward the semiconductor substrate in the processing chamber. In some embodiments, the processing chamber can be coupled to a plasma generation chamber that is separate from the processing chamber. The plasma generation chamber (e.g., a remote plasma chamber) can be an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor. In some cases, the processing chamber further includes one or more gas outlets for exhausting gases, which may or may not be coupled to a vacuum pump to maintain a desired pressure inside the processing chamber. In some embodiments, the processing chamber for depositing amorphous silicon can be the same as the processing chamber for converting the amorphous silicon into a doped silicon layer.

[0136] In some embodiments, the conductive layer can include a conductive material such as tungsten, tantalum, titanium, molybdenum, hafnium, cobalt, chromium, nickel, platinum, ruthenium, copper, aluminum, or an alloy thereof. For example, the conductive layer includes tungsten or tungsten nitride, or the conductive layer includes tungsten or molybdenum. In some embodiments, the dielectric capping layer can include an electrically insulating material such as a nitride or an oxide. For example, the dielectric capping layer can include silicon nitride, silicon oxide, aluminum oxide, silicon carbide, silicon oxycarbide, amorphous carbon, or a combination thereof.

[0137] In some embodiments, the one or more semiconductor device structures include memory device structures that are part of a memory array. For example, the one or more semiconductor device structures are DRAM bit structures that are part of a DRAM array. The DRAM bit structure can be a vertically oriented structure having at least bit lines. The DRAM bit structure can also include a capping layer on the bit lines, such as a nitride capping layer, where the capping layer is used to cover and isolate the bit lines. The capping layer can also be used as a hard mask for the bit lines. The DRAM bit structure can also include a semiconductor layer (e.g., polysilicon) below the bit lines, where the bit lines are electrically coupled to transistors at the semiconductor layer. The DRAM bit structure can include a plurality of vertically oriented structures in the DRAM array that have at least bit lines as conductive layers, a capping layer as a dielectric overlay above the bit lines, and a semiconductor layer below the bit lines. The DRAM bit structures can be spaced apart by recessed features (e.g., trenches), where the recessed features can have an aspect ratio of depth to width that is equal to or greater than about 10:1, equal to or greater than about 20:1, or equal to or greater than about 50:1.

[0138] In block 520 of process 500, an initial amorphous silicon layer is conformally deposited on the dielectric overlay and conductive layers of the one or more semiconductor device structures. Amorphous silicon (a-Si), as opposed to crystalline silicon, is non-crystalline and lacks long-range order. An "initial layer" is a thin or ultra-thin layer of material formed on the surface of at least two different materials to provide a single material surface on which subsequent depositions can be made. The thin layer can be defined as a layer having a thickness equal to or less than about thickness, while the ultra-thin layer can be defined as a layer having a thickness equal to or less than about thickness. For example, the initial amorphous silicon layer can have a thickness equal to or less than about equal to or less than about or between about and about The initial amorphous silicon layer is a thin or ultra-thin layer of amorphous silicon conformally deposited on the surfaces of at least two different materials and serves as a single material surface on which subsequent layers (e.g., spacer layers) can be deposited.

[0139] The initial amorphous silicon layer can be deposited on the one or more semiconductor device structures by CVD, PECVD, ALD, PEALD, or other suitable deposition techniques. In some embodiments, the initial amorphous silicon layer is deposited by CVD via a thermal decomposition process. The thermal decomposition process is initiated by activating a precursor gas species at a high temperature, where the precursor gas species is thermally decomposed into atoms and / or molecules by CVD for deposition.

[0140] In some embodiments, the thickness of the initial amorphous silicon layer can be controlled according to a predetermined deposition time to achieve a desired thickness. In some embodiments, the deposition time can be between about 5 seconds and about 500 seconds, or between about 10 seconds and about 200 seconds. In some embodiments, the desired thickness of the initial amorphous silicon layer can be between about and about , between about and about , or between about and about . The deposition time can correspond to the desired thickness of the initial amorphous silicon layer. The thickness can be controlled such that radicals and / or ions from subsequent remote plasma treatment can sufficiently penetrate into the initial amorphous silicon layer.

[0141] For some embodiments, the deposition of the initial amorphous silicon layer can occur by flowing one or more silicon-containing precursors into a processing chamber towards a semiconductor substrate. The silicon-containing precursor is delivered to the substrate surface where it is adsorbed by the semiconductor substrate to form a highly conformal initial amorphous silicon layer. In some embodiments, forming the initial amorphous silicon layer by CVD may require controlling the deposition pressure in the range of 0.1 Torr to 30 Torr or 0.5 Torr to about 10 Torr. The substrate temperature during amorphous silicon deposition can be controlled between about 300 °C and about 700 °C, between about 400 °C and about 650 °C, or between about 450 °C and about 600 °C. After deposition, the step coverage of the initial amorphous silicon layer can be at least about 85%. In some embodiments, the step coverage can be at least about 90%, at least about 95%, or at least about 98%. As used herein, the step coverage can be calculated by comparing the average thickness of the deposited film on the bottom, sidewall, or top of a feature with the average thickness of the deposited film on another part of the feature. For example, the step coverage can be calculated by dividing the average thickness of the deposited film on the sidewall by the average thickness of the deposited film at the top of the feature and multiplying by 100 to obtain a percentage.

[0142] For some embodiments of CVD or PECVD, the silicon-containing precursor can be continuously delivered to the semiconductor substrate until the desired thickness is obtained. In other embodiments of ALD or PEALD, the initial amorphous silicon layer can be formed by repeating: (1) pulse-delivering one or more silicon-containing precursors for a predetermined time, followed by (2) purging the excess precursor. The initial amorphous silicon layer may not include long-range order; rather, the amorphous silicon layer can have a continuous irregular network of silicon atoms.

[0143] As previously described, the initial amorphous silicon layer can be highly conformal. Without being bound by any theory, a silicon-containing precursor with a low adhesion coefficient may be able to produce a highly conformal amorphous silicon layer. In some cases, the adhesion coefficient of the precursor (under relevant deposition conditions) can be about 0.05 or less, such as about 0.001 or less.

[0144] In some embodiments, the silicon-containing precursor may include at least one or more Si-Si bonds and / or one or more Si-H bonds. Silicon-containing precursors suitable for use according to the disclosed embodiments may include polysilanes (H 3 Si-(SiH 2 ) n --SiH 3 )n, where n≥0. Examples of silanes are silane (SiH 4 4), disilane (Si 2 2H 6 6), trisilane (Si 3 3H 8 8) and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane and the like. In some embodiments, the one or more silicon-containing precursors include silane, disilane or trisilane.

[0145] In some embodiments, the silicon-containing precursor may further include halosilanes. Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilane, bromosilane, chlorosilane and fluorosilane. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane (thexyldimethylchlorosilane) and the like.

[0146] In some embodiments, the silicon-containing precursor may further include aminosilanes. Aminosilanes include at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogen and carbon. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilanes (H 3 3Si(NH 2 2)2, H 2 2Si(NH 2 2)3, HSi(NH 2 2)4 and Si(NH 2 2)4), and substituted mono-, di-, tri- and tetra-aminosilanes such as tert-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH 3 (NHC(CH 2 3)3)2, and the like. 4 )4), and substituted mono-, di-, tri- and tetra-aminosilanes such as tert-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH 2 (NHC(CH 3 )3)2, and the like.3 ) 2 (BTBAS), tert-butylsilylcarbamate, SiH(CH 3 )-(N(CH 3 ) 2 ) 2 , SiHCl-(N(CH 3 ) 2 ) 2 , (Si(CH 3 ) 2 NH) 3 , diisopropylaminosilane, di-sec-butylaminosilane, and the like. Further examples of aminosilanes are trisilylamine (N(SiH 3 ))). In some embodiments, aminosilanes having two or more amine groups attached to the central Si atom can be used. These can result in less damage compared to aminosilanes having only a single amine group attached.

[0147] Further examples of silicon precursors include trimethylsilane (3MS); ethylsilane; butasilane; pentasilane; octasilane; heptasilane; hexasilane; cyclobutasilane; 1-dimethylamino-1,1,5,5,5-pentamethyldisiloxane; cycloheptasilane; cyclohexasilane; cyclooctasilane; cyclopentasilane; 1,4-dioxa-2,3,5,6-tetrasilacyclohexane; diethoxymethylsilane (DEMS); diethoxysilane (DES); dimethoxymethylsilane; dimethoxysilane (DMOS); methyl-diethoxysilane (MDES); methyl-dimethoxysilane (MDMS); octamethoxydodecasiloxane (OMODDS); tert-butoxydisilane; tetramethylcyclotetrasiloxane (TMCTS); tetraoxymethylcyclotetrasiloxane (TOMCTS); triethoxysilane (TES); triethoxysiloxane (TRIES); and trimethoxysilane (TMS or TriMOS).

[0148] In addition to the precursor gas, an inert carrier gas or diluent gas may also flow to the semiconductor substrate. Examples of inert carrier gases or diluent gases include, but are not limited to, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and nitrogen (N 2)。In some embodiments, a gas mixture of one or more source gases and one or more inert carrier gases or diluent gases may be provided.

[0149] For example, one or more silicon-containing precursors include silane, disilane, trisilane, or other silane-based precursors. The silane-based precursors may flow into the processing chamber and adsorb on the exposed surface of the semiconductor substrate. The silane-based precursors may thermally decompose under certain CVD operating conditions (e.g., 400 °C - 650 °C, 0.1 - 30 Torr) to form an amorphous silicon initial layer. Thermal decomposition decomposes the silane-based precursors into atoms and / or molecules at high temperatures for deposition on the surface of the semiconductor substrate. Plasma-based deposition processes may result in non-conformal deposition of amorphous silicon, but thermal decomposition of silane-based precursors at sufficiently high temperatures provides highly conformal deposition of amorphous silicon.

[0150] The amorphous silicon initial layer is conformally deposited on the exposed surfaces of the one or more semiconductor device structures, including the exposed surfaces of the conductive layer and the dielectric capping layer. This may include the sidewalls of the conductive layer, the sidewalls of the dielectric capping layer, and the top surface of the dielectric capping layer. This may also include the sidewalls of the semiconductor layer. The amorphous silicon initial layer may be deposited on both the horizontal and vertical surfaces of the one or more semiconductor device structures. It should be noted that the term "vertical" as used herein includes surfaces that are close to 90° and completely vertical with respect to the plane. For example, a vertical surface may deviate from 90° by + / - 10° or + / - 5° or + / - 1° or + / - 0.5°. Similarly, a horizontal surface may vary from 180° by + / - 5° or + / - 1° or + / - 0.5°.

[0151] In some embodiments, an amorphous boron initial layer may be formed as an alternative to the amorphous silicon initial layer. Like the amorphous silicon initial layer, the amorphous boron initial layer may be highly conformal. The amorphous boron initial layer may have a thickness equal to or less than about equal to or less than about or about and about The amorphous boron initial layer may be deposited using a suitable deposition process (e.g., thermal CVD). As used herein, thermal CVD may refer to a non-plasma chemical vapor deposition process in which the deposition of the reactants is at least partially driven by thermal energy. In some cases, the amorphous boron initial layer is deposited using a boron-containing precursor such as borane (BH 3 )), diborane (B 2 H 6 )), or triborane (B 3 H 7 ). Other examples of boron-containing precursors include higher-order boranes such as tetraborane (B 4 H 10 ), pentaborane (B 5 H 9) Hexaborane (B 6 H 10 ) or decaborane (B 10 H 14 ). In some embodiments, the boron-containing precursor comprises a borazine having the chemical formula B x H y N z .

[0152] In block 530 of process 500, a spacer layer is deposited on the initial amorphous silicon layer. It should be understood that in some alternative embodiments of process 500, the spacer layer is deposited on the initial amorphous boron layer. The spacer layer can be a dielectric material, such as a low-k dielectric material. As used herein, a "low-k dielectric material" can have a dielectric constant equal to or less than about 5.0 or equal to or less than about 4.0. In some embodiments, the spacer layer comprises a silicon-containing layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. For example, the spacer layer comprises silicon oxycarbide. In some other embodiments, the spacer layer comprises a boron-containing layer, such as boron carbide, boron nitride, boron oxide, boron oxynitride, boron oxycarbide, boron carbonitride, or boron carbon oxynitride. When the one or more semiconductor device structures include a plurality of semiconductor device structures separated by recessed features, the spacer layer can separate / isolate the semiconductor device structures from each other. In some aspects, the spacer layer can be used to electrically isolate adjacent bit lines in a memory array.

[0153] The spacer layer can be deposited at least above the dielectric capping layer and the conductive layer, wherein the initial amorphous silicon layer is disposed between the spacer layer and the dielectric capping layer and between the spacer layer and the conductive layer. The spacer layer can be deposited uniformly or at least substantially uniformly above the dielectric capping layer and the conductive layer. As used herein, "substantially uniformly" depositing above the dielectric capping layer and the conductive layer means that the average thickness of the spacer layer above the dielectric capping layer differs from the average thickness of the spacer layer above the conductive layer by within + / - 10%. This means that the amount of spacer material deposited above the conductive layer is approximately the same as the amount of spacer material deposited above the dielectric capping layer. In some embodiments, the spacer layer is deposited uniformly or at least substantially uniformly above the dielectric capping layer, the conductive layer, and the semiconductor layer of the one or more semiconductor device structures.

[0154] The amorphous silicon initial layer promotes the nucleation and growth of the spacer layer at least over the dielectric capping layer and the conductive layer of the one or more semiconductor device structures. Although the growth of the spacer layer over the conductive layer (e.g., tungsten) may be inhibited or slowed relative to the dielectric capping layer, the amorphous silicon promotes the uniform growth of the spacer layer over both the conductive layer and the dielectric capping layer. Thus, the amorphous silicon initial layer reduces the nucleation delay in the conductive layer. Additionally, the amorphous silicon initial layer does not adversely affect the electrical properties of the conductive layer. In some cases, the resistance of the conductive layer is maintained or even improved using the amorphous silicon initial layer.

[0155] The deposition of the spacer layer and the amorphous silicon initial layer can occur in the same processing chamber. This avoids unnecessary vacuum interruptions that may expose the semiconductor substrate to harmful materials or particles between substrate transfers. This also reduces processing time, reduces processing steps, lowers costs, and increases throughput. The processing chamber can be configured for CVD-based deposition processes, including the deposition of the amorphous silicon initial layer and the spacer layer. For example, the amorphous silicon initial layer can be deposited in the processing chamber by thermal CVD, while the spacer layer can be deposited in the same processing chamber by remote plasma CVD.

[0156] When depositing amorphous silicon by thermal CVD, the one or more semiconductor device structures can be exposed in the processing chamber to a silane-based precursor, and heat energy is applied in the processing chamber to thermally decompose the silane-based precursor, thereby depositing the amorphous silicon initial layer. The processing chamber can be equipped to supply the silane-based precursor and use one or more heating elements to apply heat energy to control the temperature of the semiconductor substrate. The one or more heating elements can apply heat energy by heating the semiconductor substrate to a temperature between about 400 °C and about 650 °C. When depositing the spacer layer (e.g., silicon oxycarbide) by remote plasma CVD, the one or more semiconductor device structures can be exposed in the processing chamber to a silicon-containing precursor, radicals of a source gas (e.g., a hydrogen source gas) are generated in a remote plasma source located upstream of the processing chamber, and the radicals of the source gas are introduced into the processing chamber and directed towards the semiconductor substrate to react with the silicon-containing precursor to form the spacer layer. In some embodiments, the radicals of the source gas include radicals of hydrogen. The radicals of hydrogen can interact with the silicon-containing precursor at a location downstream of the remote plasma source to activate the silicon-containing precursor in the environment adjacent to the semiconductor substrate, thereby depositing the spacer layer.

[0157] The silicon-containing precursor may include one or more Si-H bonds and / or one or more Si-Si bonds. In some embodiments, the silicon-containing precursor further includes one or more Si-O bonds, one or more Si-N bonds, and / or one or more Si-C bonds. To deposit silicon oxycarbide, the silicon-containing precursor may include one or both of Si-O and Si-C bonds. In some embodiments, the silicon-containing precursor may be a siloxane. In some embodiments, the siloxane may be cyclic. Cyclic siloxanes may include cyclic tetrasiloxanes such as 2,4,6,8-tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), and heptamethylcyclotetrasiloxane (HMCTS). Other cyclic siloxanes may also include, but are not limited to, cyclotrisiloxane and cyclopentasiloxane. In some embodiments, the siloxane may be branched. Examples of suitable linear siloxanes include, but are not limited to, disiloxanes such as pentamethyldisiloxane (PMDSO), tetramethyldisiloxane (TMDSO), and trisiloxanes such as hexamethytrisiloxane, heptamethytrisiloxane. In some embodiments, the silicon-containing precursor may be an alkoxysilane. The alkoxysilane contains a central silicon atom having one or more alkoxy groups bonded thereto and one or more hydrogen atoms bonded thereto. Examples include, but are not limited to, trimethoxysilane (TMOS), dimethoxysilane (DMOS), methoxysilane (MOS), methyldimethoxysilane (MDMOS), diethoxymethylsilane (DEMS), dimethylethoxysilane (DMES), and dimethylmethoxysilane (DMMOS).

[0158] During the deposition process by remote plasma CVD, radicals of hydrogen or other source gases may selectively break Si-H bonds and / or Si-Si bonds, but retain or substantially retain Si-O bonds (if any), Si-N bonds (if any), and Si-C bonds (if any). The broken bonds can serve as sites for crosslinking during or after deposition. Bonding and crosslinking at the reaction sites can together form the main framework or matrix in the resulting spacer layer.

[0159] Radicals of hydrogen or other source gases may be in a low-energy state or ground state in the environment adjacent to the semiconductor substrate. This provides mild reaction conditions when reacting with the silicon-containing precursor. The radical may include a hydrogen radical (i.e., a hydrogen atom radical). In some embodiments, all or substantially all or most of the hydrogen atom radicals may be in the ground state. For example, at least about 90% or 95% of the hydrogen atom radicals adjacent to the semiconductor substrate are in the ground state. In certain embodiments, the source gas is provided in a carrier gas such as helium. As an example, hydrogen gas at a concentration of about 1-10% hydrogen may be provided in a helium carrier.

[0160] Once the radicals of the source gas are generated in the remote plasma source, they can be in an excited energy state. For example, hydrogen in an excited energy state can have an energy of at least 10.2 eV (first excited state). The excited hydrogen atom radicals can non-selectively decompose the silicon-containing precursor. For example, the excited hydrogen atom radicals can easily break Si-H, Si-Si, Si-N, Si-O, and Si-C bonds, thereby changing the composition or physical or electrical properties of the spacer layer. In some embodiments, when the excited hydrogen atom radicals lose their energy or relax, the excited hydrogen atom radicals become low-energy hydrogen atom radicals or ground-state hydrogen atom radicals. The low-energy or ground-state hydrogen atom radicals are capable of selectively breaking Si-H and Si-Si bonds and generally preserving Si-O, Si-N, and Si-C bonds.

[0161] In some embodiments, the silicon-containing precursor can be provided together with a co-reactant. Exemplary co-reactants include carbon dioxide (CO 2 ), carbon monoxide (CO), water (H 2 O), methanol (CH 3 OH), oxygen (O 2 ), ozone (O 3 ), nitrogen (N 2 ), nitrous oxide (N 2 O), ammonia (NH 3 ), diazene (N 2 H 2 ), methane (CH 4 ), ethane (C 2 H 6 ), acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), diborane (B 2 H 6 ) and combinations thereof. The co-reactant can be provided into the processing chamber along the same flow path as the silicon-containing precursor. Alternatively, the co-reactant can be provided along a flow path separate from the silicon-containing precursor. The radicals of the source gas can react with both the silicon-containing precursor and the co-reactant in an environment adjacent to the semiconductor substrate to form a spacer layer.

[0162] In some embodiments of process 500, before depositing the spacer layer, the amorphous silicon initial layer is exposed to a plasma to convert the amorphous silicon initial layer into a doped silicon layer. The doped silicon layer can include silicon carbide, silicon carbonitride, silicon carbonitride, or silicon carbonitride oxide. The plasma can include radicals of one or more of carbon, oxygen, hydrogen, or nitrogen. In some embodiments, the plasma can include radicals of a dopant gas, where the dopant gas includes one or more of the following: nitrogen (N 2 ), ammonia (NH 3)), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ), acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), or nitrogen dioxide (NO 2 ). Free radicals of the dopant gas may include hydrogen radicals (H*), nitrogen radicals (N*), oxygen radicals (O*), carbon radicals (C*), amine radicals (NH*, NH 2 *), or combinations thereof. In some embodiments, the conversion of the initial amorphous silicon layer may occur in the same processing chamber as the deposition of the initial amorphous silicon layer and the deposition of the spacer layer. Thus, the deposition and conversion steps may occur without introducing a vacuum interruption between operations. The plasma used in the conversion may be a remote plasma, where free radicals of the dopant gas are generated in a remote plasma source. The remote plasma is introduced into the processing chamber through a showerhead, where the initial amorphous silicon layer is exposed to the remote plasma to form a doped silicon layer. The composition of the dopant gas, relative flow rate, pressure, conversion time, plasma power, plasma frequency, and other parameters can be controlled to adjust the composition of the doped silicon layer. The doped silicon layer can serve as an initial layer for the subsequent deposition of the spacer layer, which is discussed in the following Figure 6 processes.

[0163] In some embodiments of process 500 where the initial amorphous silicon layer is replaced with an initial amorphous boron layer, the initial amorphous boron layer is exposed to a plasma to convert the initial amorphous boron layer into a doped boron layer before depositing the spacer layer. The doped boron layer may include boron carbide, boron nitride, boron oxide, boron oxynitride, boron carbon oxide, boron carbonitride, or boron carbon oxynitride. The plasma may include free radicals of one or more of carbon, oxygen, hydrogen, or nitrogen. In some embodiments, the plasma may include free radicals of a dopant gas, where the dopant gas includes one or more of the following: nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), or hydrazine (N 2 H 4 ), acetylene (C2 H 2 )), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O) or nitrogen dioxide (NO 2 ). The radicals of the dopant gas may include hydrogen radicals (H*), nitrogen radicals (N*), oxygen radicals (O*), carbon radicals (C*), amine radicals (NH*, NH 2 *), or combinations thereof. In some embodiments, the conversion of the amorphous boron initial layer may occur in the same processing chamber as the deposition of the amorphous boron initial layer and the deposition of the spacer layer. Thus, the deposition and conversion steps may occur without introducing a vacuum interruption between operations. The plasma used in the conversion may be a remote plasma, where the radicals of the dopant gas are generated in a remote plasma source. The remote plasma is introduced into the processing chamber through a showerhead from the remote plasma source, where the amorphous boron initial layer is exposed to the remote plasma to form a doped boron layer. The composition of the dopant gas, relative flow rate, pressure, conversion time, plasma power, plasma frequency, and other parameters can be controlled to adjust the composition of the doped boron layer. The doped boron layer can serve as an initial layer for subsequent deposition of the spacer layer.

[0164] Figure 6 FIG. shows a flow chart of an exemplary method of forming a spacer layer on one or more semiconductor device structures according to some other embodiments. The operations of process 600 may be performed in a different order and / or with different, fewer, or additional operations. One or more operations of process 600 may use Figure 9 or Figure 10 The substrate processing apparatus shown is used to perform. In some embodiments, the operations of process 600 may be implemented at least in part according to software stored in one or more non-transitory computer-readable media.

[0165] In block 610 of process 600, a semiconductor substrate having one or more semiconductor device structures is provided, where each semiconductor device structure includes at least a dielectric overlay above a conductive layer. The semiconductor substrate is provided in a processing chamber. The processing chamber configured to receive the semiconductor substrate is also configured to deposit an initial layer. In some embodiments, the processing chamber for depositing the initial layer is the same as the processing chamber for depositing the spacer layer. Aspects of block 610 of process 600 may be the same as or similar to those of block 510 of process 500. Thus, details regarding the semiconductor substrate, the processing chamber, and the one or more semiconductor device structures in block 610 of process 600 can be found in the description of block 510 of process 500.

[0166] In block 620 of process 600, a silicon-based initial layer is conformally deposited on the dielectric overlay and the conductive layer of the one or more semiconductor device structures. The silicon-based initial layer may be deposited using a two-step process, where an amorphous silicon layer is conformally deposited on the exposed surfaces of the one or more semiconductor device structures, and the amorphous silicon layer is then converted into a doped silicon layer by exposure to a plasma. The doped silicon layer forms the silicon-based initial layer. In some embodiments, the silicon-based initial layer may have a thickness equal to or less than about equal to or less than about or about and about between. The silicon-based initial layer may be a thin or ultra-thin doped silicon layer conformally deposited on at least two different material surfaces and serves as a single material surface on which subsequent layers (e.g., spacer layers) are deposited.

[0167] In some embodiments, the silicon-based initial layer includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. For example, the silicon-based initial layer includes silicon carbide, silicon carbonitride, silicon carbon oxynitride, or silicon carbon oxynitride. These silicon-based initial layers can promote the nucleation of subsequent layers (e.g., spacer layers) and avoid nucleation delay above the conductive layer. In addition, some of these silicon-based initial layers do not adversely affect the electrical properties of the conductive layer.

[0168] The formation of the silicon-based initial layer can be carried out by depositing an amorphous silicon layer and then converting the amorphous silicon layer upon exposure to a plasma stream. Examples of techniques for forming the amorphous silicon layer may include PVD, thermal CVD, LPCVD, PECVD, hot wire CVD, ALD, and PEALD. In some embodiments, the amorphous silicon layer may be formed by thermal CVD via a thermal decomposition process. The thermal decomposition process is initiated by activating a precursor gas species at a high temperature, where the precursor gas species is thermally decomposed into atoms and / or molecules by CVD for deposition.

[0169] In some embodiments, the thickness of the amorphous silicon layer can be controlled according to a predetermined deposition time to achieve a desired thickness. In some embodiments, the deposition time can be between about 5 seconds and about 500 seconds, or between about 10 seconds and about 200 seconds. In some embodiments, the desired thickness of the amorphous silicon layer can be between about and about , between about and about , or between about and about . The deposition time can correspond to the desired thickness of the amorphous silicon layer. The thickness can be controlled so that radicals and / or ions from a subsequent remote plasma treatment can penetrate sufficiently into the amorphous silicon layer.

[0170] For some embodiments, deposition of the amorphous silicon layer can occur by flowing one or more silicon-containing precursors into a processing chamber toward a semiconductor substrate. The silicon-containing precursor is delivered to the substrate surface where it is adsorbed by the semiconductor substrate to form a highly conformal amorphous silicon layer. In some embodiments, forming the amorphous silicon layer by CVD may require controlling the deposition pressure in the range of 0.1 Torr to 30 Torr or 0.5 Torr to about 10 Torr. The substrate temperature during amorphous silicon deposition can be controlled between about 300 °C and about 700 °C, between about 400 °C and about 650 °C, or between about 450 °C and about 600 °C. After deposition, the step coverage of the amorphous silicon layer can be at least about 85%. In some embodiments, the step coverage can be at least about 90%, at least about 95%, or at least about 98%.

[0171] The silicon-containing precursor can have a low adhesion coefficient as described above. In some cases, the adhesion coefficient of the silicon-containing precursor can be about 0.05 or less, such as about 0.001 or less. In some embodiments, the silicon-containing precursor can include at least one or more Si-Si bonds and / or one or more Si-H bonds, where the silicon-containing precursor can be a silane-based precursor as described above. By way of example, the silicon-containing precursor includes silane, disilane, trisilane, or other silane-based precursors.

[0172] The amorphous silicon layer is conformally deposited on the exposed surfaces of the one or more semiconductor device structures, including on the exposed surfaces of conductive layers and dielectric capping layers. This can include the sidewalls of the conductive layers, the sidewalls of the dielectric capping layers, and the top surfaces of the dielectric capping layers. This can also include the sidewalls of the semiconductor layers. The amorphous silicon layer can be deposited on both the horizontal and vertical surfaces of the one or more semiconductor device structures.

[0173] The amorphous silicon layer is exposed to a plasma to convert the amorphous silicon layer into a doped silicon layer. The plasma can include radical species and / or ions generated in a plasma source. In some embodiments, the plasma source can be an in-situ plasma source. In some embodiments, the plasma source can be a remote plasma source, where the remote plasma source is separated from the processing chamber. The remote plasma can be generated in the remote plasma source and introduced into the processing chamber through a showerhead to flow toward the surface of the semiconductor substrate.

[0174] A source gas (e.g., a hydrogen source gas) can be provided to the plasma source. Radicals and / or ions of the source gas can be formed in the plasma generated in the plasma source. In some embodiments, the plasma can include radicals of nitrogen, oxygen, hydrogen, or carbon. One or more of the foregoing radicals can act as dopants to form the doped silicon layer. The source gas can include a gaseous species that includes: a nitrogen-containing reactant that includes nitrogen, ammonia, diazene, or hydrazine; a hydrogen-containing reactant that includes hydrogen or methane; a hydrocarbon that includes acetylene, ethylene, or propylene; an oxygen or oxide reactant that includes oxygen, water, carbon monoxide, carbon dioxide, nitrous oxide, or nitrogen dioxide, or a mixture thereof. The gaseous species can be determined based on one or more doping elements required to form the doped silicon layer. For example, a nitrogen-containing reactant can be delivered to form a silicon nitride layer. In another example, a carbon-containing reactant can be delivered to form a silicon carbide layer. In yet another example, a carbon- and nitrogen-containing reactant can be delivered to the amorphous silicon layer to form a silicon carbonitride layer. In still other examples, an oxygen- and carbon-containing reactant can be delivered to the amorphous silicon layer to form a silicon carbon oxide layer. In some embodiments, the composition of one or more source gases in the plasma (e.g., remote plasma) can be controlled to adjust the composition of the doped silicon layer.

[0175] The pressure in the processing chamber can be adjusted to increase the ionization of one or more gaseous species in the source gas and reduce the residence time of the radicals. Reducing the residence time can reduce the effect of radical recombination. A lower pressure causes the molecules to move faster, which results in increased ionization of the source gas, reduced residence time, and reduced radical recombination. In some embodiments, the pressure can be between about 0.2 Torr and about 10 Torr, or between about 1 Torr and about 3 Torr. However, it should be understood that the pressure in the processing chamber during exposure to the plasma can be greater than 3 Torr or greater than 10 Torr, where other process conditions (e.g., an inert carrier gas) result in sufficient ionization and reduced residence time.

[0176] The amorphous silicon layer can be exposed to the plasma for a predetermined time. In some embodiments, the predetermined time can be between about 2 seconds and about 100 seconds, or between about 5 seconds and about 50 seconds. The determination of the processing time can depend on the thickness of the amorphous silicon layer, where a thicker layer may require a longer exposure time to the plasma.

[0177] In addition to the time and pressure during exposure to plasma for conversion, one or more process conditions can be controlled by adjusting one or more of RF power, source gas flow, source gas composition, and other process conditions that affect plasma characteristics, which can thus result in different bond densities in the amorphous silicon layer before or during conversion.

[0178] The deposition and conversion of the amorphous silicon layer can be achieved using a cycle of deposition and conversion. Alternatively, the deposition and conversion of the amorphous silicon layer can be achieved using alternating cycles of deposition and conversion. The deposition and conversion can be performed in a layer-by-layer manner to allow each plasma conversion cycle to fully convert the deposited amorphous silicon layer such that substantially the entire deposited amorphous silicon layer is doped. In this way, the entire amorphous silicon stack can be uniformly converted into a doped silicon layer and have a more uniform dopant distribution across the thickness of the doped silicon layer. Accordingly, it should be understood that the deposition and conversion cycles for forming the doped silicon layer can be continuously repeated until the desired thickness of the doped silicon layer is reached.

[0179] Similar to conformally depositing the amorphous silicon layer, converting the amorphous silicon layer into a doped silicon layer to form the silicon-based initial layer can result in a highly conformal initial layer on the one or more semiconductor device structures. In some embodiments, the silicon-based initial layer can have a step coverage of at least about 85%, at least about 90%, at least about 95%, or at least about 98% on the one or more semiconductor device structures. In this way, the silicon-based initial layer can be deposited substantially uniformly over the dielectric and conductive layers of the one or more semiconductor device structures.

[0180] During the conversion of the amorphous silicon layer into a doped silicon layer, the temperature in the environment adjacent to the semiconductor substrate can be any suitable temperature that promotes the conversion reaction by doping one or more gaseous species into the amorphous silicon layer, but is sometimes limited by the application of the device containing the doped silicon layer. In some embodiments, the temperature in the environment adjacent to the substrate can be primarily controlled by the temperature of the pedestal on which the substrate is supported during plasma processing / conversion. In some embodiments, the operating temperature can be between about 50 °C and about 650 °C. For example, in many integrated circuit applications, the operating temperature can be between about 250 °C and about 400 °C. In some embodiments, increasing the temperature can result in an increase in the number of bonds between silicon atoms and dopant atoms and a decrease in the number of Si-Si bonds. Increasing the temperature can also result in an increase in the crystallinity of the doped silicon layer.

[0181] In some embodiments, the conversion of the amorphous silicon layer occurs in the same processing chamber as the deposition of the amorphous silicon layer. In this way, the deposition and conversion steps can occur without introducing a vacuum interruption between operations.

[0182] Converting an amorphous silicon layer into a doped silicon layer to form a silicon-based initial layer can have several advantages. The resulting silicon-based initial layer can form a conformal layer required for manufacturing high aspect ratio features in semiconductor devices, where the conformal layer provides uniform deposition even on the surfaces of two or more materials. The processing of amorphous silicon and the deposition of amorphous silicon can occur in the same processing chamber to avoid contamination and increase throughput. Tunability of the composition in the silicon-based initial layer with one or more dopants is also possible. Further, forming the silicon-based initial layer according to some embodiments of the present invention can have a higher throughput than conventional ALD processes.

[0183] In some embodiments, process 900 involves conformally depositing a boron-based initial layer rather than a silicon-based initial layer on the dielectric capping layer and the conductive layer of the one or more semiconductor device structures. An amorphous boron layer is conformally deposited on the exposed surfaces of the one or more semiconductor device structures, and the amorphous boron layer is then converted into a doped boron layer by exposure to a plasma. The doped boron layer forms the boron-based initial layer. In some embodiments, the boron-based initial layer can have a thickness equal to or less than about Equal to or less than about Or about And about Between. The deposition of the amorphous boron layer is carried out using a boron-containing precursor (such as borane (BH 3 ), diborane (B 2 H 6 ), or triborane (B 3 H 7 ). The amorphous boron layer can be exposed to a plasma to convert the amorphous boron layer into a doped boron layer. The doped boron layer can include boron carbide, boron nitride, boron oxide, boron oxynitride, boron carbon oxide, boron carbonitride, or boron carbon oxynitride. The plasma can include radicals of one or more of carbon, oxygen, hydrogen, or nitrogen. In some instances, the plasma is a remote plasma. In some embodiments, the conversion of the amorphous boron layer can occur in the same processing chamber as the deposition of the amorphous boron layer and the deposition of the spacer layer.

[0184] In block 630 of process 600, a spacer layer is deposited on a silicon-based initial layer. It should be understood that in some alternative embodiments of process 300, the spacer layer is deposited on a boron-based initial layer. The spacer layer can be a dielectric material, such as a low-k dielectric material. In some embodiments, the spacer layer includes a silicon-containing layer, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. For example, the spacer layer includes silicon oxycarbide. When the one or more semiconductor device structures include a plurality of semiconductor device structures spaced apart by recessed features, the spacer layer can separate / isolate the semiconductor device structures from each other. In some aspects, the spacer layer can be used to electrically isolate adjacent bit lines in a memory array. In some embodiments, the one or more semiconductor device structures are DRAM bit structures that are part of a DRAM array, where the DRAM bit structure can be a vertically oriented structure having at least one bit line. The DRAM bit structures can be spaced apart by recessed features (such as trenches), where the recessed features can have an aspect ratio of depth to width equal to or greater than about 10:1, equal to or greater than about 20:1, or equal to or greater than about 50:1.

[0185] The spacer layer can be deposited at least over the dielectric capping layer and the conductive layer, where an amorphous silicon initial layer is disposed between the spacer layer and the dielectric capping layer and between the spacer layer and the conductive layer. The spacer layer can be deposited uniformly or at least substantially uniformly over the dielectric capping layer and the conductive layer. In some embodiments, the spacer layer is deposited uniformly or at least substantially uniformly over the dielectric capping layer, the conductive layer, and the semiconductor layer of the one or more semiconductor device structures. In some embodiments, the dielectric capping layer includes silicon nitride, the conductive layer includes tungsten or molybdenum, and the semiconductor layer includes polysilicon. The conductive layer can serve as one or more bit lines in a DRAM array.

[0186] The silicon-based initial layer facilitates the nucleation and growth of the spacer layer at least over the dielectric capping layer and the conductive layer of the one or more semiconductor device structures. Given that the growth of the spacer layer on the conductive layer (e.g., tungsten) may be inhibited or slowed relative to the dielectric capping layer, an amorphous silicon layer (such as silicon carbide, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride) facilitates the consistent growth of the spacer layer on the conductive layer and the dielectric capping layer. Thus, the silicon-based silicon initial layer reduces the nucleation delay in the conductive layer. Additionally, the silicon-based initial layer does not adversely affect the electrical properties of the conductive layer. In some cases, the resistance of the conductive layer is maintained or even improved using the silicon-based initial layer.

[0187] Deposition of the spacer layer and the silicon-based initial layer can occur in the same processing chamber. This avoids unnecessary vacuum interruptions that may expose the semiconductor substrate to harmful materials or particles between substrate transfers. This also reduces processing time, reduces processing steps, lowers costs, and increases yield. The processing chamber can be configured for CVD-based deposition of an amorphous silicon layer, treatment / transformation of the amorphous silicon layer into a silicon-based initial layer by exposure to plasma, and CVD-based deposition of the spacer layer. For example, the amorphous silicon layer can be deposited in the processing chamber by thermal CVD, the amorphous silicon layer can be treated / transformed using remote plasma to form a silicon-based initial layer, and the spacer layer can be deposited in the same processing chamber by remote plasma CVD.

[0188] When depositing the spacer layer (e.g., silicon oxycarbide) by remote plasma CVD, the one or more semiconductor device structures can be exposed to a silicon-containing precursor in the processing chamber. Free radicals of a source gas (e.g., a hydrogen source gas) are generated in a remote plasma source located upstream of the processing chamber, and the free radicals of the source gas are introduced into the processing chamber and directed towards the semiconductor substrate to react with the silicon-containing precursor to form the spacer layer. In some embodiments, the free radicals of the source gas include free radicals of hydrogen. The free radicals of hydrogen can interact with the silicon-containing precursor at a location downstream of the remote plasma source to activate the silicon-containing precursor in the environment adjacent to the semiconductor substrate. The remote plasma source used to generate free radicals for depositing the spacer layer can be the same as the remote plasma source used to generate free radicals for transforming the amorphous silicon layer. Deposition of the amorphous silicon layer, transformation of the amorphous silicon layer, and deposition of the spacer layer can be performed in the same processing chamber having the same remote plasma source located upstream of the processing chamber.

[0189] The silicon-containing precursor can include one or more Si-H bonds and / or one or more Si-Si bonds. In some embodiments, the silicon-containing precursor further includes one or more Si-O bonds, one or more Si-N bonds, and / or one or more Si-C bonds. For depositing silicon oxycarbide, the silicon-containing precursor can include one or both of Si-O and Si-C bonds. In some embodiments, the silicon-containing precursor can be a siloxane. In some embodiments, the silicon-containing precursor can be an alkoxysilane. Aspects of the silicon-containing precursor for depositing the spacer layer are as described above.

[0190] During deposition by remote plasma CVD, free radicals of hydrogen or other source gas can selectively break Si-H bonds and / or Si-Si bonds, but retain Si-O bonds (if any), Si-N bonds (if any), and Si-C bonds (if any). The broken bonds can serve as sites for crosslinking during or after deposition. Bonding and crosslinking at the reaction sites can together form a primary backbone or matrix in the resulting spacer layer.

[0191] Free radicals can be in a low-energy state or a ground state in an environment adjacent to a semiconductor substrate. This provides mild reaction conditions when reacting with silicon-containing precursors. The free radicals can include hydrogen radicals (i.e., hydrogen atom radicals). In some embodiments, all or substantially all or most of the hydrogen atom radicals can be in the ground state. For example, at least about 90% or 95% of the hydrogen atom radicals adjacent to the semiconductor substrate are in the ground state. In certain embodiments, the source gas is provided in a carrier gas (such as helium). As an example, hydrogen gas can be provided in a helium carrier at a concentration of about 1-10% hydrogen.

[0192] Figures 7A - 7C A cross-sectional schematic view of an exemplary semiconductor substrate for spacer formation on a plurality of semiconductor device structures according to some embodiments is shown. Figure 7A A semiconductor substrate 700 having a plurality of semiconductor device structures 710 is shown. In some embodiments, the plurality of semiconductor device structures 710 are memory device structures of a memory array. For example, the memory device structure can include bit structures in a DRAM array, where each bit structure can include a bit line and a capping layer on the bit line. In some instances, the bit line can be coupled to a polysilicon layer of a transistor. The semiconductor substrate 700 can be provided in a processing chamber configured to perform CVD-based operations.

[0193] The plurality of semiconductor device structures 710 can be separated by recessed features 730 (such as trenches). The recessed features 730 can be formed by patterning the semiconductor substrate 700. The recessed features 730 can be high aspect ratio features having an aspect ratio of depth to width equal to or greater than about 10:1, equal to or greater than about 20:1, or equal to or greater than about 50:1.

[0194] Each of the plurality of semiconductor device structures 710 includes a material stack that at least includes a conductive layer 714 and a dielectric capping layer 716 above the conductive layer 714. In some embodiments, each of the plurality of semiconductor device structures 710 further includes a semiconductor layer 712, where the conductive layer 714 is located above the semiconductor layer. In some embodiments, the conductive layer 714 includes tungsten, tantalum, titanium, molybdenum, hafnium, cobalt, chromium, nickel, platinum, ruthenium, copper, aluminum, or an alloy thereof. For example, the conductive layer 714 includes tungsten or molybdenum. The conductive layer 714 can act as a bit line in a DRAM array. In some embodiments, the dielectric capping layer 716 includes an electrically insulating material, such as a nitride or an oxide. For example, the dielectric capping layer 716 includes silicon nitride. The dielectric capping layer 716 can act as a capping layer on the bit lines of a DRAM array. The dielectric capping layer 716 can also act as a hard mask for the bit lines. In some embodiments, the semiconductor layer 712 includes polysilicon or other suitable semiconductor materials.

[0195] Figure 7Bshows the semiconductor substrate 700 after depositing an initial layer 718 on the plurality of semiconductor device structures 710. The initial layer 718 can be a thin or ultra-thin layer of material conformally deposited on each of the plurality of semiconductor device structures 710. In some embodiments, the initial layer 718 can have a thickness equal to or less than about Figure 7A equal to or less than about equal to or less than about or about between about and about

[0196] The initial layer 718 provides a uniform surface over two or more material surfaces (i.e., the dielectric overlay 716, the conductive layer 714, and the semiconductor layer 712) and is made of a common material. This common material surface enables subsequent spacer materials to grow and nucleate on the semiconductor device structures 710 and minimizes nucleation delay. In some embodiments, the initial layer 718 is composed of amorphous silicon. In some other embodiments, the initial layer 718 is composed of a doped silicon layer (such as silicon carbide, silicon carbonitride, or silicon carbonitroxide), where the doped silicon layer is formed by converting / processing amorphous silicon by exposure to a plasma (e.g., a remote plasma). In some embodiments, the initial layer 718 is composed of amorphous boron. In some other embodiments, the initial layer 718 is composed of a doped boron layer (such as boron carbide, boron nitride, boron oxide, boron oxynitride, boron carbonoxide, boron carbonitride, or boron carbonitroxide).

[0197] When the initial layer 718 is composed of amorphous silicon, amorphous silicon can be conformally deposited in a processing chamber by a thermal CVD process. The plurality of semiconductor device structures 710 of the semiconductor substrate 700 can be exposed to a silane-based precursor, where the silane-based precursor adsorbs on the exposed surfaces of the plurality of semiconductor device structures 710. Thermal energy is applied to the semiconductor substrate 700 to thermally decompose the silane-based precursor and deposit amorphous silicon in a highly conformal manner. The thermal decomposition can occur at a temperature between about 400 °C and about 650 °C. Conformal deposition of the initial layer 718 by thermal CVD provides a higher throughput compared to a conventional ALD process. For example, a conventional ALD process may take 3 to 6 minutes to deposit silicon oxide or silicon nitride to reduce nucleation delay, while a thermal CVD process may take 10 to 20 seconds to conformally deposit amorphous silicon to reduce nucleation delay.

[0198] When the initial layer 718 is composed of amorphous boron, the amorphous boron can be conformally deposited in the processing chamber by a thermal CVD process. The plurality of semiconductor device structures 710 of the semiconductor substrate 700 can be exposed to a boron-based precursor (e.g., borane), where the boron-based precursor adsorbs on the exposed surfaces of the plurality of semiconductor device structures 710. Thermal energy is applied to the semiconductor substrate 400 to thermally decompose the boron-based precursor and deposit amorphous boron in a highly conformal manner. The thermal decomposition can occur at a temperature between about 400 °C and about 650 °C.

[0199] When the initial layer 718 is composed of doped silicon, the doped silicon can be formed by the conversion / processing of the above amorphous silicon. After conformally depositing amorphous silicon by thermal CVD, the amorphous silicon can be exposed to a plasma containing radicals of a nitrogen-containing reactant, an oxygen-containing reactant, a hydrogen-containing reactant, and / or a carbon-containing reactant. The gas plasma stream can include hydrogen radicals (H*), nitrogen radicals (N*), oxygen radicals (O*), carbon radicals (C*), amine radicals (NH*, NH 2 *), or a combination thereof. In some embodiments, the plasma can be a remote plasma generated in a remote plasma source located upstream of the processing chamber. The processing chamber for the conversion / processing of amorphous silicon can be the same as the processing chamber for amorphous silicon deposition. The radicals of the plasma can act as dopants to convert amorphous silicon into doped silicon, where the doped silicon serves as the initial layer 718. After converting / processing the amorphous silicon into doped silicon, the doped silicon can maintain high conformality along the plurality of semiconductor device structures 710.

[0200] When the initial layer 718 is composed of doped boron, the doped boron can be formed by the conversion / processing of the above amorphous boron. After conformally depositing amorphous boron by thermal CVD, the amorphous boron can be exposed to a plasma containing radicals of a nitrogen-containing reactant, an oxygen-containing reactant, a hydrogen-containing reactant, and / or a carbon-containing reactant. The gas plasma stream can include hydrogen radicals (H*), nitrogen radicals (N*), oxygen radicals (O*), carbon radicals (C*), amine radicals (NH*, NH 2 *), or a combination thereof. In some embodiments, the plasma can be a remote plasma generated in a remote plasma source located upstream of the processing chamber. The processing chamber for the conversion / processing of amorphous boron can be the same as the processing chamber for amorphous boron deposition. The radicals of the plasma can act as dopants to convert amorphous boron into doped boron, where the doped boron serves as the initial layer 718. After converting / processing the amorphous boron into doped boron, the doped boron can maintain high conformality along the plurality of semiconductor device structures 710.

[0201] Figure 7C Shown is after depositing the spacer layer 720 on the initial layer 718 of the plurality of semiconductor device structures 710 Figure 7BA semiconductor substrate 700. The spacer layer 720 can provide electrical isolation between adjacent semiconductor device structures 710. In some embodiments, the spacer layer 720 can be a gap filler or at least a partial gap filler in the recessed feature 730. The spacer layer 720 can be deposited uniformly or substantially uniformly over the plurality of semiconductor device structures 710. In other words, the average thickness of the spacer layer 720 above the conductive layer 714 is the same as or substantially the same as the average thickness of the spacers above the dielectric capping layer 716 and / or above the semiconductor layer 712. In some embodiments, the average thickness of the spacer layer 720 is equal to or greater than about 1 nm, equal to or greater than about 3 nm, equal to or greater than about 10 nm, or equal to or greater than about 50 nm.

[0202] The spacer layer 720 is composed of an electrically insulating material. In some embodiments, the spacer layer 720 is composed of a low-k dielectric material. In some examples, the spacer layer 720 includes a silicon-containing layer, such as silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. In some other examples, the spacer layer 720 includes a boron-containing layer, such as boron carbide, boron nitride, boron oxide, boron oxynitride, boron carbon oxide, boron carbonitride, or boron carbon oxynitride. In some embodiments, the spacer layer 720 includes silicon carbon oxide.

[0203] The spacer layer 720 can be deposited in a processing chamber using a CVD-based process. In some embodiments, the processing chamber used to deposit the spacer layer 720 can be the same as the processing chamber used to deposit the initial layer 718. In some embodiments, the spacer layer 720 can be deposited by remote plasma CVD. For example, when the spacer layer 720 is composed of silicon oxycarbide, the plurality of semiconductor device structures 710 can be exposed to a silicon-containing precursor (e.g., siloxane), where the silicon-containing precursor adsorbs onto the initial layer 718. The plurality of semiconductor device structures 710 can be exposed to a remote plasma, where the remote plasma is generated in a plasma source located upstream of the processing chamber. When generating the remote plasma, radicals of a source gas (e.g., a hydrogen source gas) are generated in the remote plasma source. The radicals of the source gas are introduced into the processing chamber through a showerhead and flow towards the semiconductor substrate 700, where the radicals react with the adsorbed silicon-containing precursor to form the spacer layer 720. In some embodiments, the radicals are hydrogen radicals in a low-energy state (e.g., the ground state) in an environment adjacent to the semiconductor substrate 700. The hydrogen radicals can be in an energy state sufficient to selectively break the Si-H and Si-Si bonds in the silicon-containing precursor but retain the Si-O and Si-C bonds in the silicon-containing precursor. In some embodiments, the hydrogen radicals can be transported with an inert gas (e.g., argon, helium, neon, krypton, or xenon). In some embodiments, one or more co-reactants can flow into the processing chamber to react with the silicon-containing precursor, thereby increasing or decreasing the carbon, oxygen, or nitrogen content of the spacer layer 720. Details regarding remote plasma CVD processes for depositing silicon-containing films can be found in U.S. Patent No. 10,325,773, titled "CONFORMAL DEPOSITION OF SILICON CARBIDE FILMS," filed by Varadarajan et al. on February 6, 2015, U.S. Patent Application No. 16 / 044,357, titled "CONFORMAL DEPOSITION OF SILICON CARBIDE FILMS USING HETEROGENEOUS PRECURSOR INTERACTION," filed by Weimer et al. on July 24, 2018, and U.S. Patent Application No. 17 / 286,407, titled "DOPED OR UNDOPED SILICON CARBIDE DEPOSITION AND REMOTE HYDROGEN PLASMA EXPOSURE FOR GAPFILL," filed by Yuan et al. on April 16, 2021, each of which is incorporated by reference in its entirety for all purposes.

[0204] One aspect of the present invention is an apparatus configured to implement the methods described herein. Suitable apparatuses include hardware for performing process operations and a system controller having instructions for controlling the process operations in accordance with the present invention. In some embodiments, the apparatus for performing the foregoing process operations may include a remote plasma source. In some embodiments, the apparatus for performing the foregoing process operations may include a susceptor for heating a substrate to a high temperature.

[0205] Figure 8 A semiconductor processing apparatus for performing deposition is schematically shown in accordance with some embodiments. The semiconductor processing apparatus 800 may be used to deposit thin films using ALD or PEALD, but it may be suitable for performing other film deposition operations including CVD or PECVD. For simplicity, the semiconductor processing apparatus 800 is depicted as a stand-alone processing station having a reaction chamber 802 for maintaining a low-pressure environment. However, it will be understood that multiple semiconductor processing apparatuses 800 may be included in a common processing tool environment. Further, it should be understood that in some embodiments, one or more hardware parameters of the semiconductor processing apparatus 800 (including those discussed in detail below) may be programmatically adjusted by one or more computer controllers.

[0206] The semiconductor processing apparatus 800 is in fluid communication with a reactant delivery system 804 for delivering process gases to a distribution showerhead 806. The reactant delivery system 804 may include a mixing vessel 808 for mixing and / or conditioning the process gases for delivery to the showerhead 806. One or more mixing vessel inlet valves 810 and 810A may control the introduction of process gases into the mixing vessel 808. Similarly, a showerhead inlet valve 812 may control the introduction of process gases into the showerhead 806.

[0207] Some reactants may be stored in liquid form before being vaporized and subsequently delivered to the reaction chamber 802. For example, Figure 8 embodiments include a vaporization point 814 for vaporizing liquid reactants to be supplied to the mixing vessel 808. In some embodiments, the vaporization point 814 may be a heated vaporizer. Reactant vapors generated by these vaporizers may condense in downstream delivery pipes. Exposure of incompatible gases to the condensed reactants may generate small particles. These small particles may clog pipes, impede valve operation, contaminate substrates, etc. Some ways to address these issues include purging and / or evacuating the delivery pipes to remove residual reactants. However, purging the delivery pipes may increase the cycle time of the processing station and reduce the throughput of the processing station. Accordingly, in some embodiments, the delivery pipes downstream of the vaporization point 814 may be heat traced. In some examples, the mixing vessel 808 may also be heat traced.

[0208] In some embodiments, a liquid flow controller may be provided upstream of the vaporization point 814 for controlling the mass flow rate of the liquid to be vaporized and delivered to the semiconductor processing apparatus 800. For example, the liquid flow controller (LFC) may include a thermal mass flow meter (MFM) located downstream of the LFC.

[0209] The showerhead 806 distributes process gases and / or reactants (e.g., film precursors) to the substrate 816. In Figure 8 the illustrated embodiment, the substrate 816 is located below the showerhead 806 and is shown resting on the pedestal 818. It should be understood that the showerhead 806 may have any suitable shape and may have any appropriate number and arrangement of ports for distributing the process gases to the substrate 816.

[0210] The chamber space 820 is located below the showerhead 806. In some embodiments, the pedestal 818 may be raised or lowered to expose the substrate 816 to the chamber space 820 and / or to change the volume of the chamber space 820. Optionally, the pedestal 818 may be lowered and / or raised during portions of the deposition process to adjust the process pressure, reactant concentration, etc. within the chamber space 820.

[0211] Adjusting the height of the pedestal 818 may allow the plasma density to change during the plasma activation and / or treatment cycles incorporated in the deposition process. At the end of the deposition process stage, the pedestal 818 may be lowered during another substrate transfer stage to allow the substrate 816 to be removed from the pedestal 818.

[0212] While the exemplary microvolume changes described herein relate to a height-adjustable pedestal, it should be understood that in some embodiments, the position of the showerhead 806 may be adjusted relative to the pedestal 818 to change the volume of the chamber space 820. Further, it should be understood that the vertical positions of the pedestal 818 and / or the showerhead 806 may be changed by any suitable mechanism within the scope of the present invention. In some embodiments, the pedestal 818 may include a rotating shaft for rotating the orientation of the substrate 816. It should be understood that in some embodiments, one or more of these exemplary adjustments may be performed programmatically by one or more suitable computer controllers.

[0213] Return Figure 8In the illustrated embodiment, the showerhead 806 and the pedestal 818 are in electrical communication with a radio frequency (RF) power source 822 and a matching network 824 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 822 and the matching network 824 can operate at any suitable power to form a plasma having a desired radical species composition. For example, the RF power for an inductively coupled plasma for a 300 mm wafer can be between about 300 watts and about 10 kilowatts, or between about 1 kilowatt and about 6 kilowatts. Similarly, the RF power source 822 can provide RF power at any appropriate frequency. In some embodiments, the RF power source 822 can be configured to control the high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 50 kHz and 600 kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It should be understood that any suitable parameter can be adjusted discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power can be pulsed intermittently to reduce ion bombardment of the substrate surface relative to a continuously powered plasma.

[0214] In some embodiments, the semiconductor processing apparatus 800 is controlled using appropriate hardware and / or appropriate machine-readable instructions in a system controller, and the system controller can provide control instructions via a series of input / output control (IOC) sequencing instructions. In one example, the instructions for setting the plasma conditions for a plasma process stage can be included in the corresponding plasma activation recipe stage of a deposition process recipe. In some cases, the process recipe stages can be sequenced such that all instructions for a process stage are executed simultaneously with that process stage. In some embodiments, the instructions for setting one or more plasma parameters can be included in a recipe stage prior to the plasma process stage. For example, a first recipe stage can include instructions for setting the flow rates of inert and / or reactant gases, instructions for setting the plasma generator to a power set point, and a time delay instruction for the first recipe stage. A second subsequent recipe stage can include instructions for starting the plasma generator and a time delay instruction for the second recipe stage. A third recipe stage can include instructions for stopping the plasma generator and a time delay instruction for the third recipe stage. It should be understood that these recipe stages can be further subdivided and / or repeated in any suitable manner within the scope of the present invention.

[0215] In some embodiments, the pedestal 818 can be temperature-controlled by a temperature control element 826. Further, in some embodiments, the pressure control of the semiconductor processing apparatus 800 can be provided by a butterfly valve 828. As Figure 8 shown in the embodiments of, the butterfly valve 828 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the semiconductor processing apparatus 800 can also be adjusted by changing the flow rate of one or more gases introduced into the semiconductor processing apparatus 800.

[0216] Figure 9 FIG. shows a schematic diagram of an exemplary plasma processing apparatus with a remote plasma source according to some embodiments. It should be understood that, according to some embodiments, Figure 9 the plasma processing apparatus in can be used to deposit amorphous silicon / boron layers and spacer layers, and optionally process the amorphous silicon / boron layers to form silicon-based or boron-based layers according to some embodiments. In some embodiments, the initial layer (e.g., amorphous silicon, silicon-based layer, amorphous boron, or boron-based layer) and the spacer layer can be deposited without exposure to ambient atmosphere.

[0217] The plasma processing apparatus 900 includes a reaction chamber 910 having a showerhead 920. Inside the reaction chamber 910, a substrate 930 is placed on a platform or pedestal 935. In some embodiments, the pedestal 935 can be equipped with a heating / cooling element. A controller 940 can be connected to the components of the plasma processing apparatus 900 to control the operation of the plasma processing apparatus 900. For example, the controller 940 can include instructions for controlling process conditions (e.g., temperature process conditions and / or pressure process conditions) for the operation of the plasma processing apparatus 900. In some embodiments, the controller 940 can include instructions for controlling the flow rates of precursor gases, reactant gases, source gases, and / or carrier gases. The controller 940 can include instructions for changing the flow rates of reactant gases, source gases, and / or carrier gases over time. The controller 940 can include instructions for controlling the chamber pressure, substrate temperature, RF power, exposure time, gas composition, and relative concentrations of gas compositions. A more detailed description of the controller 940 is provided below.

[0218] During operation, a gas or gas mixture is introduced into reaction chamber 910 via one or more gas inlets coupled to reaction chamber 910. In some embodiments, two or more gas inlets are coupled to reaction chamber 910. A first gas inlet 955 may be coupled to reaction chamber 910 and connected to container 950, while a second gas inlet 965 may be coupled to reaction chamber 910 and connected to remote plasma source 960. In some embodiments, second gas inlet 965 may provide a carrier gas to reaction chamber 910. In embodiments that include a remote plasma source, the delivery lines for the precursor and the radical species generated in the remote plasma source are separate. Thus, the precursor and the radical species do not substantially interact before reaching substrate 930. It should be understood that in some embodiments, the gas lines may be reversed such that container 950 may provide a precursor gas stream through second gas inlet 965, while remote plasma source 960 may provide ions and radicals through first gas inlet 955.

[0219] One or more radical species may be generated in remote plasma source 960 and configured to enter reaction chamber 910 via second gas inlet 965. Any type of plasma source may be used for remote plasma source 960 to generate radical species. This includes but is not limited to inductively coupled plasma (ICP) sources, capacitively coupled plasma (CCP) sources, microwave plasma sources, DC plasma sources, and laser-generated plasma sources. An example of a capacitively coupled plasma may be a radio frequency (RF) plasma. The high-frequency plasma may be configured to operate at 13.56 MHz or higher frequencies. An example of such a remote plasma source 960 may be manufactured by Lam Research Corporation of Fremont, California Another example of such a remote plasma source 960 may be manufactured by MKS Instruments, Inc. of Wilmington, Massachusetts which may be operated at 440 kHz and may be provided as a sub-unit that bolts onto a larger device for parallel processing of one or more substrates. In some embodiments, a microwave plasma may be used as remote plasma source 960, such as also manufactured by MKS Instruments, Inc. The microwave plasma may be configured to operate at a frequency of 2.45 GHz. The gas species provided to remote plasma source 960 may include hydrogen, nitrogen, oxygen, carbon, or other gases as mentioned elsewhere herein. In certain embodiments, hydrogen is provided in a carrier gas (e.g., helium). As an example, hydrogen may be provided to the helium carrier gas at a concentration of about 1 - 50% volume hydrogen.

[0220] The precursor can be provided in a container 950 and supplied to the showerhead 920 via a first gas inlet 955. The showerhead 920 distributes the precursor into the reaction chamber 910 and towards the substrate 930. The substrate 930 can be located below the showerhead 920. It should be understood that the showerhead 920 can have any suitable shape and can have any number and arrangement of ports for distributing the gas to the substrate 930. The precursor can be supplied to the showerhead 920 at a controlled flow rate and ultimately reach the substrate 930.

[0221] The one or more radical species formed in the remote plasma source 960 can be transported in the gas phase to the substrate 930. The one or more radical species can flow through a second gas inlet 965 and into the reaction chamber 910. It should be understood that the second gas inlet 965 need not be Figure 9 transverse to the surface of the substrate 930 as shown. In some embodiments, the second gas inlet 965 can be located directly above the substrate 930 or at other locations. The distance between the remote plasma source 960 and the reaction chamber 910 can be configured to provide mild reaction conditions such that the ionized species generated in the remote plasma source 960 are substantially neutralized, but at least some radical species in the low energy state or ground state remain in the environment adjacent to the substrate 930. Such low energy radical species do not recombine to form stable compounds. The distance between the remote plasma source 960 and the reaction chamber 910 can depend on the aggressiveness of the plasma (e.g., determined in part by the source RF power level), the gas density in the plasma (e.g., if there is a high concentration of hydrogen atoms, a large portion of which may recombine to form H 2 ) and other factors. In some embodiments, the distance between the remote plasma source 960 and the reaction chamber 910 can be between about 1 cm and 30 cm, such as about 5 cm or about 15 cm.

[0222] In some embodiments, a co-reactant or reactant that is not primarily a silicon-containing precursor or a hydrogen radical is introduced during the deposition reaction and / or remote plasma etching. In some embodiments, the plasma processing apparatus 900 is configured to introduce the co-reactant or reactant through the second gas inlet 965, in which case the co-reactant is at least partially converted into a plasma. In some embodiments, the plasma processing apparatus 900 is configured to introduce the co-reactant through the showerhead 920 via the first gas inlet 955. Examples of co-reactants include oxygen, nitrogen, ammonia, carbon dioxide, carbon monoxide, and the like. The flow rate of the co-reactant can vary over time to create a composition gradient in the graded film.

[0223] In some embodiments, a gas plasma stream can be generated from a remote plasma source 960. The gas plasma stream from the remote plasma source 960 can include ions, radicals, charged neutrals, and other reactive species of the reactant gas. For example, the reactive species can include radical species of hydrogen, nitrogen, oxygen, carbon, or amines, which can be supplied to the surface of the substrate 930 for remote plasma deposition and / or conversion.

[0224] Figure 10 A schematic diagram of an exemplary plasma processing apparatus with a remote plasma source is shown in accordance with some implementations. It should be understood that Figure 10 the reaction chamber in can be used for depositing a silicon-containing layer and / or processing a silicon-containing layer formed in the reaction chamber according to some embodiments. It should be understood that Figure 10 the reaction chamber in can be used for depositing a boron-containing layer and / or processing a boron-containing layer formed in the reaction chamber according to some embodiments. In some embodiments, a silicon-containing layer or a boron-containing layer can be formed in the reaction chamber, and then processed in the same reaction chamber using a remote plasma source without exposing the silicon-containing layer or the boron-containing layer to the ambient atmosphere.

[0225] The plasma processing apparatus 1000 includes a remote plasma source 1002 separated from the reaction chamber 1004. The remote plasma source 1002 is fluidly connected to the reaction chamber 1004 through a gas distributor or showerhead 1006. In some embodiments, the showerhead 1006 includes an ion filter for filtering ions to limit ion bombardment damage to the substrate 1012. Radical species and / or ions are generated in the remote plasma source 1002, and the radical species can be supplied to the reaction chamber 1004. Precursors (such as silicon-containing precursors or boron-containing precursors) are supplied to the reaction chamber 1004 through a gas supply line or gas outlet 1008 disposed downstream of the remote plasma source 1002 and the showerhead 1006.

[0226] The substrate 1012 is supported on a substrate support structure or wafer pedestal 1014. The wafer pedestal 1014 can be configured with lift pins or other movable support members to position the substrate 1012 within the deposition / processing zone 1010. The substrate 1012 can be moved to a position closer to or farther from the showerhead 1006. The wafer pedestal 1014 is shown in Figure 10 as having lifted the substrate 1012 into the deposition / processing zone 1010.

[0227] In some embodiments, the wafer pedestal 1014 includes an electrostatic chuck 1016. The electrostatic chuck 1016 includes one or more electrostatic clamping electrodes 1018 embedded within the body of the electrostatic chuck 1016. In some embodiments, the one or more electrostatic clamping electrodes 1018 may be coplanar or substantially coplanar. The electrostatic clamping electrodes 1018 may be powered by a direct current (DC) power source or a DC clamping voltage (e.g., between about 200V and about 2000V) such that the substrate 1012 can be held on the electrostatic chuck 1016 by electrostatic attraction. Power may be supplied to the electrostatic clamping electrodes 1018 through a first wire 1020. The electrostatic chuck 1016 may further include one or more heating elements 1022 embedded within the body of the electrostatic chuck 1016. The one or more heating elements 1022 may include resistive heaters. In some embodiments, the one or more heating elements 1022 are disposed below the one or more electrostatic clamping electrodes 1018. The one or more heating elements 1022 may be configured to heat the substrate 1012 to a temperature greater than about 450°C, greater than about 500°C, greater than about 550°C, greater than about 600°C, or greater than about 650°C. The one or more heating elements 1022 provide selective temperature control of the substrate 1012. Power may be supplied to the one or more heating elements 1022 through a second wire 1024.

[0228] A coil 1028 is disposed around the remote plasma source 1002, where the remote plasma source 1002 includes an outer wall (e.g., a quartz dome). The coil 1028 is electrically coupled to a plasma generator controller 1032, which may be used to form and sustain a plasma within the plasma region 1034 through inductively coupled plasma generation. In some embodiments, the plasma generator controller 1032 may include a power supply source for supplying power to the coil 1028, where the power may be in the range of about 300W to about 15kW per station, or in the range of about 1kW to about 10kW per station during plasma generation. In some embodiments, an electrode or antenna for parallel plate or capacitively coupled plasma generation may be used to produce a continuous supply of radicals through plasma excitation rather than inductively coupled plasma generation. Regardless of the mechanism used to ignite and sustain the plasma in the plasma region 1034, radical species may be continuously generated through plasma excitation during layer formation (e.g., film deposition) and / or remote plasma processing.

[0229] In some embodiments, hydrogen radicals (H*), nitrogen radicals (N*), oxygen radicals (O*), carbon radicals (C*), amine radicals (NH*, NH 2*) or a combination thereof is generated in the plasma region 1034 under approximately steady-state conditions during steady-state film deposition or remote plasma processing controlled by the plasma generator controller 1032, but transients may occur at the start and end of film deposition and / or remote plasma processing (e.g., remote plasma etching). For example, hydrogen radicals can be generated in the plasma region 1034. In another example, two or more different types of radicals can be generated in the plasma region 1034, such as nitrogen-containing radicals and hydrogen radicals, nitrogen-containing radicals and carbon-containing radicals, or nitrogen-containing radicals, carbon-containing radicals, and oxygen-containing radicals. Although Figure 10 shows nitrogen (N*), amine radicals (NH*, NH 2 *), and hydrogen radicals (H*), it should be understood that the foregoing radicals are illustrative only, and other radicals may be present additionally or alternatively to the Figure 10 depicted radicals.

[0230] When the source gas is being supplied to the remote plasma source 1002, a continuous supply of ions and radicals can be generated within the plasma region 1034. The ions generated in the plasma region 1034 can be filtered out by the ion filter of the showerhead 1006. In this way, the radical supply generated in the plasma region 1034 can be supplied to the substrate 1012 in the reaction chamber 1004, and ion bombardment can be restricted. The conditions in the remote plasma source 1002 can be controlled, including the composition of the source gas supplied to the remote plasma source 1002 and the RF power supplied to the coil 1028, to optimize the generation of the desired radical species in the plasma region 1034. In some embodiments, the source gas can include oxygen-containing reactants (e.g., oxygen, water, ozone, carbon monoxide, carbon dioxide, nitrogen dioxide, nitrous oxide), carbon-containing reactants (e.g., acetylene, ethylene, or propylene), hydrogen-containing reactants (e.g., hydrogen or methane), or nitrogen-containing reactants (e.g., nitrogen, ammonia, diazene, or hydrazine) or mixtures thereof. In some embodiments, the source gas can include hydrogen gas. For example, hydrogen radicals can be generated in the plasma region 1034, where the source gas of hydrogen gas can be supplied to the remote plasma source 1002 to provide a gas plasma stream including hydrogen radicals to the substrate 1012 in the reaction chamber 1004. In one example, in the case where the source gas mixture includes one or both of ammonia and hydrogen gas and nitrogen gas, nitrogen radicals can be generated together with one or both of amine and hydrogen radicals. The concentration of amine radicals or nitrogen radicals can be greater than or significantly greater than the concentration of hydrogen radicals to convert the amorphous Si layer into a doped silicon film, such as a silicon nitride film. The concentration of nitrogen radicals can be greater than or significantly greater than the concentration of hydrogen radicals to deposit a silicon nitride film.

[0231] In some embodiments, the source gas may be mixed with one or more additional gases. The one or more additional gases may be supplied to a remote plasma source 1002. In some embodiments, the source gas is mixed with one or more additional gases to form a gas mixture, wherein the one or more additional gases may include a carrier gas. Non-limiting examples of the additional gases may include helium, neon, argon, krypton, and xenon. Other examples of the additional gases may include hydrogen and ammonia. The one or more additional gases may support or stabilize steady-state plasma conditions within the remote plasma source 1002 or assist in the transient plasma ignition or extinction process. In Figure 10 FIG. 1, a source gas supply source 1036 is fluidly connected to the remote plasma source 1002 to supply the source gas. Additionally, an additional gas supply source 338 is fluidly coupled to the remote plasma source 302 to supply the one or more additional gases. For some embodiments, from about 5 sccm to about 10,000 sccm, or from about 10 sccm to about 200 sccm of the source gas may be supplied from the source gas supply source 1036. Additionally, an additional gas supply source 1038 is fluidly connected to the remote plasma source 1002 to supply the one or more additional gases. While Figure 10 the embodiments in FIG. 2 depict the gas mixture of the source gas and the one or more additional gases being introduced through separate gas outlets, it should be understood that the gas mixture may be introduced directly into the remote plasma source 1002. That is, the pre-mixed dilution gas mixture may be supplied to the remote plasma source 1002 through a single gas outlet. When one or more source gases are supplied to the remote plasma source 1002, power is provided to the remote plasma source 1002, which may dissociate the one or more source gases and generate ions and / or radicals in an excited energy state.

[0232] Depending on the source gas provided to remote plasma source 1002, when the plasma source is ignited, one or more gaseous species may be at least partially converted into ions and / or radicals of the one or more gaseous species in remote plasma source 1002. For example, plasma-activated gas 1042 (e.g., ions and / or radicals of nitrogen, hydrogen, carbon, oxygen, amine, or combinations thereof) exits remote plasma source 1002 and enters reaction chamber 1004 through showerhead 1006. The plasma-activated gas 1042 within showerhead 1006 and within reaction chamber 1004 generally does not undergo continuous plasma excitation therein. Showerhead 1006 may have a plurality of gas ports to diffuse the gas flow of plasma-activated gas 1042 into reaction chamber 1004. In some embodiments, the plurality of gas ports may be spaced apart from each other. In some embodiments, the plurality of gas ports may be arranged in a regularly spaced array of channels or through-holes that extend through a plate separating remote plasma source 1002 from reaction chamber 1004. The plurality of gas ports may smoothly disperse and diffuse the radicals (including plasma-activated gas 1042) exiting remote plasma source 1002 into deposition zone 1010 of reaction chamber 1004 while filtering out ions.

[0233] Plasma-activated species 1042 (e.g., excited nitrogen, hydrogen, carbon, oxygen, and / or amine radicals) exits remote plasma source 1002 and enters reaction chamber 1004 through showerhead 1006. The plasma-activated species 1042 within showerhead 1006 and within reaction chamber 1004 generally does not undergo continuous plasma excitation therein. Showerhead 1006 may have a plurality of gas ports to diffuse the gas flow of plasma-activated gas 1042 into reaction chamber 1004. In some embodiments, the plurality of gas ports may be spaced apart from each other. In some embodiments, the plurality of gas ports may be arranged in a regularly spaced array of channels or through-holes that extend through a plate separating remote plasma source 1002 from reaction chamber 1004. The plurality of gas ports may smoothly disperse and diffuse the radicals (including plasma-activated species 1042) exiting remote plasma source 1002 into deposition / processing zone 1010 of reaction chamber 1004 while filtering out ions.

[0234] When the plasma-activated material 1042 is delivered from the showerhead 1006 to the reaction chamber 1004, a precursor gas 1044 (or other process gas) can be introduced into the reaction chamber 1004. The precursor gas 1044 can include a silicon-containing precursor such as silane. Alternatively, the precursor gas 1044 can include a boron-containing precursor such as borane. The precursor gas 1044 can be introduced through a gas supply line or gas outlet 1008, where the gas outlet 1008 can be fluidly coupled to a precursor supply source 1040. The gas supply line 1008 can include openings spaced apart from each other such that the gas flow of the precursor gas 1044 can be introduced in a direction parallel to the direction in which the plasma-activated material 1042 exits the showerhead 1006. In some embodiments, the gas supply line 1008 can be located downstream of the showerhead 1006. In some embodiments, the gas supply line 1008 is part of the showerhead 1006, such as in a dual-chamber showerhead. The dual-chamber showerhead can provide separate outlets / channels for the plasma-activated material 1042 and the precursor gas 1044 to avoid mixing in the showerhead 1006. Thus, the precursor gas 1044 can flow into the reaction chamber 1004 through the showerhead 1006 without being exposed to the plasma in the remote plasma source 1002. The gas supply line 1008 can be located upstream of the deposition / processing zone 1010 and the substrate 1012. The deposition / processing zone 1010 is inside the reaction chamber 1004 between the gas supply line 1008 and the substrate 1012.

[0235] In a film deposition process, most of the precursor gas 1044 can be prevented from mixing with the plasma-activated material 1042 in or near the showerhead 1006. In some embodiments, the precursor gas 1044 can be delivered to the substrate 1012 during the recipe stage of an ALD cycle, which is separate from the plasma-activated material 1042 delivered to the substrate 1012 during the plasma exposure stage of the ALD cycle. The adsorbed precursor gas 1044 can react with the radicals of the plasma-activated material 1042 during the plasma exposure stage of the ALD cycle to deposit a film. In some embodiments, the precursor gas 1044 can be delivered to the substrate 1012 in a continuous manner to interact with the plasma-activated material 1042 in the deposition / processing zone 1010 to deposit a film by CVD. In some embodiments, the plasma-activated material 1042 can be delivered to the substrate 1012 without delivering the precursor gas 1044 to process the film.

[0236] Gas can be removed from the reaction chamber 1004 through an outlet 1048 fluidly coupled to a pump (not shown). Thus, radical species or sweep gas can be removed from the reaction chamber 1004.

[0237] In some embodiments, a thermal shield (not shown) may be disposed beneath the wafer pedestal 1014. The thermal shield acts as a thermal insulator beneath the wafer pedestal 1014 to slow down heat loss through thermal radiation, thereby reducing the amount of power required to maintain the wafer pedestal 1014 at a specific high temperature and also preventing other components within the reaction chamber 1004 from overheating due to excessive heat radiation from the wafer pedestal 1014. For example, the thermal shield may be radially offset from the stem 1026 and may have a thin annular body with a high view factor relative to the lower side of the electrostatic chuck 1016. Thus, the annular thermal shield can reduce the radiative heat loss from the wafer pedestal 1014.

[0238] The electrostatic chuck 1016 of the wafer pedestal 1014 can adsorb / desorb the substrate 1012 in a plasma processing apparatus 1000 configured to operate at high temperatures. Such high temperatures can be greater than about 350 °C, greater than about 400 °C, greater than about 450 °C, greater than about 500 °C, or greater than about 550 °C.

[0239] In some embodiments, the controller 1050 (e.g., a system controller) is operably communicable with the plasma processing apparatus 1000. In some embodiments, the controller 1050 includes a processor system 1052 (e.g., a microprocessor) configured to execute instructions stored in a data system 1054 (e.g., a memory). In some embodiments, the controller 1050 may communicate with the plasma generator controller 1032 to control plasma parameters and / or conditions in the remote plasma source 1002. In some embodiments, the controller 1050 may communicate with the wafer pedestal 1014 to control pedestal elevation, electrostatic adsorption and desorption, and temperature. In some embodiments, the controller 1050 may control other processing conditions, such as RF power setting, frequency setting, duty cycle, pulse time, pressure within the reaction chamber 1004, pressure within the remote plasma source 1002, gas flow rate from the source gas supply source 1036, gas flow rates from additional gas supply sources 1038 and other sources, the temperature of the wafer pedestal 1014, and the temperature of the reaction chamber 1004, as well as other processing conditions.

[0240] The controller 1050 may contain instructions for controlling the process conditions for operating the plasma processing apparatus 1000. The controller 1050 will generally include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or a computer, analog and / or digital input / output connections, a stepper motor controller board, etc. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with the controller 1050 or they may be provided via a network.

[0241] In some embodiments, the controller 1050 controls all or most of the activities of the plasma processing apparatus 1000 described herein. For example, the controller 1050 may control all or most of the activities of the plasma processing apparatus 1000 associated with film deposition and / or remote plasma processing. The controller 1050 may execute system control software including an instruction set for controlling timing, gas composition, gas flow rate, chamber pressure, chamber temperature, RF power level, substrate position, substrate temperature, and / or other parameters. In some embodiments, other computer programs, scripts, or routines stored on a memory device associated with the controller 1050 may be employed. In a multi-station reactor, the controller 1050 may include different or identical instructions for different apparatus stations, thus allowing the apparatus stations to operate independently or synchronously.

[0242] In some embodiments, the controller 1050 may include instructions configured to perform operations such as conformally depositing an amorphous silicon layer on a substrate in the reaction chamber 1004 and exposing the amorphous silicon layer to plasma-activated species 1042 generated in the remote plasma source 1002 to convert the amorphous silicon layer into a doped silicon layer. In some embodiments, the plasma-activated species 1042 includes radicals of nitrogen, oxygen, hydrogen, or carbon.

[0243] In some embodiments, the controller 1050 may be configured with instructions to perform operations such as conformally depositing a silicon-based initial layer on one or more semiconductor device structures of a substrate 1012 in the reaction chamber 1004, where the one or more semiconductor device structures include at least one dielectric overlay above a conductive layer; and depositing a spacer layer on the silicon-based initial layer. Specifically, the controller 1050 configured with instructions for depositing the silicon-based initial layer may be configured with instructions to flow a silane-based precursor to adsorb on the one or more semiconductor device structures of the substrate and thermally decompose the silane-based precursor to form an amorphous silicon layer. The amorphous silicon layer may serve as the silicon-based initial layer. Alternatively, the controller 1050 may be further configured with instructions to expose the substrate 1012 to plasma-activated species 1042 generated from the remote plasma source 1002 to dope the amorphous silicon layer and form a doped silicon layer, where the doped silicon layer serves as the silicon-based initial layer. In some embodiments, the controller 1050 configured with instructions for depositing the spacer layer is configured with instructions to flow a silicon-containing precursor to adsorb on the silicon-based initial layer, generate a plasma-activated species 1042 including radicals of a source gas in the remote plasma source 1002, and expose the substrate 1012 to the plasma-activated species 1042 to interact the radicals with the adsorbed silicon-containing precursor to deposit the spacer layer.

[0244] In some embodiments, the controller 1050 may be configured with instructions to perform operations such as conformally depositing a boron-based initial layer on one or more semiconductor device structures of the substrate 1012 in the reaction chamber 1004, where the one or more semiconductor device structures include at least one dielectric overlay on top of a conductive layer, and depositing a spacer layer on the boron-based initial layer. Specifically, the controller 1050 configured with instructions for depositing the boron-based initial layer may be configured with instructions to flow a borane-based precursor to adsorb on the one or more semiconductor device structures of the substrate and thermally decompose the borane-based precursor to form an amorphous boron layer. The amorphous boron layer may serve as the boron-based initial layer. Alternatively, the controller 1050 may be further configured with instructions to expose the substrate 1012 to a plasma-activated species 1042 generated from a remote plasma source 1002 to dope the amorphous boron layer and form a doped boron layer, where the doped boron layer serves as the boron-based initial layer. In some embodiments, the controller 1050 configured with instructions for depositing the spacer layer is configured with instructions to flow a boron-containing precursor to adsorb on the boron-based initial layer, generate a plasma-activated species 1042 including radicals of a source gas in the remote plasma source 1002, and expose the substrate 1012 to the plasma-activated species 1042 to interact the radicals with the adsorbed boron-containing precursor to deposit the spacer layer.

[0245] In some embodiments, the plasma processing apparatus 1000 may include a user interface associated with the controller 1050. The user interface may include a display screen, a graphical software display of the plasma processing apparatus 1000 and / or process conditions, and user input devices (such as pointing devices, keyboards, touchscreens, microphones, etc.).

[0246] The computer program code for controlling the above operations may be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, etc. The compiled object code or script is executed by a processor to perform the tasks certified in the program.

[0247] Signals for monitoring the process may be provided through the analog and / or digital input connectors of the controller 1050. Signals for controlling the process are output on the analog and digital output connectors of the system.

[0248] Broadly speaking, the controller 1050 can be defined as an electronic device that has various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller 1050 in the form of various individual settings (or program files), and the individual settings (or program files) define the operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials (such as amorphous silicon), surfaces, circuits, and / or die of a wafer.

[0249] In some embodiments, the controller 1050 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, the controller 1050 can be in the "cloud" or be all or part of a fab host system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change the parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (such as a server) can provide a process recipe to the system via a network (which can include a local network or the Internet). The remote computer can include a user interface that enables the input or programming of parameters and / or settings, and then sends the parameters and / or settings from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool, and the controller is configured to interface with or control the tool. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are networked together and work towards a common purpose (such as the processes and controls described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely (such as at the platform level or as part of a remote computer), which are combined to control the process on the chamber.

[0250] In the foregoing description, numerous specific details have been set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that these specific embodiments are not intended to limit the disclosed embodiments.

[0251] While the foregoing embodiments have been described with some details for purposes of clear understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the presented embodiments. Accordingly, the presented embodiments are regarded as illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A method of forming a doped silicon layer, which comprises: forming an amorphous silicon layer on a semiconductor substrate in a reaction chamber; and exposing the amorphous silicon layer to a gas plasma stream to convert the amorphous silicon layer into the doped silicon layer.

2. The method according to claim 1, wherein the gas plasma stream comprises radicals of nitrogen, oxygen, hydrogen or carbon.

3. The method according to claim 1, wherein the gas plasma stream comprises a remote plasma stream.

4. The method according to claim 3, which further comprises: generating a remote plasma of a source gas in a remote plasma source; and introducing the remote plasma as the remote plasma stream into the reaction chamber through a showerhead.

5. The method according to claim 4, wherein the source gas comprises a nitrogen-containing reactant, a hydrogen-containing reactant, a hydrocarbon, an oxygen or oxide reactant, or a combination thereof.

6. The method according to claim 4, wherein the source gas comprises nitrogen (N 2 ), ammonia (NH 3 ), diazene (N 2 H 2 ), hydrazine (N 2 H 4 ), acetylene (C 2 H 2 ), ethylene (C 2 H 4 ), propylene (C 3 H 6 ), hydrogen (H 2 ), methane (CH 4 ), oxygen (O 2 ), water (H 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), or a combination thereof.

7. The method according to claim 4, wherein the composition of the source gas in the remote plasma source is controlled to adjust the composition of the doped silicon layer.

8. The method according to claim 1, wherein the doped silicon layer comprises silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, silicon carbonitride or silicon carbon oxynitride.

9. A method of depositing a spacer layer on one or more semiconductor device structures, the method comprises: providing a semiconductor substrate having one or more semiconductor device structures in a processing chamber, wherein each of the one or more semiconductor device structures comprises a conductive layer and a dielectric capping layer over the conductive layer; conformally depositing an amorphous silicon initial layer on the dielectric capping layer and the conductive layer of the one or more semiconductor device structures; and depositing the spacer layer on the amorphous silicon initial layer.

10. The method according to claim 9, wherein conformally depositing the amorphous silicon initial layer comprises: depositing the amorphous silicon initial layer by thermal chemical vapor deposition (CVD).

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