Control circuit based on deformable mirror device driver

Abstract

The invention provides a control circuit based on a deformable mirror device driver. The control circuit comprises a multi-stage power supply framework, a driving channel module, a monitoring module and an FPGA (Field Programmable Gate Array) control module, the multi-stage power supply framework comprises an external main power supply, an FPGA power supply module and a driving channel power supply module, and the external main power supply is 12V power supply output and is used for providing power supply input for the FPGA power supply module and the driving channel power supply module; the number of the driving channel power supply modules is N, the driving channel power supply modules are marked as the first driving channel power supply module to the Nth driving channel power supply module, and each driving channel power supply module comprises a voltage reference source, a voltage reduction voltage stabilizer, a voltage boosting voltage stabilizer and a D / A voltage reference source. According to the invention, the cooperative feedback of the multi-path monitoring module is utilized, the circuit operation quality is ensured, the FPGA algorithm is fused for dynamic compensation, the crosstalk between driving voltage channels is reduced, the synchronism and consistency of a large-scale array are ensured, and the accumulative error of an optical image is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of adaptive optics and precision drive control, and particularly relates to a control circuit based on a driver of a deformable mirror device. Background Art

[0002] As an active optical device capable of adjusting the deformation of the mirror surface in real time, the deformable mirror has the advantages of fast response speed, high deformation accuracy, multi-channel collaborative control, etc., and is widely used in wavefront correction of astronomical telescopes, beam shaping of laser communication, and aberration compensation of biomedical imaging and other fields. However, the existing drive circuits of deformable mirrors still have the disadvantages of slow dynamic response, insufficient multi-channel consistency and noise suppression ability. Its control accuracy and system stability also cannot meet the requirements of specific scenarios. Therefore, how to further improve the comprehensive performance of the deformable mirror driver remains the research focus in this field. Among them, the data output by the FPGA can dynamically adjust the voltage amplitude of the drive channel, significantly improving the response speed and control accuracy of the deformable mirror. The multi-module drive channels work in parallel collaboratively to ensure the synchronization of the large-scale drive array of the deformable mirror. The power supply of a single module ensures that the voltage amplifier provides precise and stable power for each unit. Moreover, traditional analog circuits are vulnerable to factors such as temperature and electromagnetic fields, and a large number of devices are required to achieve some simple data integration and algorithm processing. By using an FPGA control module to digitalize the control loop, the data extracted from the drive channel through the monitoring module can be transmitted to the FPGA for processing, and filtering or control algorithms can be added in appropriate modules using its parallel computing ability to achieve multi-channel real-time closed-loop control, and external interference can be suppressed through digital isolation and synchronous sampling techniques. Therefore, this control circuit based on the driver of the deformable mirror device has significant technical potential in improving the performance of the deformable mirror and expanding its application scenarios. Summary of the Invention

[0003] Object of the Invention: The technical problem to be solved by the present invention is to provide a control circuit based on a driver of a deformable mirror device aiming at the deficiencies of the prior art, including a multi-stage power supply architecture, a drive channel module, a monitoring module, and an FPGA control module; The multi-stage power supply architecture includes an external main power supply, an FPGA power supply module, and a drive channel power supply module. The external main power supply outputs 12V power supply, which is used to provide power input for the FPGA power supply module and the drive channel power supply module; There are N drive channel power supply modules, which are respectively denoted as the first drive channel power supply module to the Nth drive channel power supply module. Each drive channel power supply module includes a voltage reference source, a buck voltage regulator, a boost voltage regulator, and a D / A voltage reference source; There are N step-down voltage regulators, denoted as the first step-down voltage regulator to the Nth step-down voltage regulator; each step-down voltage regulator has the same structure; the first step-down voltage regulator is composed of a first BUCK converter, a second BUCK converter, a third BUCK converter, a fourth BUCK converter, a first LDO voltage regulator, and a second LDO voltage regulator; There are N voltage reference sources, denoted as the first voltage reference source to the Nth voltage reference source; each voltage reference source has the same structure; The first voltage reference source is composed of a first reference voltage, a second reference voltage, and a fifth BUCK converter; There are N D / A voltage reference sources, denoted as the first D / A voltage reference source to the Nth D / A voltage reference source; each D / A voltage reference source has the same structure.

[0004] The first step-down voltage regulator and the first voltage reference source form an FPGA power supply module. The external total power supply voltage is stepped down by the first step-down voltage regulator. The first voltage reference source provides a reference voltage for the first step-down voltage regulator and supplies power to the FPGA control module; There are N drive channel modules, denoted as the first drive channel module to the Nth drive channel module respectively. Each drive channel module includes a decoder, a digital-to-analog converter, an analog switch matrix, a voltage follower, and a multi-channel voltage amplifier. The decoder and the digital-to-analog converter receive the FPGA digital signal, use the decoder to turn on the analog switch, and transmit the analog signal of the digital-to-analog converter through the analog switch to the voltage follower for signal buffering. The voltage follower inputs the buffered analog signal into the corresponding channel of the multi-channel voltage amplifier; The digital-to-analog converter group includes N digital-to-analog converters, denoted as the first digital-to-analog converter to the Nth digital-to-analog converter respectively; The analog switch matrix includes Z analog switches, denoted as the first analog switch to the Zth analog switch respectively; There are Z voltage followers, denoted as the first voltage follower to the Zth voltage follower respectively; There are N decoders, denoted as the first decoder to the Nth decoder respectively. The decoder converts the digital signal output by the FPGA control module into an enable signal for driving the analog switch to open; The digital-to-analog converter has A analog signal output channels, converts the digital signal output by the FPGA control module into an initial analog signal for driving the deformable mirror device, and the analog signal is transmitted to the voltage follower through the analog switch; The structure and function of each analog switch are the same. The analog switch receives the enable signal output by the decoder, bidirectionally opens the corresponding channel of the analog switch, enables the analog signal of the digital-to-analog converter to be input into the analog switch of the corresponding channel, and the analog switch then outputs the analog signal to the bound voltage follower; There are A voltage followers, each with the same structure and function, which are used to buffer and electrically isolate the analog signals output by the analog switch, ensure the stability of the signals, and output the buffered analog signals to the multi-channel voltage amplifier; The multi-channel voltage amplifier amplifies the analog voltage signals output by the voltage followers and outputs high-voltage signals to drive the corresponding units of the deformable mirror; The number of each module can be flexibly changed according to the number of ceramic units for driving the deformable mirror. For example, if the number of ceramic units for driving the deformable mirror is 64, 8-channel drive channel modules can be used. Each drive channel module uses a 3-8 decoder to turn on the 8-channel analog switch. The analog signals of the 8-channel digital-to-analog converter are transmitted to the 8-channel voltage followers through the turned-on analog switch for signal buffering. Then, the signals of the voltage followers are input into the 8-channel voltage amplifiers for voltage amplification. Finally, 8 drive channel modules generate 64 voltage amplification signals to drive the 64-ceramic unit deformable mirror.

[0005] The drive channel power supply module steps down the external main power supply through a buck regulator to convert it into a stable power supply for monitoring the operation of the module and the drive channel module; the external main power supply voltage is stepped up through a boost regulator to convert it into a stable power supply for the operation of the multi-channel voltage amplifying electrical appliances of the drive channel module; the voltage reference source provides a reference voltage for the buck regulator, and the D / A voltage reference source provides a reference voltage for the digital-to-analog converter of the drive channel module; The FPGA control module includes a clock synchronization module, a digital-analog mixed signal processing module, a bus data interface, a data control module, and a monitoring control module; The clock synchronization module is used to reduce the frequency of the 50MHZ clock input by the FPGA control module and output the SPI_CLK clock for use by each module of the FPGA control module; the input SYS_RST signal of the clock synchronization module is a global reset signal, and the SYS_RST signal will be passed into each module of the FPGA control module; The digital-analog mixed signal processing module includes an SPI protocol 1 module, an SPI protocol data control module, and a read-write FIFO module; the SPI protocol 1 module is used to transmit data through the SPI protocol, the SPI protocol data control module is used to integrate the data transmitted by the SPI protocol 1 module; the read-write FIFO module is used to process the data to be written into the digital-to-analog converter by the buffer data control module and the channel feedback data of the digital-to-analog converter transmitted from the SPI protocol data control module; The digital-analog hybrid signal processing module buffers, integrates, and processes the digital signals and enable signals output by the data control module, and then outputs the processed data to the digital-to-analog converter; when inputting, it sends the digital signal for reading the specified channel to the digital-to-analog converter, reads the digital signal of the specified channel output by the digital-to-analog converter, and then performs processing, integration, and buffering operations to read out the output data to the data control module; The data control module includes a channel data distribution module and an enable module; the channel data distribution module sends an enable signal to the enable module, and the enable module receives the enable signals of the total data interface and the digital-analog hybrid signal processing module, integrates them, and issues an enable signal for driving the decoder of the channel module; When inputting, the data control module passes the channel data and enable signal output by the bus data interface, and at the same time passes the digital signal and enable signal processed by the digital-analog hybrid signal processing module. When outputting, it reads out the closed-loop signal processed to the bus data interface, and outputs the digital signal and enable signal for driving the operation of the analog switch matrix to the decoder; The bus data interface includes a total data module, SPI protocol 2, and an EEPROM storage module; When inputting, the bus data interface uses SPI protocol 2 to pass the data of the monitoring control module and the data of the data control module into the total data module for processing. When outputting, it outputs the channel data and enable signal to the data control module; the EEPROM storage module is used to store the channel feedback data of the digital-to-analog converter passed in from the data control module, and can also store the data to be written to the digital-to-analog converter in the past and present; There are N groups of the monitoring modules, denoted as the first monitoring module to the Nth monitoring module, and each monitoring module includes a distributed digital temperature sensor and a current monitor; The monitoring control module is used to integrate and pass the digital signals read by the distributed digital temperature sensor and the current monitor into the bus data interface for processing; The monitoring control module includes a temperature processing module, a current processing module, and a detection data fusion module; the temperature processing module processes the sensor temperature data and then passes it into the detection data fusion module, and the current processing module processes the sensor current data and then passes it into the detection data fusion module; the monitoring control module performs data fusion processing with the FPGA control module to achieve the distribution and closed-loop feedback control of multi-channel data; The distributed digital temperature sensor is powered by a first step-down voltage regulator, detects the temperature coefficient of the multi-channel voltage amplifier, and passes the digital signal into the FPGA control module through a register; The current monitor is powered by the buck regulator of the drive channel power supply module, monitors the current of the high-voltage line output by the boost regulator of the drive channel power supply module, and transmits the digital signal generated by the current monitor to the FPGA control module through the SPI protocol; the deformable mirror device is a planar array system composed of piezoelectric ceramic units, and the deformable mirror device controls the deformation amount of the piezoelectric ceramic by dynamically adjusting the voltage applied to each ceramic unit, so as to achieve high-precision correction of the light beam wavefront; the voltage control signals output by the multi-channel voltage amplifiers of the drive channels are distributed to each ceramic unit in a vector form.

[0006] The first buck regulator is powered by the total power supply of 12V, and the 12V power supply is stepped down to 7V output through the first BUCK converter of the first buck regulator; the second BUCK converter is stepped down to 5V output; the 12V output power supply is stepped down to 1.2V output through the fourth BUCK converter; the 5V output power supply is stepped down to 3.3V output through the third BUCK converter, and the 3.3V output power supply is stepped down to 1.5V output through the first LDO regulator; the 3.3V output power supply is stepped down to 2.5V output through the second LDO regulator; After the first buck regulator steps down the voltage, the second BUCK converter among them steps down to supply the power supply voltage input of the FPGA control module; The third BUCK converter and the first LDO regulator are used in combination to become the voltage input of the I / O port of the FPGA control module; The second LDO regulator is the PLL analog voltage input of the FPGA control module; The fourth BUCK converter is the core voltage input of the FPGA control module; After the first buck regulator steps down the voltage, the output voltage of the first BUCK converter among them is the power supply input of the first multi-channel voltage amplifier of the first drive channel; The second BUCK converter is the input of the power supply of the first digital-to-analog converter of the first drive channel; The second BUCK converter supplies power to the decoder, analog switch and voltage follower of the first drive channel module; The 5V power supply output by the second BUCK converter is converted to -5V through the first flyback converter, which is the -5V power supply input of the first multi-channel voltage amplifier of the first drive channel module; The second BUCK converter of the first buck regulator also provides 5V power supply for the first digital temperature sensor and the first current monitor of the first monitoring module.

[0007] The first voltage reference source is powered by the total power supply of 12V. The 12V power supply is converted to 3.3V output through the fifth BUCK converter. The 3.3V power supply is converted to 1.2V output and 2.5V output through the first reference voltage and the second reference voltage. The 1.2V output is used as the voltage reference source of the fourth BUCK converter, and the 2.5V output is used as the voltage reference source of the second LDO voltage regulator. The first D / A voltage reference source is powered by the total power supply of 12V. The 12V power supply is converted to 5V output through the second BUCK converter. The 5V power supply is converted to 2.5V output through the third reference voltage. The 2.5V output is used as the reference voltage of the first digital-to-analog conversion chip in the first drive channel to provide a reference voltage for the analog output signal.

[0008] The structures and functions of the N groups of boost voltage regulators are the same. The first boost voltage regulator is powered by the total power supply of 12V. The 12V power supply is boosted to 250V output through the first BOOST conversion circuit to provide 250V power input for the first multi-channel voltage amplifier. The current on the output voltage side of the first boost voltage regulator is detected by the first current monitor of the first monitoring module.

[0009] The digital-analog hybrid signal processing module of the FPGA control module buffers the digital signal and the enable signal output by the data control module into the write FIFO (abbreviation for First Input First Output, first-in-first-out queue), and then transfers the buffered data in the FIFO to the SPI protocol data control module for integration. Finally, the control data is written into the first digital-to-analog converter in the first drive channel through the SPI protocol 1 module. The digital-analog hybrid signal processing module processes the digital signal read by the first digital-to-analog converter from the channel through the SPI protocol and transfers it to the SPI protocol 1. After the digital signal is transferred to the SPI protocol data control module for data integration, it is then transferred to the read FIFO for buffering and finally sent to the data control module.

[0010] The data control module transfers the digital signal and the enable signal processed by the bus data interface to the data distribution module and the enable module for distribution, transfers the distributed channel data and the enable signal to the write FIFO, and transfers the signal to the decoder. The data control module transfers the data and the enable output from the read FIFO to the data distribution module and the enable module for processing, and then reads the processed data and the enable signal to the bus data interface.

[0011] The bus data interface transfers the signal output from the monitoring control module and the data and the enable signal output from the data control module to the total data module for sorting, and outputs the data and the enable signal to the data control module for processing. The total data module can hold the input and output data. The EEPROM storage module is used as the storage end to divide the input and output data into two storage areas. The data to be saved is transmitted to the storage end through the SPI protocol 2, and then looped back to the total data module for signal closed-loop processing.

[0012] The monitoring and control module transmits the data read by the first digital temperature sensor through the register to the temperature processing module for processing; The monitoring and control module reads the data of the first current monitor through the SPI protocol and transmits it to the current processing module for processing; The information processed by the temperature processing module and the current processing module is respectively sent to the detection data fusion module for data processing and integration, and finally the data is output to the bus data interface.

[0013] The detection data fusion module of the monitoring and control module includes: a temperature signal, a filter, and a temperature PI for temperature control, and a current signal, a filter, and a current PI for current control; The data of the temperature PI and the current PI are put into the output conditioning of the detection data module for signal processing, and then the processed signal is sent to the bus data interface.

[0014] The detection data fusion module adopts discretization to implement the incremental PI control algorithm, including: calculating the deviation between the input signal and the reference signal to generate the current error signal e(n): , where is the reference input at the nth moment, is the actual output of the system at the nth moment; The error signal e(n) is processed in parallel through two channels: one channel in the two channels is multiplied by the integral coefficient KI to generate an integral adjustment amount; the other channel is stored in the register as the historical error input e(n - 1) for the proportional term operation in the next control cycle; the proportional term is obtained by multiplying the proportional coefficient KP by the historical error e(n - 1) in the register; then the integral term and the proportional term are vectorially synthesized to obtain the incremental adjustment amount ΔU(n) of the current control cycle: , where is the proportional coefficient, is the integral coefficient; The incremental adjustment amount is algebraically superimposed with the control amount U(n - 1) at the previous moment to obtain the output control amount: , where is the control amount output at the current moment; Update error register: , Store the current error in the register for use in the next cycle; the symbol indicates that the value is assigned to . This algorithm eliminates the integral accumulation effect of the traditional positional algorithm through a recursive iteration mechanism, significantly improving the dynamic response characteristics and steady-state robustness of the system while ensuring control accuracy.

[0015] Advantages: (1) The present invention uses the collaborative design of multi-module distributed independent power supplies and high-precision voltage reference sources to provide isolated stable voltages and low-noise requirements for each operating module; (2) The present invention can be flexibly expanded through N driving channels, and the collaborative parallel operation of multiple modules and driving channels can adapt to deformable mirror arrays of different scales; (3) The present invention uses the collaborative feedback of multiple monitoring modules to ensure the quality of circuit operation, and then integrates the FPGA algorithm for dynamic compensation to reduce the crosstalk between driving voltage channels, ensure the synchronization and consistency of large-scale arrays, and reduce the cumulative error of optical images; (4) The driving channels of the present invention use high-precision digital-to-analog converters, combined with analog switches and decoders, increasing the flexible selection of the driving circuit. The multi-channel voltage amplifier combined with a boost voltage regulator and a voltage follower makes the control of the deformable mirror more precise, significantly improving the correction resolution of the optical system; (5) The present invention uses FPGA digital closed-loop control to achieve multi-channel parallel control, and combines communication protocols to improve the response speed and control accuracy of the system. It meets the wavefront correction requirements such as astronomical observation or laser communication. Brief Description of the Drawings

[0016] Figure 1 is a schematic diagram of the overall structure of the present invention.

[0017] Figure 2 is a schematic diagram of the structure of the FPGA power supply module.

[0018] Figure 3 is a schematic diagram of the structure of the first driving channel power supply module.

[0019] Figure 4 is a schematic diagram of the structure of the first monitoring module.

[0020] Figure 5 is a schematic diagram of the FPGA control module.

[0021] Figure 6 is a schematic diagram of the detection data fusion module.

[0022] Figure 7 Schematic side view of the deformable mirror. Specific implementation mode

[0023] The present invention will be further specifically described below in conjunction with the accompanying drawings and specific implementation modes, and the above and / or other advantages of the present invention will become clearer.

[0024] As Figure 1 shown, an embodiment of the present invention provides a control circuit based on a deformable mirror device driver, including: a multi-stage power supply architecture, a drive channel array, a monitoring unit, and an FPGA control core. The multi-stage power supply architecture consists of an external total power input terminal (12V), an FPGA dedicated low-voltage power supply circuit, and N groups of drive channel high-voltage power supply circuits; the drive channel array includes a cascaded decoder, a digital-to-analog converter group, an analog switch matrix, a voltage follower group, and a multi-channel high-voltage amplifier; the monitoring unit is composed of N groups of distributed digital temperature sensors and a current monitoring device; the FPGA control core integrates a clock synchronization module, a digital-analog mixed signal processor, a bus data interface, and a closed-loop monitoring controller to realize the distribution of multi-channel data and closed-loop feedback control.

[0025] In the power supply module of this example, the external power input of 12V is transmitted to the FPGA power supply module and N groups of drive channel power supply modules. The first buck regulator in the FPGA power supply module converts the 12V voltage into 4-way voltage sources suitable for supplying the FPGA chip based on the reference voltage provided by the first voltage reference source. The buck regulators of the N groups of drive channel power supply modules convert the 12V voltage into voltage sources suitable for supplying the chips of each module of the drive channel based on the reference voltage provided by the voltage reference source. The boost regulator provides a 250V power supply for the multi-channel voltage amplifiers specified by the drive channels. The D / A voltage reference source provides an external reference voltage source for the high-precision requirements of the analog-to-digital converter.

[0026] The FPGA control module reads the data of the temperature of the amplifier monitored by the digital temperature sensor in the monitoring module and the high-voltage line current output by the boost regulator monitored by the current detector, processes the data through the internal module, and inputs the decoder drive data and the digital signal of the analog-to-digital converter into the two chips. After receiving the information, the decoder outputs an enable signal to turn on the specified analog switch. Subsequently, in one clock cycle, the analog-to-digital converter transmits the analog signal in and out through the analog switch. The voltage follower buffers and electrically isolates the analog signal output by the analog switch and then outputs it to the multi-channel voltage amplifier. The multi-channel voltage amplifier amplifies the weak analog signal by a specified multiple according to its own gain requirement to obtain a voltage sufficient to drive the unit array of the deformable mirror, causing it to deform and achieving the purpose of optical wavefront correction.

[0027] The FPGA control module can send read instructions, and the instruction data is transmitted into the digital-to-analog converter. The digital-to-analog converter can output the data of the specified channel required to be read in the instruction to the FPGA control module. The FPGA control module performs feedback processing based on the monitoring module and the read channel voltage data. Then, reasonable channel data is output to the digital-to-analog converter to form a closed-loop control. The read channel voltage feedback signal and the monitoring module sensor feedback signal can be input to drive the digital signal and stored in the memory of the EEPROM storage module. Then, it loops back to the internal module for signal processing.

[0028] Figure 2 It is a schematic diagram of the structure of the FPGA power supply module. The power supply system takes the 12V input as the core and generates different voltage rails through multi-stage voltage conversion to provide precise power supply for the devices in the FPGA control module. The system uses the first buck regulator and the second BUCK converter to convert the 12V power input into 7V and 5V powers. Among them, the 5V output is the power supply voltage for the FPGA, and 7V is the power supply for the multi-channel voltage amplifier. The third BUCK converter and the first LDO regulator can generate the power supply for the 3.3V and 1.5V I / O ports output to the FPGA, enabling the FPGA to flexibly configure the circuit. The second LDO regulator can generate the power supply for the 2.5V PLL analog voltage output to the FPGA, and the 1.2V core voltage power supply generated by the fourth BUCK converter. Its first voltage reference source can use the fifth BUCK converter to generate 3.3V power from the external 12V power supply to supply power to the reference voltage chip. The 1.2V and 2.5V voltages generated by the first reference voltage and the second reference voltage provide the reference reference voltage for the important analog voltage and core voltage conversion chips of the FPGA. Through the power supply sequence control chip or circuit design, the power-on sequence of the power supply is 1. core voltage, 2. analog voltage, 3. I / O port, 4. power supply voltage. And the power-on sequence of the power supply meets the timing requirements during power-on, so as to avoid the latch-up effect and ensure the stable IO state and the reliable startup and long-term stable operation of the FPGA.

[0029] Figure 3 It is a schematic diagram of the structure of the first drive channel power supply module. The power supply system takes the 12V input as the core and generates different voltage rails through multi-stage voltage conversion to provide precise power supply for the devices in the drive channel module. The principles of the buck regulator and the voltage reference source are as Figure 2The above will not be introduced in more detail. The 7V power supply and 5V power supply output by the first BUCK converter generate a -5V power supply through the first flyback converter, and -5V powers the first voltage amplifier. Further, the 5V power supply also powers the first analog-to-digital converter, decoder, analog switch, voltage follower of the drive channel, and the first monitoring module outside. Among them, the first D / A voltage reference source generates a 5V power supply through the second BUCK converter, and then uses a reference chip with a third reference voltage to reduce it to a 2.5V reference voltage, providing an external reference voltage for the mode converter. The first boost regulator uses the first BOOST conversion circuit to boost the input 12V power supply to 250V power supply, providing a drive voltage for the first multi-channel voltage amplifier. The current of its 250V voltage line is also monitored by the first current monitor of the first monitoring module. The first drive channel power supply module is the same as the drive channel power supply modules of other channels.

[0030] Figure 4 It is a schematic diagram of the structure of the first monitoring module. The total power supply of 12V powers the first drive channel power supply module. The first drive channel power supply module powers the first digital temperature sensor and the first current monitor of the first monitoring module through the BUCK circuit. The first digital temperature sensor monitors the temperature coefficient of the first multi-channel voltage amplifier. The FPGA control module reads the temperature value through register configuration. The first current monitor monitors the current of the 250V line. The FPGA control module reads the current value through the SPI protocol. The device temperature is monitored by the first temperature sensor to prevent overheating damage. A temperature compensation algorithm is integrated in the FPGA control module to adjust the drive voltage or signal gain according to the temperature data, improving the system stability. The first current monitor real-time detects the output current of the first multi-channel voltage amplifier to prevent device damage caused by overcurrent. The output power of the power supply module is adjusted according to the current data to reduce the system power consumption and improve the energy efficiency. Their data provides key feedback for the FPGA control module, supporting dynamic adjustment, fault protection, and energy efficiency optimization, and is an indispensable core component in the deformable mirror drive system. The first monitoring module is the same as the monitoring modules of other channels.

[0031] Figure 5Schematic diagram of the FPGA control module; the clock synchronization module converts the system clock input SYS_CLK_50HZ into the global clock SPI_CLK suitable for the operation of other modules. Its SYS_RST is the global reset of the system and is associated with the push-button switch. In the FPGA control module, the temperature processing module in the monitoring and control module reads the sensor register data, processes it, and then passes it to the detection data fusion module for integration. The current processing module in the monitoring and control module uses the SPI protocol to read the first current monitor data, processes it, and then passes it to the detection data fusion module for integration. The detection data fusion module outputs the integrated data to the bus data interface. After processing the temperature and current data through an algorithm, it is used as the output reference for driving the closed-loop output data of the channel voltage. The bus data interface outputs the drive channel data of the deformable mirror array to the data control module and the EEPROM storage module supported by the SPI protocol respectively. The data control module uses the common cooperation of the data distribution module and the EN module to integrate the data output from the bus data interface and the enable signal into two paths. One path is the data signal of 3 bits and the enable signal of the drive encoder. The other path is the data signal of 24 bits and the enable signal passed to the digital-analog hybrid signal processing module. The digital-analog hybrid signal processing module buffers the two input signals into the read FIFO, and the buffered data of the read FIFO is output to the SPI protocol data control for processing into serial data suitable for SPI operation. Further, the SPI protocol data control passes the data to the SPI protocol 1 module, and the SPI protocol 1 outputs the data to the first digital-to-analog converter using the SPI protocol.

[0032] When the FPGA wants to read the data of a certain channel, it sends a read message to the first digital-to-analog converter. The first digital-to-analog converter outputs the data to the SPI protocol 1 module through the SPI protocol, and the SPI protocol data control processes the data of the SPI protocol 1 module and buffers it into the read FIFO. The read FIFO sends the read data and the enable signal to the data distribution module and the enable module of the data control module. The data distribution module and the enable module process the data and output the channel data and the enable signal to the total data module of the total data for splitting and reading. The read channel data can be stored in the EEPROM storage module using the SPI protocol.

[0033] In the total data module of the bus data interface, data can be interacted with the data stored in the EEPROM storage module. The data written to and read from the channels in the past and currently can be read and stored, and then put into the total data module to jointly perform algorithm processing with the sensor coefficients read by the monitoring module, providing more accurate numerical and temperature operations for the unit drive of the deformable mirror array. The storage of the EEPROM storage module can be divided into two areas, half for reading data and half for writing data. The stored data in the EEPROM storage module can also be interacted with an external host computer for convenient host computer control. It transmits 24-bit data, including default register bits, read / write enable bits, channel selection read / write bits, register type configuration bits, and channel data read / write bits, and can cooperate with check codes or check bits to ensure data integrity.

[0034] Figure 6 It is a schematic diagram of the detection data fusion module; the temperature data and current data generated by the temperature sensor and current monitor of the monitoring module are input into the temperature signal and current signal of the detection data fusion module. After the temperature signal is filtered by the filter, the data is input into the temperature PI for regulation. After the current signal is filtered by the filter, the data is input into the current PI for regulation. The values of the temperature PI and the current PI are input into the output conditioning module for signal fusion. The processed signal is then input into the total data module of the bus data interface.

[0035] Figure 7 It is a side schematic diagram of the deformable mirror; on the left is the drive array of the deformable mirror, and on the right is the mirror surface. These units are used to adjust the shape of the mirror surface. The deformable mirror compensates for wavefront aberration by changing the shape of the mirror surface to improve the imaging quality.

[0036] The present invention provides a control circuit based on a deformable mirror device driver. There are many methods and ways to specifically implement this technical solution. The above description is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented using existing technologies.

Claims

1. A control circuit for a deformable mirror device driver, characterized in that, It includes a multi-level power supply architecture, a drive channel module, a monitoring module, and an FPGA control module; The multi-level power supply architecture includes an external main power supply, an FPGA power supply module, and a drive channel power supply module. The external main power supply outputs 12V power supply, which is used to provide power input for the FPGA power supply module and the drive channel power supply module; There are N drive channel power supply modules, which are respectively denoted as the first drive channel power supply module to the Nth drive channel power supply module. Each drive channel power supply module includes a voltage reference source, a buck regulator, a boost regulator, and a D / A voltage reference source; There are N buck regulators, denoted as the first buck regulator to the Nth buck regulator; each buck regulator has the same structure; the first buck regulator is composed of a first BUCK converter, a second BUCK converter, a third BUCK converter, a fourth BUCK converter, a first LDO regulator, and a second LDO regulator; There are N voltage reference sources, denoted as the first voltage reference source to the Nth voltage reference source; Each voltage reference source has the same structure; The first voltage reference source is composed of a first reference voltage, a second reference voltage, and a fifth BUCK converter; There are N D / A voltage reference sources, denoted as the first D / A voltage reference source to the Nth D / A voltage reference source; each D / A voltage reference source has the same structure; The first buck regulator and the first voltage reference source form the FPGA power supply module. The external main power supply voltage is stepped down by the first buck regulator. Among them, the first voltage reference source provides a reference voltage for the first buck regulator and provides power for the FPGA control module; There are N drive channel modules, which are respectively denoted as the first drive channel module to the Nth drive channel module. Each drive channel module includes a decoder, a digital-to-analog converter, an analog switch matrix, a voltage follower, and a multi-channel voltage amplifier. Among them, the decoder and the digital-to-analog converter receive the FPGA digital signal, use the decoder to open the analog switch, and transmit the analog signal of the digital-to-analog converter to the voltage follower through the analog switch for signal buffering. The voltage follower inputs the buffered analog signal into the corresponding channel of the multi-channel voltage amplifier; The digital-to-analog converter group includes N digital-to-analog converters, which are respectively denoted as the first digital-to-analog converter to the Nth digital-to-analog converter; The analog switch matrix includes Z analog switches, which are respectively denoted as the first analog switch to the Zth analog switch; There are Z voltage followers, which are respectively denoted as the first voltage follower to the Zth voltage follower; There are N decoders, which are respectively denoted as the first decoder to the Nth decoder. The decoder converts the digital signal output by the FPGA control module into an enable signal for driving the analog switch to open; The digital-to-analog converter has A analog signal output channels, which converts the digital signal output by the FPGA control module into an initial analog signal for driving the deformable mirror device. The analog signal is transmitted to the voltage follower through the analog switch; The structure and function of each analog switch are the same. The analog switch receives the enable signal output by the decoder, bidirectionally opens the analog switch of the corresponding channel, enables the analog signal of the digital-to-analog converter to be input to the analog switch of the corresponding channel, and the analog switch then outputs the analog signal to the bound voltage follower; There are A voltage followers, and the structure and function of each voltage follower are the same. It is used to buffer and electrically isolate the analog signal output by the analog switch, ensure the stability of the signal, and output the buffered analog signal to the multi-channel voltage amplifier; The multi-channel voltage amplifier amplifies the analog voltage signal output by the voltage follower and outputs a high-voltage signal for driving the corresponding unit of the deformable mirror; The driving channel power supply module steps down the external total power supply through a buck regulator to convert it into a stable power supply for monitoring the operation of the module and the driving channel module; the external total power supply voltage is stepped up through a boost regulator to convert it into a stable power supply for the operation of the multi-channel voltage amplifier in the driving channel module; the voltage reference source provides a reference voltage for the buck regulator, and the D / A voltage reference source provides a reference voltage for the digital-to-analog converter in the driving channel module; The FPGA control module includes a clock synchronization module, a digital-analog mixed signal processing module, a bus data interface, a data control module, and a monitoring control module; The clock synchronization module is used to reduce the frequency of the 50MHZ clock input by the FPGA control module and output the SPI_CLK clock for each module of the FPGA control module to use; the SYS_RST signal input by the clock synchronization module is a global reset signal, and the SYS_RST signal will be passed to each module of the FPGA control module; The digital-analog mixed signal processing module includes an SPI protocol 1 module, an SPI protocol data control module, and a read-write FIFO module; the SPI protocol 1 module is used to transmit data through the SPI protocol, and the SPI protocol data control module is used to integrate the data transmitted by the SPI protocol 1 module; the read-write FIFO module is used to process the data to be written to the digital-to-analog converter by the buffer data control module and the channel feedback data of the digital-to-analog converter transmitted from the SPI protocol data control module; The digital-analog mixed signal processing module buffers, integrates, and processes the digital signal and enable signal output by the data control module, and then outputs the processed data to the digital-to-analog converter; when inputting, it sends a digital signal for reading a specified channel to the digital-to-analog converter, reads the digital signal of the specified channel output by the digital-to-analog converter, and then performs processing, integration, and buffering operations to read the output data to the data control module; The data control module includes a channel data distribution module and an enable module; the channel data distribution module sends an enable signal to the enable module, and the enable module receives the enable signals of the total data interface and the digital-analog mixed signal processing module and integrates them, and issues an enable signal for the decoder of the driving channel module; When inputting, the data control module receives the channel data and enable signal output by the bus data interface, and at the same time receives the digital signal and enable signal processed by the digital-analog hybrid signal processing module. When outputting, it reads the closed-loop signal and outputs it to the bus data interface, and outputs the digital signal and enable signal for driving the analog switch matrix to the decoder; The bus data interface includes a total data module, SPI protocol 2, and an EEPROM storage module; When inputting, the bus data interface uses SPI protocol 2 to transmit the data of the monitoring control module and the data of the data control module to the total data module for processing. When outputting, it outputs the channel data and enable signal to the data control module; the EEPROM storage module is used to store the channel feedback data of the digital-to-analog converter transmitted from the data control module, and can also store the data to be written to the digital-to-analog converter in the past and present; There are N groups of the monitoring modules, denoted as the first monitoring module to the Nth monitoring module, and each monitoring module includes a distributed digital temperature sensor and a current monitor; The monitoring control module is used to integrate the digital signals read by the distributed digital temperature sensor and the current monitor and transmit them into the bus data interface for processing; The monitoring control module includes a temperature processing module, a current processing module, and a detection data fusion module; the temperature processing module processes the sensor temperature data and then transmits it to the detection data fusion module, and the current processing module processes the sensor current data and then transmits it to the detection data fusion module; the monitoring control module performs data fusion processing with the FPGA control module to achieve the distribution and closed-loop feedback control of multi-channel data; The distributed digital temperature sensor is powered by the first buck regulator, detects the temperature coefficient of the multi-channel voltage amplifier, and transmits the digital signal to the FPGA control module through the register; The current monitor is powered by the buck regulator of the drive channel power supply module, monitors the current of the high-voltage line output by the boost regulator of the drive channel power supply module, and transmits the digital signal generated by the current monitor to the FPGA control module through the SPI protocol; the deformable mirror device is a planar array system composed of piezoelectric ceramic units. The deformable mirror device controls the deformation amount of the piezoelectric ceramic by dynamically adjusting the voltage applied to each ceramic unit, thereby achieving high-precision correction of the light beam wavefront; the voltage control signal output by the multi-channel voltage amplifier of the drive channel is distributed to each ceramic unit in a vector form.

2. The control circuit for a deformable mirror device driver according to claim 1, characterized in that, The first buck regulator is powered by the total power supply of 12V, and steps down the 12V power supply to 7V output through the first BUCK converter of the first buck regulator; the second BUCK converter steps down to 5V output; the 12V output power supply is stepped down to 1.2V output through the fourth BUCK converter; the 5V output power supply is stepped down to 3.3V output through the third BUCK converter, and the 3.3V output power supply is stepped down to 1.5V output through the first LDO regulator; the 3.3V output power supply is stepped down to 2.5V output through the second LDO regulator; After the first step-down regulator steps down the voltage, the second BUCK converter therein steps down the voltage to supply the power supply voltage input for the FPGA control module; The third BUCK converter and the first LDO regulator are used in combination to become the I / O port voltage input for the FPGA control module; The second LDO regulator is the PLL analog voltage input for the FPGA control module; The fourth BUCK converter is the core voltage input for the FPGA control module; After the first step-down regulator steps down the voltage, the output voltage of the first BUCK converter therein is the power supply input for the first multi-channel voltage amplifier of the first drive channel; The second BUCK converter is the power supply input for the first digital-to-analog converter of the first drive channel; The second BUCK converter supplies power to the decoder, analog switch, and voltage follower of the first drive channel module; The 5V power supply output by the second BUCK converter is converted to -5V through the first flyback converter, which is the -5V power supply input for the first multi-channel voltage amplifier of the first drive channel module; The second BUCK converter of the first step-down regulator also provides a 5V power supply for the first digital temperature sensor and the first current monitor of the first monitoring module.

3. The control circuit for a deformable mirror device driver according to claim 2, wherein, The first voltage reference source is powered by the total power supply of 12V. The 12V power supply is converted to 3.3V output through the fifth BUCK converter; the 3.3V power supply is converted to 1.2V output and 2.5V output through the first reference voltage and the second reference voltage. The 1.2V output is used as the voltage reference source for the fourth BUCK converter, and the 2.5V output is used as the voltage reference source for the second LDO regulator; The first D / A voltage reference source is powered by the total power supply of 12V. The 12V power supply is converted to 5V output through the second BUCK converter; the 5V power supply is converted to 2.5V output through the third reference voltage. The 2.5V output is used as the reference voltage for the first digital-to-analog conversion chip of the first drive channel, providing a reference voltage for the analog output signal.

4. The control circuit for a deformable mirror device driver according to claim 3, wherein, The structures and functions of the N groups of boost regulators are the same; the first boost regulator is powered by the total power supply of 12V. The 12V power supply is boosted to 250V output through the first BOOST conversion circuit, providing a 250V power supply input for the first multi-channel voltage amplifier; the current on the output voltage side of the first boost regulator is detected by the first current monitor of the first monitoring module.

5. The control circuit for a deformable mirror device driver according to claim 4, wherein, The digital-analog hybrid signal processing module of the FPGA control module buffers the digital signal and the enable signal output by the data control module into the write FIFO, and then transfers the buffered data in the FIFO to the SPI protocol data control module for SPI protocol data integration. Finally, the control data is written into the first digital-to-analog converter of the first drive channel through the SPI protocol 1 module; The digital-analog hybrid signal processing module processes the digital signal read from the channel by the first digital-to-analog converter through the SPI protocol and transfers it to the SPI protocol 1. After the digital signal is transferred to the SPI protocol data control module for data integration, it is then transferred to the read FIFO for buffering and finally sent to the data control module.

6. The control circuit for a deformable mirror device driver according to claim 5, wherein, The data control module transmits the digital signals and enable signals processed by the bus data interface to the data distribution module and the enable module for distribution, and transmits the distributed channel data and enable signals to the write FIFO, and transmits the signals to the decoder; The data control module transmits the data and enable output from the read FIFO to the data distribution module and the enable module for processing, and then reads the processed data and enable signals out to the bus data interface.

7. The control circuit for a deformable mirror device driver according to claim 6, wherein, The bus data interface transmits the signals output from the monitoring control module and the data and enable signals output from the data control module to the total data module for sorting, and outputs the data and enable signals to the data control module for processing; The total data module can hold the input and output data, divides the EEPROM storage module into two storage areas for input and output data as the storage end, transmits the data to be stored to the storage end through the SPI protocol 2, and then loops back to the total data module for signal closed-loop processing.

8. The control circuit for a deformable mirror device driver according to claim 7, wherein, The monitoring control module transmits the data read by the first digital temperature sensor through the register to the temperature processing module for processing; The monitoring control module reads data through the SPI protocol from the first current monitor and transmits it to the current processing module for processing; The information processed by the temperature processing module and the current processing module is respectively sent to the detection data fusion module for data processing and integration, and finally the data is output to the bus data interface.

9. The control circuit for a deformable mirror device driver according to claim 8, wherein, The detection data fusion module of the monitoring control module includes: a temperature signal, a filter, and a temperature PI for temperature control, and a current signal, a filter, and a current PI for current control; The data of the temperature PI and the current PI are put into the output conditioning of the detection data module for signal processing, and then the processed signals are sent to the bus data interface.

10. The control circuit for a deformable mirror device driver according to claim 9, wherein, The detection data fusion module adopts discretization to implement the incremental PI control algorithm, including: calculating the deviation between the input signal and the reference signal to generate the current error signal e(n): ， wherein is the reference input at the n-th moment, is the actual output of the system at the n-th moment; The error signal e(n) is processed through dual-channel parallel processing: one of the two channels is multiplied by the integral coefficient KI to generate an integral adjustment amount; the other channel is stored in a register as the historical error input e(n-1) for the proportional term operation in the next control cycle; the proportional term is obtained by multiplying the proportional coefficient KP by the historical error e(n-1) in the register; then the integral term and the proportional term are vectorially combined to obtain the incremental adjustment amount ΔU(n) of the current control cycle: ， wherein is a proportionality coefficient, is an integral coefficient; The incremental adjustment amount is algebraically superimposed with the control amount U(n-1) at the previous moment to obtain the output control amount: ， wherein is the control quantity output at the current moment; Update the error register: ， Store the current error in a register for use in the next cycle; the symbol indicates that the value of .

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