Cache consistency system, method and device, electronic device and storage medium

Abstract

The invention discloses a cache consistency system, method and device, an electronic device and a storage medium, and relates to the technical field of computers.A request buffer area is arranged between a master node and a slave node, the slave node can monitor the blocking condition of each memory access request in the request buffer area, and the cache consistency is improved. When the request blocking degree of any processor core reaches the preset blocking threshold value, the priority of the memory access request of the processor core is improved in the request buffer area, so that the situation that the slave node does not respond to the memory access request of a certain processor core in time is avoided, and the overall performance of a system is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a cache coherence system, method, device, electronic device, and storage medium. Background Art

[0002] In a multi-core processor system, the problems of cache data inconsistency and memory access latency are becoming increasingly prominent, seriously restricting system performance. Therefore, how to solve these problems based on a cache coherence protocol has become the focus of research.

[0003] In related technologies, as an important cache coherence protocol, the Coherent Hub Interface (CHI) protocol has a network architecture including multiple node types. Among them, the slave node is responsible for receiving the memory access requests sent by the master node and making responses. In the scenario of a multi-core processor, memory access requests often correspond to different processor cores. However, due to the limited response speed of storage devices such as system memory, situations such as the slave node not responding in a timely manner to the memory access requests of a certain processor core often occur, resulting in a decline in the overall system performance. Summary of the Invention

[0004] This application provides a cache coherence system, method, device, electronic device, and storage medium to at least solve the problem in related technologies that the slave node does not respond in a timely manner to the memory access requests of a certain processor core, resulting in a decline in the overall system performance.

[0005] This application provides a cache coherence system, including: a request node, a master node, and a slave node, with a request buffer provided between the master node and the slave node;

[0006] The request node is configured to receive a cache operation request initiated by any processor core and send the cache operation request to the master node;

[0007] The master node is configured to receive the cache operation request, and in the case where it is determined that the cache operation request belongs to an external storage operation request, write a corresponding memory access request into the request buffer;

[0008] The slave node is configured to access the request buffer and sequentially respond to the access requests in the request buffer based on the cache coherence protocol. When any memory access request in the request buffer meets a preset priority response condition, the memory access request is used as a priority response request;

[0009] Among them, the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches a preset blocking threshold.

[0010] This application also provides a cache coherence method, which is applied to the slave node in any of the above cache coherence systems. The method includes:

[0011] By accessing the request buffer, obtain the memory access request sent by the master node; among them, when the master node determines that any cache operation request initiated by a processor core received belongs to a peripheral storage operation request, write the corresponding memory access request into the request buffer;

[0012] Respond to the access request in order based on the cache coherence protocol;

[0013] When any memory access request in the request buffer meets the preset priority response condition, use this memory access request as the priority response request;

[0014] Prioritize the response to the priority response request;

[0015] Among them, the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches the preset blocking threshold.

[0016] This application also provides a cache coherence device, which is characterized by including: a multi-core processor and the cache coherence system of any one of the above;

[0017] Each processor core in the multi-core processor corresponds to a request node in the cache coherence system one by one.

[0018] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above cache coherence methods when executing the computer program.

[0019] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above cache coherence methods are implemented.

[0020] This application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any one of the above cache coherence methods are implemented.

[0021] Through this application, since a request buffer is set between the master node and the slave node, the slave node can monitor the blocking situation of each memory access request in the request buffer. When the request blocking degree of any processor core reaches the preset blocking threshold, the priority of the memory access request of this processor core is increased in the request buffer to avoid the situation that the slave node fails to respond to the memory access request of a certain processor core in a timely manner, thereby improving the overall performance of the system. Description of the Drawings

[0022] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a schematic diagram of the network structure of the CHI protocol provided by the embodiment of the present application;

[0024] Figure 2 It is a schematic diagram of the interaction process of the cache coherence system provided by the embodiment of the present application;

[0025] Figure 3 It is a schematic diagram of the operation process of the request module provided by the embodiment of the present application;

[0026] Figure 4 It is a schematic diagram of the operation process of the send response module provided by the embodiment of the present application;

[0027] Figure 5 It is a schematic diagram of the operation process of the send data module provided by the embodiment of the present application;

[0028] Figure 6 It is a schematic diagram of the process of the read operation of the slave node provided by the embodiment of the present application;

[0029] Figure 7 It is a schematic diagram of the operation process of the receive data module provided by the embodiment of the present application;

[0030] Figure 8 It is a schematic diagram of the process of the write operation of the slave node provided by the embodiment of the present application;

[0031] Figure 9 It is a schematic diagram of the structure of the preset transport layer provided by the embodiment of the present application;

[0032] Figure 10 It is a schematic diagram of the overall structure of the cache coherence system provided by the embodiment of the present application;

[0033] Figure 11 It is a schematic diagram of the process of the cache coherence method provided by the embodiment of the present application;

[0034] Figure 12 It is a schematic diagram of the structure of the cache coherence device provided by the embodiment of the present application;

[0035] Figure 13 It is a schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0037] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0038] In a multi-core processor system, each processor is usually equipped with its own cache (private cache), and multiple processors may also share a cache (shared cache) for storing data with high access frequencies. When multiple processors access or modify shared data simultaneously, problems such as data inconsistency and memory access latency will occur. To solve the above problems, cache coherence protocols need to be introduced in multi-processor systems. These protocols define how processors share and synchronize cache data to ensure that all processors can see a consistent data view. By specifying the rules that processors must follow when reading and writing cache data, cache coherence protocols can prevent data inconsistency. Although cache coherence protocols will increase certain communication and synchronization overheads, they can improve the overall system performance by reducing unnecessary memory accesses and cache misses.

[0039] The Coherent Hub Interface (CHI) protocol, as an important cache coherence protocol, is used to build various systems from small to large, which use multiple components, including processor clusters, graphics processors, memory controllers, I / O bridges, PCIe subsystems, and the interconnect itself. CHI protocol nodes are the key components that make up the CHI network. They are responsible for generating, processing requests and responses, and maintaining cache coherence, such as Figure 1As shown in the figure, it is a schematic diagram of the network structure of the CHI protocol provided by the embodiment of the present application. In the CHI network, there are mainly four types of nodes: a request node (RN), a home node (HN), a slave node (SN), and a miscellaneous node (MN) not shown in the figure. The RN node is used to generate protocol transactions for interconnection, including read and write operations; the HN node is used to receive protocol transactions from the RN, complete corresponding coherence operations, and return a response; the SN node is used to receive requests from the HN, complete corresponding operations, and return a response; the MN node is used to receive DVM operations from the RN, complete corresponding operations, and return a response.

[0040] The CHI protocol maintains cache coherence by defining cache state transitions on nodes and the transmission processes for each request type. I: Invalid, the data in this cache line is not in the current cache; UC: Unique Clean, the data in this cache line is only in the current cache and is consistent with the data in the main memory; UD: Unique Dirty, the data in this cache line is only in the current cache and is inconsistent with the data in the main memory and has been modified; SC: Shared Clean, other caches may also have copies of this cache line, and this cache line may have been modified; SD: Shared Dirty, other caches may also have copies of this cache line; this cache line has been modified relative to the main memory.

[0041] In the CHI protocol, the SN node plays an important role. The SN node is mainly used to receive requests from the HN (Home Node), complete corresponding operations, and return a response. The communication with other nodes (such as HN, RN, etc.) is based on channels. A channel is a logical path for transmitting information between nodes. The CHI protocol defines multiple types of channels, including Request (REQ), Response (RSP), Snoop (SNP), and Data (DAT), etc.

[0042] The SN node starts operations by receiving requests from the HN. Taking peripheral storage as memory as an example, these requests may include reading memory data, writing memory data, or performing other types of operations.

[0043] Among them, the channel types involved by the SN node are shown in Table 1:

[0044] Table 1

[0045] TX Channel RX Channel REQ Channel RXREQ DAT Channel TXDAT RXDAT RSP Channel TXRSP

[0046] After receiving a request, the SN node will perform corresponding operations according to the type and content of the request. For example, if the request is to read memory data, the SN node will read the data from the specified memory address; if the request is to write memory data, the SN node will write the data to the specified memory address. After the operation is completed, the SN node will generate a response packet and send it back to the HN node to confirm the completion and result of the operation.

[0047] However, since the slave node is usually connected to the peripheral storage for data interaction operations between the processor and the storage, and since the processor speed is much faster than the memory operation speed, situations such as the slave node not timely responding to the memory access requests of a certain processor core often occur, resulting in a decline in the overall performance of the system.

[0048] The embodiment of the present application provides a cache coherence system, method, device, electronic device and storage medium to solve the above technical problems. By setting a request buffer between the master node and the slave node; the request node is used to receive the cache operation request initiated by any processor core and send the cache operation request to the master node; the master node is used to receive the cache operation request and, when it is determined that the cache operation request belongs to the peripheral storage operation request, write the corresponding memory access request into the request buffer; the slave node is used to access the request buffer and sequentially respond to the access requests in the request buffer based on the cache coherence protocol. When any memory access request in the request buffer meets the preset priority response condition, the memory access request is taken as the priority response request; wherein, the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches the preset blocking threshold. The system provided by the above solution monitors the blocking situation of each memory access request in the request buffer by the slave node. When the request blocking degree of any processor core reaches the preset blocking threshold, the priority of the memory access request of the processor core is increased in the request buffer to avoid the situation that the slave node does not timely respond to the memory access request of a certain processor core, thereby improving the overall performance of the system.

[0049] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the following further details the present application in conjunction with the drawings and specific embodiments.

[0050] The embodiment of the present application provides a cache coherence system for ensuring the timely response of the memory access requests of the slave nodes to each processor core in the CHI protocol network architecture.

[0051] As Figure 2 shown, it is a schematic diagram of the interaction process of the cache coherence system provided by the embodiment of the present application. The system includes: a request node, a master node and a slave node, and a request buffer is provided between the master node and the slave node.

[0052] Among them, the request node is used to receive cache operation requests initiated by any processor core and send the cache operation requests to the master node; the master node is used to receive the cache operation requests and write corresponding memory access requests into the request buffer when it is determined that the cache operation request belongs to a peripheral storage operation request; the slave node is used to access the request buffer and sequentially respond to the access requests in the request buffer based on the cache coherence protocol. When any memory access request in the request buffer meets the preset priority response condition, the memory access request is used as the priority response request.

[0053] Among them, the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches the preset blocking threshold.

[0054] It should be noted that the request nodes correspond one-to-one with the processor cores. In actual applications, the processor cores can also be called request nodes. The processor cores generate cache operation requests according to business requirements, such as reading or writing data in the cache.

[0055] Specifically, when the master node receives a cache operation request sent by a request node, it will determine whether the request belongs to a peripheral storage operation request. A peripheral storage operation request refers to an access request to the storage area of an external device (such as memory, hard disk, USB flash drive, etc.). If it is a peripheral storage operation request, the master node writes the corresponding memory access request into the request buffer. The slave node is responsible for accessing the memory access requests in the request buffer and sequentially responding to these requests according to the cache coherence protocol. The cache coherence protocol is a set of rules that ensure the data in each cache in the system is consistent and avoid data inconsistency. The caches in the system include the request node caches of each request node, the master node cache, and the peripheral storage. In addition, when the slave node finds that any memory access request meets the preset priority response condition, it takes this memory access request as the priority response request and processes it preferentially. Specifically, when the request blocking degree of the processor core corresponding to a certain memory access request reaches this preset blocking threshold, the memory access request is regarded as the priority response request and processed preferentially to relieve the blocking of the processor core and avoid affecting the operation efficiency of the entire system due to long-term waiting.

[0056] Based on the above embodiments, as an implementable manner, in one embodiment, the master node is used to obtain the current state information of the master node cache when receiving a cache operation request sent by any request node; and determine whether the cache operation request belongs to a peripheral storage operation request according to the current state information of the master node cache and the operation requirement information of the cache operation request.

[0057] Among them, the current state information of the master node cache at least includes the currently stored data content, the validity of the data, the sharing state of the data, etc.

[0058] Specifically, it is possible to combine the operation requirement information of the cache operation request, such as whether it is a read request or a write request and the address requested to be accessed, etc., to determine whether the cache operation request belongs to the peripheral storage operation request. Specifically, it is possible to determine that the cache operation request belongs to the peripheral storage operation request when the address requested to be accessed is the peripheral storage address or the data requested to be accessed by the main node buffer is not stored in the main node buffer.

[0059] Specifically, in one embodiment, the main node is further configured to, when determining that the cache operation request does not belong to the peripheral storage operation request, respond to the cache operation request based on the main node buffer according to the cache coherence protocol, and return the response result to the corresponding request node.

[0060] Specifically, when determining that the cache operation request does not belong to the peripheral storage operation request, the main node can respond to the cache operation request based on its own main node buffer. For example, when it is a read request, the corresponding data is read from the main node buffer, and when it is a write request, the data in the main node buffer is updated. After the processing is completed, the main node returns the response result to the corresponding request node, enabling the request node to obtain the operation result and continue the subsequent processing work. This can efficiently process the operations related to the local cache, reduce unnecessary access to the peripheral storage, and improve the system performance.

[0061] Based on the above embodiments, as an implementable manner, in one embodiment, the slave node includes:

[0062] A request module, configured to access the request buffer, extract the memory access request to be responded in the request buffer, parse the access request to obtain request parsing information, and when the request parsing information indicates that the memory access request is a read request, send the request parsing information to the data sending module, and when the request parsing information indicates that the memory access request is a write request, send the request parsing information to the data receiving module;

[0063] A data sending module, configured to execute the read operation represented by the memory access request according to the obtained parsing information;

[0064] A data receiving module, configured to execute the write operation represented by the memory access request according to the obtained parsing information.

[0065] It should be noted that the request buffer includes a request buffer queue. The request module in the slave node is responsible for receiving the instruction (memory access request) from the request FIFO (request buffer queue) and performing corresponding parsing to obtain the request parsing information, and then transmitting the instruction and the corresponding request parsing information to the corresponding module. The request parsing information includes the memory access request instruction itself and the write operation information or read operation information of the memory access request. The write operation information and the read operation information at least include the read and write addresses.

[0066] It should be further noted that by dividing the data sending module and the data receiving module in the slave node provided by the embodiment of the present application, parallel processing of write operations and read operations is achieved, improving the response efficiency of the slave node to memory access requests.

[0067] Specifically, for a read request, the operations to be performed include transmitting the information required for assembling the data packet of the coherence protocol to the data sending channel storage and waiting for the data to return in the data sending channel; transmitting the information required for converting the storage bus channel signal to the transport layer; and when a feedback response is required, transmitting the information required for assembling the response to the response sending channel. For a write request, the operations include transmitting the information required for returning the response to the response sending channel, transmitting information such as addr to the data receiving channel, waiting for the corresponding data to be sent, and then sending them together to the preset transport layer and converting them into write address and write data channel signals.

[0068] Among them, as Figure 3 shown, it is a schematic diagram of the operation process of the request module provided by the embodiment of the present application. The entire operation is divided into a four-stage pipeline of S0 to S3:

[0069] S0: After successfully shaking hands with the request FIFO, fetch the instruction and perform decoding (parsing), fetch the corresponding position for assignment operation. After the assignment is completed, according to the operation code of the instruction, determine the direction of generating the request information (request parsing), and transmit the corresponding data required for the request. After the processing is completed, send a ready (ready signal) to the corresponding lower-level module. After successfully shaking hands with the lower-level module, set the request module register of if to 1.

[0070] S1: After decoding, distinguish the read and write requests and send them to different modules for packaging, and then transmit them to the lower-level module together with the request. After the packaging is completed, send ready, and after successfully shaking hands, send the request module register. In this stage of the pipeline, the read request information will be synchronously sent to the prefetch module for memory access mode check.

[0071] S2-1: For a read request, send the corresponding information to TxDat (data sending module) for recording. If a response needs to be returned, send the corresponding information to TxRsp (response sending module) to return the response. After the sending is completed, set ready to 1 for the lower level, and set the request module register of the upper level to 1 after successfully shaking hands.

[0072] S2-2: For a write request, send the information to RxDat (data sending module) and wait for the data to return from the upper node. At the same time, send it to TxRsp (response sending module) to make it return the corresponding response according to the above two situations. After the sending is completed, set the request module register of the upper level to 1.

[0073] S3: For a read request, send the data to the transport layer, and set the request module register to 1 after the sending is completed.

[0074] Specifically, in one embodiment, the slave node further includes a response sending module, configured to receive a response instruction sent by the request module or the data receiving module, and in response to the response instruction, generate a corresponding response packet, and write the response packet into the request buffer for feedback to the master node through the request buffer.

[0075] Wherein, the request module is configured to send a response instruction to the response sending module when it is determined that the data sending module has completed a read operation; the data receiving module is configured to send a response instruction to the response sending module when obtaining the parsing information corresponding to a write operation.

[0076] Specifically, as Figure 4 shown, it is a schematic diagram of the operation process of the response sending module provided by an embodiment of the present application. The response sending module (TxRsp) is configured to return a response to a superior, receive information from the request module and the data receiving module, and return a corresponding response.

[0077] Wherein, for a read transaction, when the request module Req sends a read transaction request, these requests are distinguished by different numerical values of different bits. For example, a certain bit being 1 represents a specific read request, and being 0 represents another. The response sending module TxRsp performs a handshaking operation with Req. Only when the handshaking is successful (that is, after processing the task, set ready to 1, and when the handshaking with the lower-level module is successful, set req to 1, and req&&ready is true), will TxRsp receive the corresponding data at the corresponding position according to the specific content of the request. After receiving the data, TxRsp assembles it into a response packet, then transmits it to the next-level module, and finally sends it to the response sending buffer queue through the read port, thus completing the operation of returning a read transaction response to the superior. Wherein, the request buffer includes the response sending buffer queue.

[0078] Wherein, for a write transaction, when a write transaction occurs and a response needs to be returned, after the data receiving module RxDat completes data reception, it will return the corresponding data and the request signal (req) to TxRsp together. After receiving these data and signals, TxRsp performs a packaging process to form a response packet for the write transaction. Similarly, after TxRsp finishes processing the task, it will set ready to 1, and when the handshaking with the lower-level module is successful, set req to 1. When req&&ready is true (handshaking is successful), the response packet is sent to the response sending buffer queue through the write port to implement returning a write transaction response to the superior node.

[0079] Specifically, in one embodiment, the data sending module is used to determine the target read data and the corresponding target read times according to the obtained parsed data; read the target read data from the peripheral storage through a preset transport layer, and when the read times reach the target read times, perform packet processing on the read target read data to obtain a target read data packet; determine the target buffer queue of the target read data packet according to the memory access type corresponding to the target read data packet; add a check bit to the target read data packet and then write the target read data packet into the target buffer queue.

[0080] Among them, the memory access types are at least divided into a normal type and a prefetch type, the request buffer includes multiple buffer queues, and the buffer queues are at least divided into a data sending buffer queue and a prefetch storage queue.

[0081] It should be noted that the data sending module (TxDat) is used to return a data response read to the upper level when receiving a read transaction, and needs to store the data information obtained from the request channel and combine it with the data returned by the memory bus, and then assemble it into a data packet and return it. This module needs to be enabled when the request received in the request module is a read request, and is used to store information such as the identifier in the read request (request parsing information). After the data returns from the lower-level memory bus, the corresponding information is retrieved by comparing the identifier, and after assembling it into a data packet according to the request information, it is returned to the data sending buffer queue or the prefetch storage queue according to the memory access request type.

[0082] Specifically, as Figure 5 shown, it is a schematic diagram of the operation process of the data sending module provided by the embodiment of the present application. The whole operation is divided into three-level pipelines S0 to S2:

[0083] S0: After the request module (Req) determines that the received request is a read request, it transmits the corresponding information (parsing information) to the data sending module (TxDat). This information includes key contents such as the identifier and address of the read request. TxDat performs an instruction fetch operation, that is, obtains instruction information related to the read request. After receiving the information and when the register (td_reg) inside TxDat is not full, the received information is recorded in the register and waits for the corresponding data to be returned from the lower-level memory bus. At the same time, the corresponding counter is recorded as the number of times required to transmit a group of data (target read times), and this counter is used to track the progress of data transmission subsequently.

[0084] S1: According to the request type information recorded in the register (td_reg), determine which response data should be returned subsequently. For different read requests, TxDat only stores the information necessary to assemble the corresponding data packet to avoid occupying too many resources. By comparing the number of rows in the register with the number of non-zero counters, it is judged whether the register is full. If the two are not equal, it means that there is still space in the register to store new data or information.

[0085] S2: For the data return operation corresponding to a read request, each time, find the corresponding row in the register through the identification information, retrieve the relevant information stored therein, and merge it with the data returned from the lower-level memory bus to form a complete data packet. After successfully retrieving the information and completing the handshake operation each time, decrement the value of the counter. When the counter value is 0, it indicates that all the data in this row has been processed, and the data in this row is invalid, and new data can be stored in this row subsequently. After completing the reception of the data returned from the lower-level memory bus, TxDat differentiates whether the memory access type is prefetch or normal type. Prefetch is to obtain the data that may be used in advance, and the normal type is a regular read data request. According to different memory access types, add parity bits according to the corresponding rules to ensure the accuracy of the data during transmission. Then, send the data to the prefetch storage queue and the data transmission buffer queue respectively. The prefetch storage is used to store the data obtained in advance, and the data transmission buffer queue is used to send the data to the master node subsequently.

[0086] Among them, as Figure 6 shown, it is a schematic flowchart of the slave node read operation provided by the embodiment of the present application. The master node sends a read request (ReadNoSnp request), and this request enters the slave node. When the master node requests to feedback the ReadReceipt information, the slave node will feedback a response signal to the master node. After receiving the read request, the slave node extracts relevant information from the read request inside it, such as key contents like the requested address. Then, this information passes through the preset transport layer of the slave node and is converted into the signal format required by the read address channel according to the requirements of other protocols (such as the AXI protocol). After that, the converted signal is sent to peripheral storages such as DDR / Flash. At this time, the slave node is in a state of waiting for the peripheral storage to return data. The peripheral storage finds the corresponding data in its own storage area according to the received read request address information. Then, the data is fed back to the preset transport layer of the slave node through the read data channel. The preset transport layer extracts relevant information from the returned data and assembles it into a read data packet in the slave node. Finally, this read data packet is sent back to the master node, and thus the processing of the entire ReadNoSnp transaction is completed, enabling the master node to obtain the data it requests.

[0087] Specifically, in one embodiment, the receive data module is used to obtain a target write data packet according to the obtained parsed data; verify the check bits of the target write data packet; when the target write data packet passes the check bit verification, compare the data identifier of the target write data packet with the request identifier of the access request represented by the parsed information; when it is determined that the data identifier and the request identifier match, extract the target write address information from the parsed data; pack the target write data packet and the target write address information to obtain a target write operation packet, and send the target write operation packet to a preset transport layer; based on the preset transport layer, convert the target write operation packet into a target write data channel signal to write the target write data packet to the target write address through the write data channel.

[0088] It should be noted that the receive data module (RxDat) is applicable in write transactions and is used to receive write data packets and forward them to the transport layer, and forward them to the response channel if necessary. This module needs to be enabled when the request received by the request module is a write request, record the signals required for the subsequent write address channel and the signals required for comparison, and send the received data after receiving it. There are two types of received RxDat. One is valid data, and the operation is to send it to the transport layer in combination with the corresponding address; the second is to cancel the write data, and the operation is to delete the recorded address information.

[0089] Specifically, in one embodiment, the receive data module is further used to submit a verification failure signal to an error register when the target write data packet fails the check bit verification, so that the master node re-uploads the target write data packet. Among them, the cache coherence system includes an error register.

[0090] Among them, as Figure 7 shown, it is a schematic diagram of the operation process of the receive data module provided by the embodiment of the present application. The entire operation is divided into a three-stage pipeline of S0 to S2:

[0091] S0: The write request information sent from the request module (Req) enters the receive data module (RxDat). This part of the information contains the key content of the write operation, such as operation type, target address and other related instructions. After RxDat shakes hands successfully with Req, the write request information is stored in the register (rd_reg). At the same time, an initialization operation is performed on this line of data. The counter value is set to the number of times the upper module needs to transmit data, which is used to track the data transmission progress subsequently; the valid bit is set to 1, indicating that this line of data is currently valid and can be used for subsequent processing.

[0092] S1: Wait for the upper node to return the write data. The data will first enter the receive data buffer queue, and then RxDat performs a check based on the parity bit in the data. The check is to ensure that the received data has not been corrupted during transmission, such as through parity check, cyclic redundancy check (CRC), etc. If the check is successful, the identifier of the returned data is compared with the identifier previously stored in the register. If the two are the same, it means that the returned data is the data required for the corresponding write request. At this time, the corresponding address information is retrieved from the register and merged with the data in the packet bus module. Each time a merge operation is completed, the counter value is decremented by one. When the counter value is 0, it means that no new data will be returned for this row. If the check fails, a signal is submitted to the error register to request the upper node to retransmit the data. If an error-correcting check method (such as LDPC) is used, an attempt is made to correct the error data at this stage. Among them, the error register is used to report the exception information of the slave node.

[0093] S2: Send the merged data packet in the S1 stage to the preset transport layer. The transport layer will convert the data packet into a signal form that meets the requirements of the write address and write data channel, so as to write the data to the target write address through the write data channel. If the write operation requires a feedback signal, when the counter is 0, RxDat sends a signal to the transmit response module (TxRsp) to let TxRsp return a response signal to the upper module to inform the processing status of the write operation. If the counter is 0 and no response is required, the valid bit of the data in this row is set to 0, indicating that the data in this row is invalid, and new data can be stored subsequently. By comparing the number of rows in the register with the number of bits with a valid bit of 1 (valid is 1), it is judged whether the register is full. If they are not equal, it means that there is still free space in the register for storing new data.

[0094] Among them, as Figure 8 shown, it is a schematic flow diagram of the slave node write operation provided by the embodiment of the present application. The master node sends a write request (WriteNoSnoop transaction) to the slave node. After the slave node successfully receives the write request, it will feedback a write response signal (CompDBIDResp information) to the master node. After the master node receives this write response signal, it sends the write data to the slave node, which completes the request and preparation work in the early stage of the write operation. After the slave node receives the write request and write data, it processes this information. Specifically, the write request and data information can be converted into a signal form that conforms to the consistency protocol channel of the peripheral storage connection. After the conversion is completed, these signals are sent to the peripheral storage (DDR / Flash). Then, the slave node waits for the peripheral storage to return a response signal. When the response signal is received, the entire write operation process is completed.

[0095] Specifically, in one embodiment, the cache coherence system further includes a preset transport layer for encrypting the target write operation packet before converting it into a target write data channel signal.

[0096] Specifically, as Figure 9 shown, it is a schematic structural diagram of the preset transport layer provided by the embodiment of the present application. For a write data request, the preset transport layer encrypts the received data sent by the RxDat module, then transmits it to the bus interface concentration, converts it into the data format of the corresponding protocol channel, and sends it to the lower-level peripheral bus after corresponding with the write address through identification. For a read data request, after the preset transport layer converts the request into the lower-level storage bus format and sends it out, it waits for the returned data and decrypts it, and then sends it to the TxDat for subsequent operations after converting it into the slave node format. Figure 9 The lower-level storage unit therein is the peripheral storage.

[0097] Among them, the formatting conversion module is used to convert the data packet into the CHI protocol or convert the CHI protocol into the peripheral storage communication protocol (lower-level storage bus protocol). The peripheral storage communication protocol includes AXI, USB, UART, IIC, etc. Taking the conversion between the CHI protocol and the AXI protocol as an example. For a read transaction, it receives the read request sent by the Req channel (request module channel), extracts the required information such as addr and converts it into an AR channel signal. After waiting for the R channel data returned by the AXI, it extracts the required information such as Data and ID and sends it to the TxDat module. For a write transaction, the RxDat module sends the addr, data, and other required information together. After extracting the required information, it is converted into AW and W channel signals and sent together. The conversion relationship is shown in Table 2 below:

[0098] Table 2

[0099]

[0100] Based on the above embodiments, as an implementable manner, in one embodiment, the cache coherence system includes:

[0101] An exception core register for recording the number of memory access request records of different processor cores in the request buffer and the waiting request duration of each processor core;

[0102] A slave node is used to determine that the request blocking degree of a processor core reaches a preset blocking threshold when the number of memory access request records of any processor core reaches a preset number threshold and the waiting request duration reaches a preset waiting duration threshold, and use the memory access request corresponding to the processor core in the request buffer as a priority response request.

[0103] It should be noted that in a multi-core processor environment, if the memory access requests of some processor cores are not processed for a long time, these cores will be in a waiting state, which will in turn affect the performance of the entire multi-core processor. By preferentially processing the requests of cores with a high degree of blockage, the core waiting time can be reduced, and the overall performance of the multi-core processor can be improved. Moreover, ensuring that the memory access requests of each processor core can be processed within a reasonable time can avoid system instability caused by long-term blockage of some cores.

[0104] Specifically, in one embodiment, the cache coherence system further includes:

[0105] A data status register for recording the memory access addresses of the memory access requests in the request buffer, and taking multiple memory access requests with the same memory access address and no data modification requirements as associated requests;

[0106] A slave node is used to obtain the associated data of the memory access address, send the associated data of the memory access address to the processor cores corresponding to each associated request, and send a sharing signal to the master node to prompt the master node that the associated data is shared data, so that the master node maintains the cache coherence state of the associated data in different processor cores.

[0107] Specifically, the data status register is responsible for monitoring the memory access addresses of the memory access requests in the request buffer. During the operation of the system, it continuously collects the address information of the memory access requests. When it is found that the addresses of multiple memory access requests are the same and these requests have no data modification requirements, they are classified as associated requests. This operation is mainly to identify those memory access requests that may involve shared data, and to prepare for subsequent optimization of data transmission and maintenance of cache coherence. After the data status register identifies the associated requests, the slave node obtains the associated data of the memory access addresses corresponding to these associated requests, and then sends this data to each processor core corresponding to the associated request. This can avoid repeatedly reading the same data from the storage device and reduce the memory access overhead. At the same time, the slave node also sends a sharing signal to the master node, informing the master node that these associated data are shared data. After receiving this signal, the master node maintains the cache coherence state of these associated data in different processor cores according to the cache coherence protocol, ensuring that the data obtained by each processor core is consistent.

[0108] Specifically, in one embodiment, the cache coherence system further includes:

[0109] A software configuration register for recording the page table base address information of the process to be terminated, and sending a clear signal to the slave node when obtaining the page table base address information of any process to be terminated;

[0110] The slave node is used to respond to the clear signal, determine the memory access requests to be cleared corresponding to the process to be terminated according to the page table base address information, and clear the memory access requests to be cleared in the request buffer or the preset transport layer.

[0111] Specifically, in the cache coherence system, the software configuration register and the slave node cooperate with each other to record the task of the page table base address information of the process to be terminated according to the user's process termination requirement. When the system decides to terminate a certain process, the page table base address information of the process is written into the software configuration register, and the software configuration register sends a clear signal to the slave node to inform the slave node that it needs to process the memory access requests of a specific process. Among them, the process page table base address information is the unique identification information of the process.

[0112] Specifically, after receiving the clear signal, the slave node searches and determines the memory access requests to be cleared corresponding to the process to be terminated in the request buffer or the preset transport layer. The process requests in the read operation or write operation pipeline of the slave node have been cleared in the preset transport layer.

[0113] Specifically, in one embodiment, the software configuration register is further used for:

[0114] Recording the running state information of the multi-core processor;

[0115] The slave node further includes:

[0116] A prefetch module, which is used to predict the to-be-accessed addresses stored in the peripheral according to the running state information of the multi-core processor to obtain a to-be-accessed address prediction result; generate a data prefetch request according to the to-be-accessed address prediction result, and send the data prefetch request to the request buffer.

[0117] Among them, the running state information of the multi-core processor includes the load conditions of each processor core, the types of tasks currently being executed by each core, the process switching frequency, etc.

[0118] Specifically, the prefetch module obtains the running status information recorded in the software configuration register, analyzes the current running trend of the processor using a specific algorithm or model, thereby predicting the addresses of the data to be accessed stored in the peripheral, and obtaining the prediction result of the addresses to be accessed. For example, if a certain core frequently accesses data in a specific area and it is judged according to the running status that the subsequent tasks of this core may still require relevant data, the prefetch module will predict that the data addresses near this area may be accessed. Based on the prediction result, the prefetch module generates data prefetch requests and sends these requests to the request buffer for subsequent processing. By predicting in advance the addresses of the data to be accessed stored in the peripheral and initiating prefetch requests, the data is pre-fetched into the cache before the processor actually needs the data. In this way, when the processor performs a memory access operation, it can directly obtain the data from the cache, reducing the time waiting for the data to be transferred from the peripheral storage, effectively reducing the memory access latency, and improving the data acquisition efficiency of the processor.

[0119] Specifically, in one embodiment, the software configuration register is further used to receive the atomic operation requests sent by the upper-level software; while sending the atomic operation requests to the slave node for response, it blocks all the memory access requests recorded in the request buffer, so that the slave node can continuously respond to the atomic operation requests.

[0120] Among them, an atomic operation refers to a set of indivisible operations that cannot be interrupted by other operations during execution to ensure the consistency and integrity of data.

[0121] Specifically, when the software configuration register receives an atomic operation request, it forwards the atomic operation request to the slave node so that the slave node can respond to and execute the request; and, to ensure the smooth execution of the atomic operation, the software configuration register blocks all the memory access requests recorded in the request buffer. During the execution of the atomic operation, other ordinary memory access requests cannot enter the processing flow temporarily, so that the slave node can focus on and continuously respond to the atomic operation requests, avoiding the atomic operation being interfered by other memory access requests.

[0122] Specifically, in one embodiment, the cache coherence system further includes: a process status register, which is connected to the page table base address register, senses the changes of the process by recording the page table base address, records the usage of the process therein, and sends the process identifier corresponding to the memory access read request to the prefetch module for classifying the memory access requests of the same process.

[0123] Specifically, in one embodiment, the prefetch module is used to verify the prefetch accuracy rate of the data prefetch requests before sending the data prefetch requests to the request buffer; in the case where the data prefetch requests pass the prefetch accuracy rate verification, the data prefetch requests are sent to the request buffer.

[0124] It should be noted that the prefetch accuracy verification is to evaluate the possibility that a prefetch request can obtain the data actually required by the processor in actual applications through specific methods or algorithms. Before passing the prefetch accuracy verification, the prefetch request is stored in the internal register of the prefetch module. Only when this probability reaches a certain standard, that is, when the data prefetch request passes the prefetch accuracy verification, will the prefetch module send the request to the request buffer for subsequent processing; if it fails the verification, it will not be sent to avoid invalid requests occupying system resources. The prefetch request sent after passing the prefetch accuracy verification has a higher possibility of obtaining the data actually required by the processor, making the prefetched data more likely to be used by the processor, thereby improving the cache hit rate. When the cache hit rate increases, the processor can obtain data from the cache faster, reducing the time to read data from the peripheral storage, and thus improving the overall system performance.

[0125] Specifically, in one embodiment, the prefetch module is used to determine the memory access stream characteristics of each currently running process according to the running state information of the multi-core processor; take any process as the process to be predicted, and determine the data prefetch request of the process to be predicted according to the memory access behavior pattern characterized by the memory access stream characteristics of the process to be predicted.

[0126] Specifically, during the operation of the multi-core processor, its running state information will change in real time, including the load conditions of each core, the type of instructions currently executed, the process switching frequency, etc. The prefetch module obtains this information as the basis for analyzing the memory access behavior of each process. Obtain memory access request information from the request module (Req), including the page table base address. According to the page table base address, the prefetch module records the memory access requests with the same page table base address (i.e., the same process) in the same table. Through the analysis of these records, the memory access stream characteristics of each process are extracted, such as the change rule of the memory access address, the time interval of memory access, etc. Take any process as the process to be predicted, and predict the addresses that the process may access subsequently according to the memory access behavior pattern characterized by the memory access stream characteristics of the process, so as to determine the data prefetch request. For example, if the memory access stream characteristics of a certain process show that it always accesses memory addresses in a certain step size order, then the prefetch module can predict the next possible memory access address according to this step size and use it as the target address of the data prefetch request. Send the simulated prefetch address to the peripheral storage and move it to the specified area for recording, and then test the prefetch accuracy by comparing the subsequent memory access instructions of the same process with the simulated prefetch address in the specified area. When the accuracy exceeds the threshold, the simulated prefetch address is determined as the real prefetch address. When the request module (Req) is idle, send the real prefetch address to it to initiate a prefetch request. When idle, the prefetch module multiplexes the existing module to fetch the prefetch data and stores it in the specified storage module (prefetch storage queue), so that these data can be directly fetched when the subsequent processor needs them, reducing the memory access latency.

[0127] Specifically, in one embodiment, the prefetch module is configured to monitor subsequent memory access requests of a process to be predicted after determining a data prefetch request of the process to be predicted; determine a prefetch accuracy rate of the data prefetch request according to a comparison result between an actual access address of the subsequent memory access request and a to-be-accessed address of the data prefetch request; and determine that the data prefetch request passes the prefetch accuracy rate verification when the prefetch accuracy rate of the data prefetch request reaches a preset accuracy rate threshold.

[0128] Specifically, since the accuracy of the prefetch request directly affects system performance and resource utilization efficiency, the prefetch module compares the address actually accessed by the subsequent memory access request with the to-be-accessed address in the previously determined data prefetch request after determining the data prefetch request of the process to be predicted. Through this comparison, it is possible to intuitively understand the matching degree between the prefetch address and the actual access address of the process, and then determine the prefetch accuracy rate of the data prefetch request. The prefetch accuracy rate reflects the prediction accuracy of the prefetch module. Only when the prefetch accuracy rate reaches the preset accuracy rate threshold, it is considered that the data prefetch request passes the prefetch accuracy rate verification.

[0129] Exemplarily, such as Figure 10As shown in the figure, it is a schematic diagram of the overall structure of the cache coherence system provided by the embodiment of the present application. The system includes a request buffer, a slave node functional area, a register bank, and a preset transport layer. The request buffer includes a prefetch storage queue, a request buffer queue, a receive data buffer queue, a send response buffer queue, and a send data buffer queue. The slave node functional area includes a prefetch module, a request module, a receive data module, a send response module, and a send data module. The register bank includes a software configuration register, a process status register, an exception core register, and an error register. The request module (Req) is responsible for receiving the instructions transmitted from the request buffer queue and performing corresponding parsing, and then transmitting the instructions and the corresponding information to the corresponding module; the receive data module (RxDat) is applicable in write transactions, and is used to receive write data packets and forward them to the preset transport layer, and forward them to the send response channel if necessary; the send response module (TxRsp) is used to return a response to the upper level, receive information from the request channel and the receive data channel and return the corresponding response; the send data module (TxDat) is used to return the read data response to the upper level during read transactions, and needs to store the data information obtained from the request channel and combine it with the data returned by AXI, and assemble it into a Data Flit and then return it; the prefetch module (Pre) is used to learn the access storage request addresses of the same process and reuse the Req module to issue corresponding prefetch requests, and store the retrieved data in the prefetch storage. The configuration register bank is used to connect the slave node to the bus of the lower-level storage module. Among them, the Enc_Dec module (encryption and decryption module) is used to encrypt and decrypt the data interacting with the storage. The BUS Master (bus master) integrates a variety of different bus protocol interfaces to meet compatibility, such as AXI, USB, UART, IIC, etc. The timeout counter is used to record the sending time of the memory access request. When any memory access request reports an error due to timeout, an exception reporting process is performed for the software.

[0130] The cache coherence system provided by the embodiments of the present application, where the requesting node is used to receive cache operation requests initiated by any processor core and send the cache operation requests to the master node; the master node is used to receive the cache operation requests and write corresponding memory access requests into the request buffer when determining that the cache operation requests belong to peripheral storage operation requests; the slave node is used to access the request buffer and sequentially respond to the access requests in the request buffer based on the cache coherence protocol. When any memory access request in the request buffer meets the preset priority response condition, the memory access request is used as the priority response request; where the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches a preset blocking threshold. In the system provided by the above solution, by monitoring the blocking situation of each memory access request in the request buffer by the slave node, when the request blocking degree of any processor core reaches the preset blocking threshold, the priority of the memory access request of the processor core is increased in the request buffer to avoid the situation that the slave node fails to respond to the memory access request of a certain processor core in a timely manner, thereby improving the overall performance of the system. Moreover, for the slave node provided by the embodiments of the present application, the addition of the request buffer improves the ability of the slave node to receive memory access requests, reduces the possibility of memory access requests being blocked here, and improves the processing ability. When a prefetch module is designed in the slave node and the memory access stream characteristics are learned in units of processes (page table base addresses), on the one hand, it is convenient to obtain the missing memory access addresses and obtain more accurate memory access stream characteristics, and on the other hand, prefetching the data that may be used in advance helps to reduce the memory access latency. Perceiving abnormal cores can avoid the situation that the memory access requests of some cores have not been processed for a long time, effectively improving the performance of the multi-core processor. Processing different channel signals in separate modules, using a pipeline design within the module, and adding registers to the modules that need to wait, effectively improving the ability of the slave node to concurrently process multiple requests and improving the overall performance of the system. Performing encryption and decryption operations before interacting with the memory to improve the security and reliability of the slave node. Setting a timeout counter, verifying the transmitted data through verification, and adding an error reporting mechanism to improve the reliability of the slave node. Setting a software configuration interface to enable software to guide hardware operations, combining the advantages of software and hardware to improve flexibility.

[0131] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0132] The embodiments of the present application provide a cache coherence method, which is applied to the slave node in the cache coherence system provided by the above embodiments.

[0133] As Figure 11 shown, it is a schematic flowchart of the cache coherence method provided by the embodiments of the present application. The method includes:

[0134] Step 1101: Obtain the memory access request sent by the master node by accessing the request buffer. Among them, when the master node determines that any cache operation request initiated by a processor core received belongs to a peripheral storage operation request, it writes the corresponding memory access request into the request buffer.

[0135] Step 1102: Respond to the access request in order based on the cache coherence protocol.

[0136] Step 1103: When any memory access request in the request buffer meets the preset priority response condition, use this memory access request as the priority response request.

[0137] Step 1104: Prioritize responding to the priority response request.

[0138] Among them, the preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches the preset blocking threshold.

[0139] For the description of the features in the embodiments corresponding to the cache coherence method, reference can be made to the relevant descriptions of the embodiments corresponding to the cache coherence system, which will not be elaborated here one by one.

[0140] The embodiment of the present application provides a cache coherence device for deploying the cache coherence system provided in the above embodiment.

[0141] As Figure 12 shown, it is a schematic structural diagram of the cache coherence device provided by the embodiment of the present application. The cache coherence device includes: a multi-core processor and the cache coherence system provided in the above embodiment.

[0142] Each processor core in the multi-core processor corresponds one-to-one with the request nodes in the cache coherence system.

[0143] For the description of the features in the embodiments corresponding to the cache coherence device, reference can be made to the relevant descriptions of the embodiments corresponding to the cache coherence system, which will not be elaborated here one by one.

[0144] The embodiment of the present application also provides an electronic device. As Figure 13 shown, it is a schematic structural diagram of the electronic device provided by the embodiment of the present application, including a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above cache coherence method embodiments.

[0145] The embodiment of the present application also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium, and the computer program is configured to execute the steps in any of the above cache coherence method embodiments when running.

[0146] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media that can store computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs.

[0147] The embodiment of the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the cache coherence method.

[0148] The embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the cache coherence method.

[0149] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0150] The above has introduced in detail a cache coherence system, method, device, electronic device, and storage medium provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A cache consistency system, characterized in that: include: A request node, a master node and a slave node, wherein a request buffer is provided between the master node and the slave node; The requesting node is used to receive a cache operation request initiated by any processor core, and send the cache operation request to the master node; The master node is used to receive the cache operation request, and write a corresponding memory access request in the request buffer when determining that the cache operation request belongs to a peripheral storage operation request; The slave node is used to access the request buffer and respond to the access requests in the request buffer in order based on the cache consistency protocol, and when any of the memory access requests in the request buffer meets the preset priority response condition, the memory access request is used as a priority response request; The preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches a preset blocking threshold.

2. The cache consistency system according to claim 1, characterized in that: The master node is used to: When receiving a cache operation request sent by any requesting node, obtaining the current status information of the master node cache; According to the current state information of the master node cache and the operation requirement information of the cache operation request, it is determined whether the cache operation request belongs to an external storage operation request.

3. The cache consistency system according to claim 2, characterized in that: The master node is also used for: When it is determined that the cache operation request does not belong to a peripheral storage operation request, the cache operation request is responded to based on the master node cache in accordance with the cache consistency protocol, and the response result is returned to the corresponding requesting node.

4. The cache consistency system according to claim 1, characterized in that: The slave node comprises: a request module, configured to access the request buffer, extract the memory access request to be responded to in the request buffer, parse the access request to obtain request parsing information, and send the request parsing information to the data sending module when the request parsing information indicates that the memory access request is a read request, and send the request parsing information to the data receiving module when the request parsing information indicates that the memory access request is a write request; The data sending module is used to execute the read operation represented by the memory access request according to the obtained parsing information; The data receiving module is used to execute the write operation represented by the memory access request according to the obtained parsed information.

5. The cache consistency system according to claim 4, characterized in that: The slave node further includes: a response sending module, configured to receive a response instruction sent by the request module or the data receiving module, and generate a corresponding response packet in response to the response instruction, and write the response packet into the request buffer so as to feed back to the master node through the request buffer; Among them, the request module is used to send the response instruction to the sending response module when it is determined that the sending data module completes the read operation; the receiving data module is used to send the response instruction to the sending response module when the parsing information corresponding to the write operation is obtained.

6. The cache consistency system according to claim 4, characterized in that: The data sending module is used to: Determine target read data and a target reading number corresponding to the target read data according to the obtained parsed data; The target read data is read from the peripheral storage through a preset transport layer, and when the number of reads reaches the target number of reads, the read target read data is packaged to obtain a target read data packet; Determining a target buffer queue of the target read data packet according to a memory access type corresponding to the target read data packet; After adding a check bit to the target read data packet, writing the target read data packet into the target buffer queue; The memory access type is at least divided into a common type and a pre-fetch type, the request buffer includes a plurality of buffer queues, and the buffer queues are at least divided into a data transmission buffer queue and a pre-fetch storage queue.

7. The cache consistency system according to claim 4, characterized in that: The data receiving module is used for: According to the obtained parsed data, the target write data packet is obtained; Checking the check bit of the target write data packet; When the target write data packet passes the check bit check, comparing the data identifier of the target write data packet with the request identifier of the access request represented by the parsing information; In the case where it is determined that the data identifier and the request identifier match, extracting target write address information from the parsed data; Packing the target write data packet and the target write address information to obtain a target write operation packet, and sending the target write operation packet to a preset transmission layer; Based on the preset transmission layer, the target write operation packet is converted into a target write data channel signal, so as to write the target write data packet into the target write address through the write data channel.

8. The cache coherence system according to claim 7, characterized in that: The data receiving module is further used for: If the target write data packet fails to pass the check bit check, submitting a verification failure signal to an error register so that the master node re-uploads the target write data packet; Wherein, the cache consistency system includes the error register.

9. The cache coherence system according to claim 7, characterized in that: The cache consistency system further includes: The preset transport layer is used to encrypt the target write operation packet before converting the target write operation packet into a target write data channel signal.

10. The cache coherence system according to claim 1, characterized in that: The cache consistency system comprises: An abnormal core register, used to record the number of memory access request records from different processor cores in the request buffer and the waiting request duration of each processor core; The slave node is used to determine that the request blocking degree of any processor core reaches a preset blocking threshold when the number of memory access request records of any processor core reaches a preset number threshold and the waiting request time reaches a preset waiting time threshold, and treat the memory access request corresponding to the processor core in the request buffer as a priority response request.

11. The cache coherence system according to claim 1, characterized in that: The cache consistency system further includes: A data status register, used to record the memory access addresses of the memory access requests in the request buffer, and to treat multiple memory access requests with the same memory access addresses and no data modification requirements as associated requests; The slave node is used to obtain the associated data of the memory access address, send the associated data of the memory access address to the processor core corresponding to each of the associated requests, and send a sharing signal to the master node to prompt the master node that the associated data is shared data, so that the master node maintains the cache consistency status of the associated data in different processor cores.

12. The cache coherence system according to claim 1, characterized in that: The cache consistency system further includes: A software configuration register, used for recording the page table base address information of the process to be terminated, and sending a clear signal to the slave node when the page table base address information of any process to be terminated is obtained; The slave node is used to respond to the clear signal, determine the memory access request to be cleared corresponding to the process to be terminated according to the page table base address information, and clear the memory access request to be cleared in the request buffer or the preset transmission layer.

13. The cache coherence system according to claim 12, characterized in that: The software configuration register is also used for: Record the operating status information of the multi-core processor; The slave node further includes: The prefetch module is used to predict the address to be accessed stored in the peripheral device according to the operation status information of the multi-core processor, and obtain the prediction result of the address to be accessed; generate a data prefetch request according to the prediction result of the address to be accessed, and send the data prefetch request to the request buffer.

14. The cache coherence system according to claim 12, characterized in that: The software configuration register is also used for: Receive atomic operation requests from superior software; While sending the atomic operation request to the slave node for response, all memory access requests recorded in the request buffer are blocked so that the slave node can respond to the atomic operation request uninterruptedly.

15. The cache coherence system according to claim 13, characterized in that: The pre-fetch module is used for: Before sending the data pre-fetch request to the request buffer, verifying the pre-fetch accuracy of the data pre-fetch request; In a case where the data pre-fetch request passes the pre-fetch accuracy verification, the data pre-fetch request is sent to the request buffer.

16. The cache coherence system according to claim 15, characterized in that: The pre-fetch module is used for: Determining memory access flow characteristics of each currently running process according to the running state information of the multi-core processor; Any of the processes is taken as a process to be predicted, and a data prefetch request of the process to be predicted is determined according to a memory access behavior pattern represented by a memory access flow feature of the process to be predicted.

17. The cache coherence system according to claim 16, characterized in that: The pre-fetch module is used for: After determining the data prefetch request of the process to be predicted, monitoring subsequent memory access requests of the process to be predicted; Determining the prefetch accuracy of the data prefetch request according to a comparison result between the actual access address of the subsequent memory access request and the to-be-accessed address of the data prefetch request; When the prefetch accuracy of the data prefetch request reaches a preset accuracy threshold, it is determined that the data prefetch request passes the prefetch accuracy verification.

18. A cache consistency method, characterized in that: Applied to a slave node in a cache coherence system according to any one of claims 1 to 17, the method comprising: Obtaining a memory access request issued by the master node by accessing the request buffer; wherein, when the master node determines that the cache operation request initiated by any processor core received belongs to a peripheral storage operation request, the master node writes the corresponding memory access request into the request buffer; Responding to the access request in order based on a cache coherence protocol; When any of the memory access requests in the request buffer satisfies a preset priority response condition, the memory access request is used as a priority response request; giving priority response to the priority response request; The preset priority response condition includes that the request blocking degree of the processor core corresponding to the memory access request reaches a preset blocking threshold.

19. A cache consistency device, characterized in that: include: A multi-core processor and a cache coherence system as claimed in any one of claims 1 to 17; Each processor core in the multi-core processor corresponds one-to-one to a request node in the cache coherence system.

20. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the cache consistency method as claimed in claim 18 when executing the computer program.

21. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the cache consistency method as claimed in claim 18 when executed by a processor.

22. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the cache consistency method according to claim 18 are implemented.

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