Dynamic self-adaptive interrupt processing method and interrupt processing system

Abstract

The invention provides a dynamic self-adaptive interrupt processing method and system, and the method comprises the steps: collecting a plurality of working state parameters of each peripheral module in a processor in real time, and evaluating the interrupt priority of each interrupt based on a priority evaluation model; according to the historical triggering times of each interrupt, predicting the triggering times of each interrupt in a future time period based on a prediction algorithm; determining an interrupt scheduling strategy according to the interrupt priority of each interrupt and the triggering times in the future time period; and regularly evaluating the efficiency of the interrupt scheduling strategy, and adjusting parameters of the priority evaluation model and the prediction algorithm according to an evaluation result so as to adjust the interrupt scheduling strategy. According to the method and the device, the priority of each interrupt can be adjusted in real time according to the working state parameters of the peripheral module, the corresponding interrupt scheduling strategy is given, and the method and the device are suitable for scenes with limited performance under the conditions of MCU resource shortage, high real-time performance requirement and high power consumption requirement.

Description

Technical Field

[0001] The present invention relates to the field of interrupt handling, and more particularly, to a dynamic adaptive interrupt handling method and an interrupt handling system. Background Art

[0002] As the core component of an embedded system, a processor is widely used in real-time control and data processing scenarios. In processor driver development, interrupt handling is a key technology to ensure the real-time performance and efficiency of the system.

[0003] Traditional interrupt handling mechanisms usually adopt fixed priority, static scheduling strategies or round-robin priority methods. For example, fixed interrupt priorities are set through a nested vector interrupt controller (NVIC).

[0004] Traditional interrupt handling mechanisms have the following defects: 1. Interrupt conflicts: In high-load situations, multiple peripheral modules (such as UART, SPI, I2C, etc.) trigger interrupts simultaneously. The fixed priority mechanism may cause low-priority interrupts to be blocked for a long time, affecting the real-time performance of the system. Although the round-robin priority mechanism does not cause low-priority interrupts to be blocked for a long time, there is a problem that high-priority interrupts cannot be executed in a timely manner, and there are also real-time performance problems in the system.

[0005] 2. Resource waste: Traditional methods do not consider the dynamic characteristics of interrupt handling. For example, some interrupts may be inactive during a specific period but still occupy system resources.

[0006] 3. Development complexity: Driver development engineers need to manually adjust interrupt priorities and scheduling strategies, increasing the development and maintenance costs.

[0007] 4. Power consumption issues: In low-power application scenarios, frequent interrupt handling may lead to unnecessary power consumption overhead.

[0008] Therefore, traditional interrupt handling mechanisms cannot well meet the requirements in application scenarios with high real-time requirements, limited CPU resources, and high power consumption requirements. Summary of the Invention

[0009] The present invention provides a dynamic adaptive interrupt handling method and an interrupt handling system for the technical problems existing in the prior art, and overcomes the problem that the requirements cannot be well met in application scenarios with high real-time requirements, limited CPU resources, and high power consumption requirements.

[0010] According to a first aspect of the present invention, there is provided a dynamic adaptive interrupt handling method, including: Collect multiple working state parameters of each peripheral module in the real-time acquisition processor, where the multiple working state parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirements. Each peripheral module triggers one or more interrupts; Based on the interrupt trigger frequency, the data throughput, the active time, and the task real-time requirements of each interrupt, evaluate the interrupt priority of each interrupt based on a priority evaluation model; Based on the number of trigger times of each interrupt in the historical time period, predict the number of trigger times of each interrupt in the future time period based on a prediction algorithm; Based on the interrupt priority and the number of trigger times in the future time period of each interrupt, determine the interrupt scheduling strategy of each interrupt; Process each interrupt according to the interrupt scheduling strategy; Regularly evaluate the efficiency of the interrupt processing strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

[0011] According to the second aspect of the present invention, there is provided a dynamic adaptive interrupt processing system, including a dynamic monitoring module, a priority evaluation module, an interrupt prediction module, an interrupt scheduling module, and an interrupt optimization module; The dynamic monitoring module is configured to collect multiple working state parameters of each peripheral module in the processor in real time. The multiple working state parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirements. Each peripheral module triggers one or more interrupts; The priority evaluation module is configured to evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the task real-time requirements of each interrupt; The interrupt prediction module is configured to predict the number of trigger times of each interrupt in the future time period based on a prediction algorithm according to the number of trigger times of each interrupt in the historical time period; The interrupt scheduling module is configured to determine the interrupt scheduling strategy of each interrupt based on the interrupt priority and the number of trigger times in the future time period of each interrupt, and process each interrupt according to the interrupt scheduling strategy; The interrupt optimization module is configured to regularly evaluate the efficiency of the interrupt processing strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

[0012] A dynamic adaptive interrupt handling method and an interrupt handling system provided by the present invention collect multiple working state parameters of each peripheral module in a processor in real time; based on the multiple working state parameters, evaluate the interrupt priority of each interrupt based on a priority evaluation model; based on the historical trigger times of each interrupt, predict the trigger times of each interrupt within a future time period based on a prediction algorithm; determine the interrupt scheduling strategy of each interrupt according to the interrupt priority and the trigger times within the future time period of each interrupt; accelerate the time consumed by interrupt execution through context caching and tail chain technology; during the inactive period of the interrupt, dynamically adjust the power state of the corresponding module to reduce power consumption; regularly evaluate the efficiency of the interrupt scheduling strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy. Through the present invention, the priority of each interrupt can be evaluated in real time according to the working state parameters of the peripheral module, the priorities of each interrupt can be dynamically adjusted, and the corresponding interrupt scheduling strategy can be given, which is applicable to the scenarios with limited performance under the conditions of tight MCU resources, high real-time requirements, and high power consumption requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a flowchart of a dynamic adaptive interrupt handling method provided by an embodiment of the present invention; Figure 2 It is an overall flowchart of a dynamic adaptive interrupt handling method according to an embodiment of the present invention; Figure 3 It is a flowchart for calculating the priority score of an interrupt according to an embodiment of the present invention; Figure 4 It is a flowchart for predicting the future trigger times of an interrupt according to an embodiment of the present invention; Figure 5 It is a structural block diagram of a dynamic adaptive interrupt handling system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. In addition, the technical features in each embodiment or a single embodiment provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. Such combination is not restricted by the order of steps and / or the pattern of structural composition, but must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0015] Figure 1 The following is a flowchart of a dynamic adaptive interrupt handling method provided by the present invention. As Figure 1 and Figure 2 shown, the dynamic adaptive interrupt handling method includes: Step 1: Real-time collect multiple working state parameters of each peripheral module in the processor. The multiple working state parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirement. Among them, each peripheral module triggers one or more interrupts.

[0016] It can be understood that the processor (Soc chip) includes multiple peripheral modules, and each peripheral module may trigger one interrupt or multiple interrupts. When a large number of interrupts are triggered simultaneously by the various peripheral modules of the processor, there will be a problem of processing congestion. Therefore, it is necessary to configure an interrupt scheduling strategy to process a large number of interrupts in an orderly manner.

[0017] First, obtain the working state parameters of each peripheral module. The working state parameters include interrupt trigger frequency, data throughput, module active time, module power consumption state, and task real-time requirement.

[0018] Among them, use a hardware counter (such as the hardware timer in the processor) to count the interrupt trigger frequency of each module (such as UART), and record it as Freq_module (times / second); Use the DMA controller to count the data throughput of each module (such as SPI), and record it as Trans_module (bytes / second); Use the PMU (Power Management Unit) to count the power consumption of each module, and record it as Power_module (milliwatts).

[0019] Step 2: Based on the interrupt trigger frequency, data throughput, active time, and task real-time requirement of each interrupt, evaluate the interrupt priority of each interrupt based on the priority evaluation model.

[0020] It can be understood that in Step 1, the interrupt-related parameters of each peripheral module are obtained. In this step, based on these parameters, the priority of each interrupt is evaluated, and a priority mapping table of interrupts is generated. In the embodiment of the present invention, the weighted scoring method is used to evaluate the priority of each interrupt based on the priority evaluation model. Multidimensional data (Freq_norm, Trans_norm, Active_norm, Real_norm) is input into the priority evaluation model, and the output is the priority score S_priority. The weight coefficients of the priority evaluation model are updated regularly to adapt to different application scenarios. For example, in the industrial control field, the weight of the real-time requirement Real_norm can be increased (w4 = 0.4).

[0021] Specifically, refer to Figure 3 , the priority evaluation model constructs an interrupt priority evaluation model according to the relevant parameters of each collected interrupt, and calculates the priority score S_priority of each interrupt source. The formula is as follows: S_priority = w1 * Freq_norm + w2 * Trans_norm + w3 * Active_norm + w4 * Real_norm; where: Freq_norm, Trans_norm, and Active_norm are the interrupt trigger frequency, data throughput, and active time after normalization (mapping the data to [0, 1]); Real_norm is the normalized value of the task real-time requirement, which is provided by the RTOS task priority or the user; w1, w2, w3, and w4 are weight coefficients, which can be dynamically adjusted by the policy optimization module, and the default values are 0.3, 0.3, 0.2, and 0.2.

[0022] Determine the interrupt priority of each interrupt according to the priority score of each interrupt, and generate an interrupt priority mapping table; among them, the priorities of all interrupts are sorted according to the size of the priority score. The interrupt with a large priority score has a high priority, and the interrupt with a small priority score has a low priority.

[0023] Step 3: Based on the trigger times of each interrupt in the historical time period, predict the trigger times of each interrupt in the future time period based on the prediction algorithm.

[0024] In an embodiment of the present invention, predicting the trigger times of each interrupt in the future time period based on the trigger times of each interrupt in the historical time period includes: Obtain the trigger time series {t1, t2, …, t n} of interruptions within a historical time period, and convert the trigger time series into the number of interruptions triggered within a time window, where t1, t2, …, t n represent the moments when interruptions are triggered within the historical time period, and n is the moment index; Count the number of interruptions triggered within each time window, and generate the interruption trigger sequence {X1, X2, …, X m} within the historical time period, where X1, X2, …, X m represent the number of interruptions triggered within each time window; Based on the interruption trigger sequence {X1, X2, …, X m} within the historical time period, predict the number of interruptions triggered by each interruption within the next time window based on a prediction algorithm, where m is the number of time windows included in the historical time period.

[0025] Specifically, refer to Figure 4 , and predict the number of interruptions triggered within the next 10 ms based on a time series analysis algorithm (such as exponential smoothing method or ARIMA model). For example, for the UART module, input the interruption trigger time series {t1, t2, …, t n} of the past 50 ms, and the steps for outputting the number of interruptions triggered within the next 10 ms, St, are as follows: 1. {t1, t2, …, t n} is the time stamp of the interruption trigger, and convert it into the number of interruptions within a time window.

[0026] 2. Assume that the time window is 1 ms (50 ms is divided into 50 1-ms windows), count the number of interruptions within each time window, and generate the sequence {X1, X2, …, X 50}.

[0027] If t1 = 2.3 ms, t2 = 2.7 ms, t3 = 5.1 ms, then: In the 2-ms time window: 2 interruptions (2.3 ms and 2.7 ms), in the 5-ms time window: 1 interruption (5.1 ms), and in other time windows: 0 interruptions. Count the total number of interruptions within 50 ms, and generate the sequence {X1, X2, …, X 50} of the number of interruptions triggered in each time window.

[0028] 3. Predict the future number of interrupt triggers using the exponential smoothing method: $S_t = \alpha*X_t+(1-\alpha)*S_{t-1}$, where $S_t$ is the smoothed value, estimating the number of interrupt triggers within the next 1 ms time window; $X_t$ is the number of interrupt triggers in the current 1 ms window; $S_{t-1}$ is the average number of interrupt triggers within the historical 50 ms time window (total number of interrupts within 50 ms / 50). The calculated $S_t$ is the number of interrupt triggers within the next 1 ms time window, and the number of interrupt triggers within the next 10 ms is $10*S_t$ (10 1 ms time windows).

[0029] Step 4. Determine the interrupt scheduling strategy for each interrupt according to the interrupt priority of each interrupt and the number of triggers within the future time period.

[0030] It can be understood that the scheduling strategy for each interrupt is determined according to the priority of each interrupt and the trigger probability within a future period of time. Among them, the interrupt scheduling strategy includes interrupt masking, interrupt merging, and interrupt delay processing. Specifically, if the number of triggers $S_t$ of a certain interrupt source (such as I2C) is lower than the threshold, the interrupt is temporarily masked by the interrupt controller; if multiple low-priority interrupts (such as GPIO and timer interrupts) are triggered frequently within a short period of time, they are merged into a batch processing interrupt through software; for non-real-time interrupts (such as log recording interrupts), they are delayed through the delay queue mechanism.

[0031] Step 5. Process the interrupts according to the interrupt scheduling strategy.

[0032] It is understandable that after determining the scheduling policy for each interrupt, the interrupt is processed. During the process of processing the interrupt, context switching will be involved. In the embodiment of the present invention, during the interrupt processing, an adaptive context switching technology is adopted. Through interrupt context caching and interrupt nesting optimization (tail chain technology), the overhead of unnecessary interrupt context (register state of the current task) switching is reduced. In the traditional method, each time an interrupt is triggered, a complete context save and restore are required (about 50 instruction cycles), which includes saving the register state of the current task (program counter PC, general-purpose registers, status register, etc.) to the stack area before interrupt processing, and after the interrupt processing is completed, reloading the saved register state into the registers to resume the execution of the original task. In S4, through the tail chain technology and fast context caching, the context switching overhead is reduced to about 20 instruction cycles. Among them, the fast context caching uses a hardware mechanism (hardware stack frame) to quickly store the register state into the stack and restore it from the stack to the registers. The tail chain technology means that after an interrupt processing is completed, the processor rechecks whether there is a pending interrupt in the interrupt controller (such as NVIC). If so, the processor directly jumps to the new interrupt entry without restoring the context of the current interrupt, nor immediately saving the complete context of the new interrupt, but restoring the context after all pending interrupts are processed.

[0033] According to the predicted future triggering trend of the interrupt, the power state of the peripheral module is dynamically adjusted during the inactive period of the interrupt. For example, if it is predicted that there will be no interrupt trigger in the SPI module within the next 50 ms, the SPI module is placed in the low-power mode (turn off the clock or reduce the voltage) through the PMU (power management module) to reduce the power consumption of the entire system.

[0034] Step 6, regularly evaluate the efficiency of the interrupt processing policy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling policy.

[0035] It is understandable that after processing the interrupt according to the interrupt scheduling policy, the efficiency of the interrupt processing policy is evaluated, the parameters of the priority evaluation model and the prediction algorithm are adjusted according to the evaluation results, the priority evaluation of the interrupt and the prediction of the triggering trend are adjusted, and then the interrupt scheduling policy is adjusted.

[0036] Among them, the evaluation of the interrupt processing efficiency mainly includes evaluating the real-time index, power consumption index and performance index of the interrupt processing. Among them: Real-time index: Interrupt latency time D_latency (milliseconds), and the standard is D_latency < 1 ms; Power consumption index: Average power consumption P_avg (milliwatts), and the standard is that P_avg is reduced by 30%; Performance indicators: CPU occupancy rate C_usage (in percentage), with the standard being a 20% reduction in C_usage.

[0037] According to the evaluation results of each indicator of the interrupt handling strategy, adjust the weight coefficients {w1, w2, w3, w4} of the priority evaluation model and the smoothing factor α of the prediction algorithm to achieve dynamic evaluation of interrupt priorities and dynamic prediction of trigger trends, and then dynamically adjust the interrupt scheduling strategy.

[0038] See Figure 5 , a dynamic adaptive interrupt handling system provided by the present invention, characterized in that it includes a dynamic monitoring module 301, a priority evaluation module 302, an interrupt prediction module 303, an interrupt scheduling module 304, and a policy optimization module 305.

[0039] The dynamic monitoring module 301 is used to collect multiple working state parameters of each peripheral module in the processor in real time. The multiple working state parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirements. Among them, each peripheral module triggers one or more interrupts; The priority evaluation module 302 is used to evaluate the interrupt priority of each interrupt based on the priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the task real-time requirements of each interrupt; The interrupt prediction module 303 is used to predict the number of trigger times of each interrupt in a future time period based on the prediction algorithm according to the number of trigger times of each interrupt in a historical time period; The interrupt scheduling module 304 is used to determine the interrupt scheduling strategy of each interrupt according to the interrupt priority and the number of trigger times of each interrupt in the future time period, and process the interrupt according to the interrupt scheduling strategy; The policy optimization module 305 is used to regularly evaluate the efficiency of the interrupt handling strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

[0040] Among them, see Figure 5 , the dynamic adaptive interrupt handling system provided by the embodiment of the present invention further includes a context switching module 306 and a low-power management module 307, where: The context switching module 306 is used to switch the context based on context caching and interrupt nesting optimization during the interrupt handling process; The low-power management module 307 is used to dynamically adjust the power state of the peripheral module during the inactive period of the interrupt according to the predicted number of trigger times of each interrupt in the future time period, and place the peripheral module in the low-power mode.

[0041] It can be understood that a dynamic adaptive interrupt processing system provided by the present invention corresponds to the dynamic adaptive interrupt processing methods provided in the foregoing embodiments. For the related technical features of the dynamic adaptive interrupt processing system, reference can be made to the related technical features of the dynamic adaptive interrupt processing methods, which will not be elaborated herein.

[0042] A dynamic adaptive interrupt processing method and system provided by an embodiment of the present invention solve the problem of limited performance of the traditional interrupt processing mechanism in scenarios with tight MCU resources, high real-time requirements, and high power consumption requirements through an interrupt prediction algorithm (exponential smoothing method), a priority evaluation method, and a fast context switching processing method, and have the following advantages: 1) Dynamic adaptive interrupt processing: According to the interrupt prediction algorithm, dynamically adjust resource allocation, such as interrupt masking, interrupt merging, and interrupt delay, to avoid waste of CPU resources under static configuration of interrupts.

[0043] 2) High performance: Optimize for interrupt context switching to improve CPU processing efficiency. For example, for nested interrupts, use the tail chain technology of ARM to avoid repeated context switching; for high-frequency interrupts, speed up interrupt processing efficiency by embedding assembly language in the ISR; use the SF pointer to quickly save and restore register states.

[0044] 3) Low power consumption: According to the interrupt prediction algorithm, place the modules in which interrupts are in an inactive period for a period of time in the future in a low-power state to reduce energy consumption.

[0045] 4) Easy to implement: The interrupt prediction algorithm uses a lightweight algorithm, which is suitable for the MCU environment with limited resources.

[0046] 5) Feedback mechanism: The policy optimization module monitors and optimizes the prediction algorithm parameters in real time to enhance the robustness of the system.

[0047] 6) High interrupt prediction accuracy: Use normalized processing for the parameters required by the interrupt prediction algorithm to improve the prediction accuracy.

[0048] It should be noted that in the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0049] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] The present invention will be described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices produce means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0051] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or multiple blocks.

[0053] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0054] Obviously, those skilled in the art can make various changes and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and variations.

Claims

1. A dynamic adaptive interrupt processing method, characterized in that: include: Real-time acquisition of multiple working status parameters of each peripheral module in the processor, wherein the multiple working status parameters include interrupt trigger frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts; According to the interrupt triggering frequency, the data throughput, the active time and the task real-time requirement of each interrupt, the interrupt priority of each interrupt is evaluated based on the priority evaluation model; According to the number of times each interruption is triggered in the historical time period, the number of times each interruption is triggered in the future time period is predicted based on the prediction algorithm; Determine the interrupt scheduling strategy for each interrupt based on the interrupt priority of each interrupt and the number of triggers in the future time period; Processing each interrupt according to the interrupt scheduling strategy; The efficiency of the interrupt handling strategy is evaluated regularly, and the parameters of the priority evaluation model and the prediction algorithm are adjusted according to the evaluation results to adjust the interrupt scheduling strategy.

2. The method for dynamically adaptive interrupt processing according to claim 1, characterized in that: The real-time acquisition processor collects multiple working status parameters of each peripheral module, including: Use the hardware counter to count the interrupt trigger frequency of each peripheral module in the processor and record it as Freq_module; Use the DMA controller to count the data throughput of each interrupt of each peripheral module in the processor, recorded as Trans_module; Determine the real-time requirements of the task based on the task type and record it as Real_module.

3. The dynamic adaptive interrupt processing method according to claim 1, characterized in that: The step of evaluating the interrupt priority of each interrupt based on the priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement of each interrupt includes: Calculate the priority score of each interrupt based on the priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement of each interrupt; The interrupt priority of each interrupt is determined according to the priority score of each interrupt, and an interrupt priority mapping table is generated; wherein the priorities of all interrupts are sorted according to the priority scores, the interrupts with large priority scores have large priorities, and the interrupts with small priority scores have small priorities.

4. The method for dynamically adaptive interrupt processing according to claim 3, characterized in that: The calculating the priority score of each interrupt based on the priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement of each interrupt includes: S_priority=w1*Freq_norm+w2*Trans_norm+w3*Active_norm+w4*Real_norm; Wherein: Freq_norm, Trans_norm, Active_norm are respectively the normalized interrupt trigger frequency, data throughput, active time and task real-time requirement, S_priority is the priority score of the interrupt, w1, w2, w3 and w4 are respectively the weight coefficients of the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement.

5. The method for dynamically adaptive interrupt processing according to claim 1, characterized in that: According to the number of times each interruption is triggered in the historical time period, the number of times each interruption is triggered in the future time period is predicted based on the prediction algorithm, including: Get the trigger time sequence {t1, t2, ..., t n }, convert the trigger time series into the number of interrupt triggers within the time window, where t1, t2, ..., t n Indicates the time when the interrupt is triggered in the historical time period, and n is the time index; Count the number of interrupt triggers in each time window and generate the interrupt trigger sequence {X1, X2, ..., X m }, where X1, X2, …, X m It indicates the number of interrupt triggers in each time window, and m is the number of time windows in the historical time period; According to the interrupt trigger sequence {X1, X2, ..., X m }, based on the prediction algorithm, predict the number of times each interrupt will be triggered within a future time window.

6. The method for dynamically adaptive interrupt processing according to claim 5, characterized in that: The interrupt trigger sequence {X1, X2, ..., X m }, based on the prediction algorithm, predict the number of times each interrupt will be triggered in a future time window, including: S_t = α*X_t+(1-α)*S_(t-1); Among them, S_t is the predicted number of times each interrupt will be triggered in a future time window; X_t is the number of interrupt triggers in the current time window, S_(t-1) is the average number of interrupt triggers in all time windows in the historical time period, and α is the smoothing factor.

7. The method for dynamically adaptive interrupt processing according to claim 1, characterized in that: Determining the interrupt scheduling strategy for each interrupt according to the interrupt priority of each interrupt and the number of triggers in a future time period includes: If the number of times the interrupt is triggered in the future time period is lower than a preset threshold, the interrupt is temporarily shielded by the interrupt controller; If multiple low-priority interrupts are triggered frequently within a short period of time, multiple interrupts are merged into one batch processing interrupt through software; For non-real-time interrupts, the interrupts are delayed by a delay queue mechanism; According to the predicted triggering times of each interrupt in a future time period, the power state of the peripheral module is dynamically adjusted during the inactive period of the interrupt, and the peripheral module is placed in a low power consumption mode.

8. The method for dynamically adaptive interrupt processing according to claim 6, characterized in that: Regularly evaluating the efficiency of the interrupt handling strategy, and adjusting the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results, including: After processing the interrupt according to the interrupt scheduling strategy, the interrupt delay time, average power consumption and CPU occupancy rate of each interrupt are obtained; The efficiency of the interrupt handling strategy is evaluated based on the interrupt delay time of each interrupt, the average power consumption of the processor and the CPU occupancy rate to obtain an evaluation result; The weight coefficients w1, w2, w3 and w4 in the priority evaluation model and the smoothing factor α of the prediction algorithm are adjusted according to the evaluation result.

9. The method for dynamically adaptive interrupt processing according to claim 1, characterized in that: Also includes: During interrupt processing, context switching is performed based on context caching and interrupt nesting optimization.

10. A dynamic adaptive interrupt processing system, characterized in that: Including dynamic monitoring module, priority assessment module, interruption prediction module, interruption scheduling module, and interruption optimization module; The dynamic monitoring module is used to collect multiple working status parameters of each peripheral module in the processor in real time, wherein the multiple working status parameters include interrupt triggering frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts; The priority evaluation module is used to evaluate the interrupt priority of each interrupt based on the priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement of each interrupt; An interrupt prediction module is used to predict the number of times each interrupt is triggered in a future time period based on a prediction algorithm according to the number of times each interrupt is triggered in a historical time period; An interrupt scheduling module, used to determine an interrupt scheduling strategy for each interrupt according to the interrupt priority of each interrupt and the number of triggers in a future time period, and to process each interrupt according to the interrupt scheduling strategy; The interrupt optimization module is used to regularly evaluate the efficiency of the interrupt processing strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

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