Multi-chip parallel current rising process modeling method and system based on loop inductor

Abstract

The invention discloses a loop inductance-based multi-chip parallel current rising process modeling method and system, and the method comprises the steps: writing a current rising process equation through a loop inductance method of a multi-chip parallel double-pulse test circuit, and accurately describing the current rising behavior in the multi-chip parallel double-pulse test circuit. By calculating the terminal voltage of each chip, the method can determine a key factor for achieving a complete current sharing condition, in a parallel circuit, current sharing is the key for ensuring that all components uniformly share loads and avoid overheating and damage, and the established simulation circuit model is based on an actual current rising process equation and the current sharing condition. And the behavior of an actual circuit can be accurately reflected. Based on circuit topology described by a graph theory, Kelvin sources, non-Kelvin sources and other connection modes are unified, most (all) electromagnetic induction effects are described with least inductance parameters, a simple and effective equation is obtained, and analysis and expansion are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor applications, and in particular, to a method and system for modeling the current rising process of multi-chip parallel connection. Background Art

[0002] Power semiconductor chips are the core of power electronic energy conversion and are widely used in the fields of electric vehicle drives, charging piles, solid-state transformers, and ship power systems. However, the current-carrying capacity of a single chip is limited. In some high-power applications, chip parallel connection is required. When power semiconductor chips perform power conversion, they continuously switch. During this process, the currents flowing through different chips will be inconsistent. The faster the switching speed, the more obvious the current inconsistency, resulting in different heats generated between the chips, leading to uneven temperatures and reducing the utilization rate of the chips.

[0003] Traditional high-power power semiconductor chips generally use Si IGBTs. With the development of wide-bandgap semiconductors, silicon carbide (SiC) MOSFETs have gradually begun to be applied. Compared with Si IGBTs, SiC MOSFETs have higher breakdown voltages and faster switching speeds, which can reduce the volume of power converters and improve efficiency, and have broad application prospects. However, the faster switching speed makes it easier for SiC MOSFETs to have uneven current distribution problems during parallel connection, especially large and uneven losses will occur during the current rising process.

[0004] Due to the large number of chips, most of the existing analysis models establish local inductance interconnection models, which are difficult to simply and effectively model the current rising process and are difficult to guide the chip parallel layout design. Summary of the Invention

[0005] Aiming at the problems existing in the prior art, the present invention provides a method and system for modeling the current rising process of multi-chip parallel connection based on loop inductance, which can simply and effectively model the current rising process, provide a basis for chip parallel layout design, and promote the popularization and application of SiC MOSFETs in high-power scenarios.

[0006] The present invention is realized through the following technical solutions: A method for modeling the current rising process of multi-chip parallel connection based on loop inductance includes: Writing the current rising process equation based on the loop inductance method of a double-pulse test circuit with multi-SiC MOSFET parallel connection; Obtaining the terminal voltages of each chip of the double-pulse test circuit with multi-SiC MOSFET parallel connection during current rising based on the current rising process equation, so that the complete current sharing condition is achieved among the chips; Based on the condition of achieving complete current sharing among chips and the current rising process equation, a simulation circuit model is established.

[0007] Preferably, the current of the double-pulse test circuit with multiple SiC MOSFETs in parallel is freewheeling through a diode, and the driving signal changes from negative output to positive output, thus entering the current rising stage.

[0008] Preferably, the double-pulse inductor of the double-pulse test circuit with multiple SiC MOSFETs in parallel is a constant current source.

[0009] Preferably, the double-pulse test circuit with multiple SiC MOSFETs in parallel includes 3 chips, having 3 power loops and 3 driving loops.

[0010] Preferably, the current rising process equation is written based on the loop inductance method of the double-pulse test circuit with multiple SiC MOSFETs in parallel. The specific process is as follows: Based on each loop of the double-pulse test circuit with multiple SiC MOSFETs in parallel generating a magnetic field in space, thus generating magnetic fluxes in each loop, and an induced electromotive force is generated through the change of the magnetic fluxes. Based on the electromagnetic induction law of the induced electromotive force, and according to the device channel characteristics, junction capacitance characteristics and loop voltage equation in the double-pulse test circuit with multiple SiC MOSFETs in parallel, the differential equation of each loop voltage is obtained, thus obtaining the current rising process equation.

[0011] Preferably, the device channel characteristics, junction capacitance characteristics and loop voltage equation in the double-pulse test circuit with multiple SiC MOSFETs in parallel are specifically as follows: ; In the formula: v gsj and v dsj are respectively the gate-source voltage and drain-source voltage of the j th chip; i pj is the power loop current, i gj is the driving loop current, j = 1, 2, 3, and the function f represents the port characteristics of the chip in the saturation region, reflecting the relationship between the drain-source current of the chip and the port voltage; gdj is the first-order derivative of the gate-source voltage with respect to time; V DC is the DC bus voltage, V DD is the positive output of the driving signal; R ext and Rint are the external drive resistance and the drive resistances of each chip, respectively; E pj and E gj are the induced electromotive forces of the power loop and the drive loop, respectively, j = 1, 2, 3; i gk represents the sum of the currents of each drive loop, k = 1, 2, 3, C iss is the input capacitance of the chip.

[0012] Preferably, the current rising process equation is specifically:

[0013] where

[0014]

[0015] C = V DC V DC V DC V DD V DD V DD T v = v ds1 v ds2 v ds3 v gs1 v gs2 v gs3 T In the formula ，f ′( v gsj ) is the derivative of the characteristics of each port of the chip with respect to the gate-source voltage; R ext and R int are the external drive resistance and the drive resistances of each chip, respectively, C iss is the input capacitance of the chip; v gsj and v ​​dsj are respectively the gate-source voltage and drain-source voltage of the j th chip, M gjgj is the mutual inductance coefficient between each drive loop, L pj is the self-inductance coefficient of each power loop, M pjgj is the mutual inductance coefficient between each power loop and the drive loop, j = 1, 2, 3; v are the voltages of each port, the first-order derivative of each port voltage with respect to time, the second-order derivative of each port voltage with respect to time.

[0016] Preferably, the condition for achieving complete current sharing among the chips of the dual-pulse test circuit with multiple SiC MOSFETs in parallel is: In the dual-pulse test circuit with multiple SiC MOSFETs in parallel, the self-inductances of each drive loop are equal, the mutual inductances between the drive loops are equal, the mutual inductances of each power loop with respect to the drive loop corresponding to the chip in its own loop are equal, and the mutual inductances of each power loop with respect to the drive loops corresponding to other chips are equal.

[0017] Preferably, the specific process of establishing the simulation circuit model is as follows: According to the device channel and junction capacitance characteristics and loop voltage equations in the dual-pulse test circuit with multiple SiC MOSFETs in parallel, determine a section of connecting wire where there is no coupling between each loop in the dual-pulse test circuit with multiple SiC MOSFETs in parallel. Use finite element simulation software to obtain the self-inductance values and mutual inductance values of each loop, and place inductance elements with self-inductances equal to those of each loop in this section of wire. Set the coupling coefficients between each inductance element according to the mutual inductance values, so as to obtain a simulation circuit model for the current rise process of multiple chips in parallel based on loop inductance.

[0018] A modeling system for the current rise process of multiple chips in parallel based on loop inductance, including; A current rise process equation acquisition module, which is used to write the current rise process equation based on the loop inductance method of the dual-pulse test circuit with multiple SiC MOSFETs in parallel; A terminal voltage acquisition module, which is used to obtain the terminal voltages of each chip in the dual-pulse test circuit with multiple SiC MOSFETs in parallel during current rise based on the current rise process equation, so that the condition of complete current sharing among the chips in the dual-pulse test circuit with multiple SiC MOSFETs in parallel is achieved; A model establishment module, which is used to establish a simulation circuit model based on the condition of complete current sharing among the chips and the current rise process equation.

[0019] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a method for modeling the current rising process of multi-chip parallel connection based on loop inductance. By writing the current rising process equation through the loop inductance method of a double-pulse test circuit based on multi-SiC MOSFET parallel connection, it can accurately describe the rising behavior of the current in the double-pulse test circuit with multi-SiC MOSFET (silicon carbide metal-oxide-semiconductor field effect transistor) parallel connection. By calculating the terminal voltage of each chip, this method can determine the key factors for achieving the complete current sharing condition. In a parallel circuit, current sharing is the key to ensuring that all components evenly share the load and avoid overheating and damage. Therefore, this method helps to improve the reliability and efficiency of the circuit. The established simulation circuit model is based on the actual current rising process equation and current sharing condition, and can accurately reflect the behavior of the actual circuit. Based on the circuit topology described by graph theory, the present invention unifies the Kelvin source, non-Kelvin source, and other connection methods, and describes the most (all) electromagnetic induction effects with the fewest inductance parameters, obtaining a concise and effective equation, which is convenient for analysis and expansion. Compared with the previous modeling methods based on partial inductance, it has the characteristics of simplicity, symmetry, and easy expansion, and describes the most (all) electromagnetic induction effects with the fewest inductance parameters. The chip current sharing criterion based on this model is also more concise and reasonable.

[0020] Furthermore, this model can perform concise and effective modeling of the current rising process, providing a basis for the chip parallel layout design. Compared with the traditional trial-and-error method, the design method based on accurate modeling and simulation can significantly shorten the development cycle of the circuit and promote the popularization and application of SiC MOSFET in high-power scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings: Figure 1 is a modeling flowchart for writing the current rising process of multi-chip parallel connection based on loop inductance; Figure 2 is the multi-chip parallel double-pulse test circuit and all loops of the present invention; Figure 3 is the simulation circuit corresponding to the modeling method of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following further describes the present invention in detail with specific embodiments, which are explanations rather than limitations of the present invention.

[0023] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0024] A method for modeling the current rising process of multi-chip parallel connection based on loop inductance is as Figure 1 shown, and the specific steps are as follows: (1) Build a double-pulse test circuit model for the parallel connection of multiple SiC MOSFET (chips). Taking 3 chips as an example, there are 3 power loops and 3 drive loops. As Figure 2 shown. The double-pulse circuit consists of a DC power supply, a hollow inductor, a device under test (i.e., the parallel connection of 3 SiC MOSFET chips), a freewheeling diode, and a drive circuit. The drive circuit sends out two pulse signals. When the drive signal is high, the device under test conducts, and the power supply charges the inductor; when the drive signal is low, the inductor current is freewheeled by the diode. In the present invention, during the process that the drive signal changes from low to high for the second time, the drive signal changes from negative output to positive output, and the inductor current commutates from the freewheeling diode to the device under test, that is, the current rising stage. During this stage, due to the clamping effect of the diode, the change in the drain-source voltage of the chip is small. Therefore, the drain-source capacitance of the SiC MOSFET is ignored, and only the input capacitance of the SiC MOSFET is retained C iss . It is assumed that the chips are in good consistency and all parameters are the same. The diode is treated as an ideal diode, and the double-pulse inductor is regarded as a constant current source.

[0025] This circuit diagram uses concepts related to graph theory. A node corresponds to a set of conductive connections in the actual circuit. The edges connecting nodes to nodes must contain components, and the components include semiconductor devices, resistors, capacitors, and lumped-parameter inductors (such as double-pulse inductors), but do not include distributed-parameter inductors (such as the parasitic inductance of the commutation loop). Therefore, regardless of whether the drive connection is through a non-Kelvin source connection or a Kelvin source connection, only the distributed-parameter inductance changes, and all source networks correspond to Figure 2 the source nodes in

[0026] (2) Write the current rising process equation based on the loop inductance method of the double-pulse test circuit for the parallel connection of multiple SiC MOSFETs, and give the conditions for complete current sharing; First, determine the independent circuits to be studied. The dual-pulse inductor is considered a constant-current source and does not interact with other circuits, making it easy to observe that there are a total of 6 independent circuits. According to symmetry, 3 power circuits and 3 drive circuits can be selected, and the corresponding loop currents are respectively set as i pj and i gj ( j = 1, 2, 3, the same below). Each circuit of the dual-pulse test circuit based on multi-SiC MOSFET parallel connection generates a magnetic field in space, thereby generating magnetic flux in each circuit. An induced electromotive force is generated through the change of the magnetic flux. Based on the electromagnetic induction law of the induced electromotive force, as well as according to the device channel characteristics, junction capacitance characteristics, and loop voltage equation in the dual-pulse test circuit based on multi-SiC MOSFET parallel connection, the differential equation of the voltage of each circuit is obtained, and thus the current rise process equation is obtained.

[0027] Among them, according to the electromagnetic induction law, there is (1) Among them, E pj and E gj are the induced electromotive forces of each circuit respectively, and each L and M are the self-inductance and mutual-inductance coefficients of each circuit, j = 1, 2, 3. For example, E p1 is the induced electromotive force of power circuit 1, E p2 is the induced electromotive force of power circuit 2, E p3 is the induced electromotive force of power circuit 3, E g1 is the induced electromotive force of drive circuit 1, E g2 is the induced electromotive force of drive circuit 2, E g3 is the induced electromotive force of drive circuit 3; i p1 The induced current of power circuit 1, i p2 The induced current of power circuit 2, i p3 The induced current of power circuit 3, i g1 The induced current of drive circuit 1, i g2 The induced current of drive circuit 2, i g3 The induced current of drive circuit 3,L p1 is the self-inductance coefficient of power circuit 1; L p2 is the self-inductance coefficient of power circuit 2; L p3 is the self-inductance coefficient of power circuit 3; M g1g2 is the mutual inductance coefficient between drive circuit 1 and drive circuit 2, M g1g3 is the mutual inductance coefficient between drive circuit 1 and drive circuit 3, M g2g1 is the mutual inductance coefficient between drive circuit 2 and drive circuit 1, M g2g3 is the mutual inductance coefficient between drive circuit 2 and drive circuit 3, M g3g1 is the mutual inductance coefficient between drive circuit 3 and drive circuit 1, M g3g2 is the mutual inductance coefficient between drive circuit 3 and drive circuit 2, M p1g1 is the mutual inductance coefficient between power circuit 1 and drive circuit 1, M p1g2 is the mutual inductance coefficient between power circuit 1 and drive circuit 2; M p1g3 is the mutual inductance coefficient between power circuit 1 and drive circuit 3; M p2g1 is the mutual inductance coefficient between power circuit 2 and drive circuit 1; M p2g2 is the mutual inductance coefficient between power circuit 2 and drive circuit 2; M p2g3 is the mutual inductance coefficient between power circuit 2 and drive circuit 3; M p3g1 is the mutual inductance coefficient between power circuit 3 and drive circuit 1; M p3g2 is the mutual inductance coefficient between power circuit 3 and drive circuit 2; M p3g3 is the mutual inductance coefficient between power circuit 3 and drive circuit 3; It can be obtained that n 2 n independent circuits are connected in parallel for n (2 n + 1) inductance coefficients.

[0028] According to the device channel and junction capacitance characteristics and the loop voltage equation, it is easy to list: (2) Among them, v gsj and vdsj Respectively j The gate-source voltage and drain-source voltage of each chip; i pj is the power loop current, i gj is the driving circuit current, j = 1, 2, 3, function f It is represented as the port characteristics of SiC MOSFET chip in the saturation region, reflecting the relationship between the chip's drain-source current and the port voltage; gdj is the first-order derivative of the gate-source voltage with respect to time; V DC is the DC bus voltage, V DD It is the positive output of driving signal; R ext and R int They are external drive resistor and each chip drive resistor respectively; E pj and E gj are the induced electromotive force of the power circuit and the drive circuit respectively, j = 1, 2, 3; i gk Represents the sum of the currents of each drive circuit, k = 1, 2, 3, C iss is the input capacitance of the SiC MOSFET.

[0029] Combining equations (1) and (2), we can sort out the differential equations for each voltage and obtain (3) in,

[0030]

[0031] C= [ V DC V DC V DC V DD V DD V DD ] T v = [ v ds1 vds2 v ds3 v gs1 v gs2 v gs3 T where 0 is a zero matrix of size 3×3, f ′ (v gsj ) is the derivative of the port characteristics of the SiC MOSFET with respect to the gate-source voltage, v are the port voltages, where, v gs1 is the gate-source voltage of the first chip, v gs2 is the gate-source voltage of the second chip, v gs3 is the gate-source voltage of the third chip, v ds1 is the drain-source voltage of the first chip, v ds2 is the drain-source voltage of the second chip, v ds3 is the drain-source voltage of the third chip; The first-order derivative of the port voltages with respect to time, The second-order derivative of the port voltages with respect to time, V DC is the DC bus voltage, V DD is the positive output of the drive signal; R ext and R int are the external drive resistance and the drive resistances of each chip, respectively, M gjgj is the mutual inductance coefficient between the drive loops, L pj is the self-inductance coefficient of each power loop, M pjgj is the mutual inductance coefficient between each power loop and the drive loop, j = 1, 2, 3; Equation (3) is the current rise process equation written based on the loop inductance method, which gives the terminal voltages of each chip during current rise.

[0032] To achieve current sharing, it should satisfy v gs1 ≡ v gs2 ≡ v gs3 ​, according to symmetry, the condition for achieving complete current sharing among chips in the double-pulse test circuit with multiple SiC MOSFETs in parallel is: In the lower-right 3×3 sub-matrices of matrices A and B, the diagonal elements are equal to each other, that is L g1 = L g2 = L g3 , M p1g1 = M p2g2 = M p3g3 ; In the lower-right 3×3 sub-matrices of matrices A and B, the elements other than the diagonal elements are equal to each other, that is M g1g2 = M g1g3 = M g2g3 , M p1g2 = M p1g3 = M p2g1 = M p2g3 = M p3g1 = M p3g2 .

[0033] That is, the self-inductances of the drive loops in the double-pulse test circuit with multiple SiC MOSFETs in parallel are equal, the mutual inductances between the drive loops are equal, the mutual inductances of each power loop with respect to the drive loop corresponding to the chip in its own loop are equal, and the mutual inductances of each power loop with respect to the drive loops corresponding to other chips are equal.

[0034] Satisfying the above conditions can achieve complete current sharing among chips. By calculating the terminal voltages of each chip, this method can determine the key factors for achieving the complete current sharing condition. In a parallel circuit, current sharing is crucial to ensure that all components evenly share the load and avoid overheating and damage. Therefore, this method helps to improve the reliability and efficiency of the circuit.

[0035] (3) Establish a simulation circuit model. The loop inductance acts on the circuit with an electromotive force, and it is difficult for circuit software to directly simulate according to Figure 2 Therefore, it is necessary to build a simulation model according to equation (2). The specific method is as follows: According to the device channel and junction capacitance characteristics and loop voltage equations in the double-pulse test circuit with multiple SiC MOSFETs in parallel, a connecting wire segment without coupling between each loop in the double-pulse test circuit with multiple SiC MOSFETs in parallel is determined. The self-inductance values and mutual-inductance values of each loop are obtained using finite element simulation software, and inductance elements with self-inductance values of each loop are placed inside this wire segment. The coupling coefficients are set between each inductance element according to the mutual-inductance values, so as to obtain a simulation circuit model for the current rise process of multi-chip parallel connection based on loop inductance. The established simulation circuit model is based on the actual current rise process equation and current sharing condition, can accurately reflect the behavior of the actual circuit, and is used to predict the influence of different design parameters on the circuit performance, so as to guide the optimized design of the circuit.

[0036] The independent connecting wire of the power loop can take the drain of the chip, and the independent connecting wire of the drive loop can take the gate of the chip. Set the excitation and current magnitude at the corresponding positions in the Ansys Maxwell software, and calculate the magnetic field energy to obtain the self-inductance value and mutual-inductance value of each, as Figure 3 shown.

[0037] This method is not only applicable to SiC MOSFETs, but can also be extended to other types of semiconductor devices and parallel circuits. Its modeling method based on physical principles makes this method have strong adaptability and generality. Compared with the traditional trial-and-error method, the design method based on accurate modeling and simulation can significantly shorten the development cycle of the circuit. Through simulation, different design options can be tested without building an actual prototype, thus reducing costs and accelerating product market entry.

[0038] The present invention also provides a multi-chip parallel current rise process modeling system based on loop inductance, including; A current rise process equation acquisition module, configured to write the current rise process equation based on the loop inductance method of the double-pulse test circuit with multiple SiC MOSFETs in parallel; A terminal voltage acquisition module, configured to obtain the terminal voltage of each chip in the double-pulse test circuit with multiple SiC MOSFETs in parallel when the current rises based on the current rise process equation, so that the complete current sharing condition is achieved between each chip in the double-pulse test circuit with multiple SiC MOSFETs in parallel; A model establishment module, configured to establish a simulation circuit model based on the complete current sharing condition between each chip and the current rise process equation.

[0039] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention; any ordinary technician in the industry can smoothly implement the present invention as shown in the accompanying drawings of the specification and as described above; however, any slight changes, modifications, and equivalent variations made by those skilled in the art within the scope of the technical solution of the present invention by using the technical content disclosed above are equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications, and evolutions made to the above embodiments based on the substantial technology of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for modeling the current rise process of multi-chip parallel connection based on loop inductance, characterized in that: include, Write the current rise process equation based on the loop inductance method of the double pulse test circuit of multiple SiC MOSFETs in parallel; Based on the current rising process equation, the terminal voltage of each chip in the double pulse test circuit with multiple SiC MOSFETs in parallel is obtained when the current rises, so that the chips can achieve complete current sharing conditions; A simulation circuit model is established based on the conditions for achieving complete current sharing among chips and the current rising process equation.

2. The method for modeling the current rise process of multiple chips in parallel based on loop inductance according to claim 1, characterized in that: The current of the double-pulse test circuit with multiple SiC MOSFETs connected in parallel is freewheeling through the diode, and the drive signal is converted from negative output to positive output, thereby entering the current rising stage.

3. The method for modeling the current rise process of multiple chips in parallel based on loop inductance according to claim 1, characterized in that: The double pulse inductor of the double pulse test circuit with multiple SiC MOSFETs in parallel is a constant current source.

4. The method for modeling a current rise process of multiple chips in parallel based on loop inductance according to claim 1, characterized in that: The double pulse test circuit for multiple SiC MOSFETs in parallel includes three chips with three power loops and three drive loops.

5. The method for modeling the current rise process of multiple chips in parallel based on loop inductance according to claim 1, characterized in that: The loop inductance method of the double pulse test circuit based on multiple SiC MOSFETs in parallel is used to write the current rising process equation. The specific process is: Each loop of the double-pulse test circuit based on multiple SiC MOSFETs in parallel generates a magnetic field in space, thereby generating magnetic flux in each loop. The change of magnetic flux generates induced electromotive force. Based on the law of electromagnetic induction of induced electromotive force, and according to the device channel characteristics, junction capacitance characteristics and loop voltage equation in the double-pulse test circuit of multiple SiC MOSFETs in parallel, the differential equation of each loop voltage is obtained, thereby obtaining the current rising process equation.

6. The method for modeling the current rise process of multiple chips in parallel based on loop inductance according to claim 5, characterized in that: The device channel characteristics, junction capacitance characteristics and loop voltage equations in the double pulse test circuit of multiple SiC MOSFETs in parallel are as follows: ； Where: v gsj and v dsj Respectively j The gate-source voltage and drain-source voltage of each chip; i pj is the power loop current, i gj is the driving circuit current, j = 1, 2, 3, function f It is expressed as the port characteristics of the chip in the saturation region, reflecting the relationship between the chip's drain-source current and the port voltage; gdj is the first-order derivative of the gate-source voltage with respect to time; V DC is the DC bus voltage, V DD It is the positive output of driving signal; R ext and R int They are external drive resistor and each chip drive resistor respectively; E pj and E gj are the induced electromotive force of the power circuit and the drive circuit respectively, j = 1, 2, 3; i gk Represents the sum of the currents of each drive circuit, k = 1, 2, 3, C iss is the input capacitance of the chip.

7. The method for modeling the current rising process of multiple chips in parallel based on loop inductance according to claim 5 is characterized in that: The current rising process equation is as follows: in, C = [ V DC V DC V DC V DD V DD V DD ] T v = [ v ds1 v ds2 v ds3 v gs1 v gs2 v gs3 ] T In the formula ，f ′( v gsj ) is the derivative of each port characteristic of the chip with respect to the gate-source voltage; R ext and R int They are external drive resistors and each chip drive resistor, C iss is the input capacitance of the chip; v gsj and v dsj Respectively j The gate-source voltage and drain-source voltage of each chip, M gjgj is the mutual inductance coefficient between each driving circuit, L pj is the self-inductance coefficient of each power circuit, M pjgj is the mutual inductance coefficient between each power circuit and the drive circuit, j =1,2,3; v is the voltage at each port, The first-order derivative of the voltage at each port with respect to time, The second derivative of the voltage at each port with respect to time.

8. The method for modeling a current rise process of multiple chips in parallel based on loop inductance according to claim 1, characterized in that: The conditions for achieving complete current sharing between the chips in the double pulse test circuit with multiple SiC MOSFETs in parallel are: The self-inductance of each drive circuit in the double-pulse test circuit with multiple SiC MOSFETs in parallel is equal, the mutual inductance between the drive circuits is equal, the mutual inductance of each power circuit to the drive circuit corresponding to the chip of the circuit is equal, and the mutual inductance of each power circuit to the drive circuit corresponding to other chips is equal.

9. The method for modeling the current rising process of multiple chips in parallel based on loop inductance according to claim 1 is characterized in that: The specific process of establishing a simulation circuit model is: According to the conditions of achieving complete current sharing between chips and the device channel and junction capacitance characteristics and loop voltage equation in the double pulse test circuit of multiple SiC MOSFETs in parallel, a section of connecting line without coupling between the various loops in the double pulse test circuit of multiple SiC MOSFETs in parallel is determined, and the self-inductance and mutual inductance of each loop are obtained using finite element simulation software. Inductance elements with inductance values ​​equal to the self-inductance of each loop are placed in the section of line, and coupling coefficients are set between the inductance elements according to the mutual inductance values, thereby obtaining a simulation circuit model of the current rising process of multi-chip parallel connection based on loop inductance.

10. A multi-chip parallel current rising process modeling system based on loop inductance, characterized in that: The method for modeling a multi-chip parallel current rising process based on loop inductance according to any one of claims 1 to 9 comprises: The current rising process equation acquisition module is used to write the current rising process equation based on the loop inductance method of the double pulse test circuit of multiple SiC MOSFETs in parallel; The terminal voltage acquisition module is used to obtain the terminal voltage of each chip of the double pulse test circuit with multiple SiC MOSFETs connected in parallel when the current rises based on the current rising process equation, so that the chips of the double pulse test circuit with multiple SiC MOSFETs connected in parallel can achieve a complete current sharing condition; The model building module is used to build a simulation circuit model based on the conditions for achieving complete current sharing among the chips and the current rising process equation.

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