Method for checking spacing in large-scale integrated circuit layout

Abstract

The invention relates to a method for checking spacing in a large-scale integrated circuit layout, which belongs to the technical field of integrated circuit computer aided design, and comprises the following steps: S1, dividing an integrated circuit layout to be processed into a plurality of local layouts according to a preset division rule, including an original local layout and an interference local layout; outwards expanding the edges, determined by a preset division rule, of the interference local layouts to obtain expanded local layouts; s2, checking whether the edges of all the functional parts in all the local layouts meet the constraint condition upper limit corresponding to the selected preset checking rule one by one according to the currently selected preset checking rule so as to screen out the edges meeting the potential conditions; s3, forming associated edge pairs, and screening the associated edge pairs through a filter to obtain associated edge pairs meeting filtering conditions; and S4, carrying out secondary cutting on the associated edge pairs according to the cutting ranges of the associated edge pairs meeting the filtering conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of computer-aided design of integrated circuits, and particularly to a method for checking the internal spacing in a large-scale integrated circuit layout. Background Art

[0002] In the past 30 years, the development of integrated circuit technology has followed "Moore's Law", that is, the number of transistors on a chip doubles approximately every two years. With this trend continuing, the feature size of the chip has been continuously reduced, and the integration degree of a single chip has also been significantly improved. However, as the chip scale continues to expand, the design rules that need to be verified in each stage of integrated circuit design have become increasingly complex and numerous. In this context, the design rule check (DRC) of the integrated circuit layout has become particularly important. DRC is not only crucial for eliminating design errors and reducing design costs, but also plays a key role in reducing the risk of product failure caused by design defects.

[0003] CN102663169A discloses a method for checking the design rules of an integrated circuit layout. The method is as follows: abstracting the layout graphics into a polygon data representation defined by a series of horizontal boundaries, defining and implementing a polygon feature extraction method, a logical operation method between polygons, and an enumeration traversal operation method for polygon connected regions and boundary edges. On this basis, the design rules are checked and marked. The invention can perform the mutual conversion of data structures between the interconnecting wire rectangles and the layout polygons, define and implement polygon operations and the enumeration traversal operation method for polygon boundary edges, and check the design rules on this basis.

[0004] In particular, in the design of very large scale integrated circuits (VLSIs), the layout scale has expanded rapidly, which makes it a major challenge for major electronic design automation (EDA) manufacturers to complete the verification work of the design scheme within an effective time. As one of the core functions of DRC, the dimension check is particularly important. The internal spacing check is an important part of the dimension check, aiming to ensure that the spacing between polygons inside and between different layers meets specific design specifications. This check is applicable to both the internal spacing check of polygons within a single layer and the internal spacing check of polygons across layers to support various application scenarios such as width check and overlap check (see Figure 4 ). To meet different check requirements, a variety of filters have also been designed for the internal spacing check, such as direction filters, connectivity filters, shielding filters, projection filters, and intersection filters, etc.

[0005] Faced with the rapid growth of integrated circuit scale, how to efficiently and accurately check the internal spacing has become one of the key issues to be solved in DRC work. Traditional methods are difficult to meet the current requirements for efficiency and accuracy, especially when dealing with complex ultra-large-scale integrated circuits. Therefore, developing a technical means to quickly locate and verify potential problem points while ensuring the comprehensiveness and accuracy of the results has become an important way to improve the quality and reliability of integrated circuit design.

[0006] In addition, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making the present invention, but due to space limitations, not all details and contents are listed in detail. However, this does not mean that the present invention does not have the characteristics of these prior arts. On the contrary, the present invention already has all the characteristics of the prior art, and the applicant reserves the right to add relevant prior art to the background technology. Summary of the invention

[0007] In view of the deficiencies of the prior art, the present invention aims to provide a method for checking the spacing within a large-scale integrated circuit layout, which achieves comprehensive and accurate design rule checking through multi-threaded concurrent processing, local layout expansion and multiple algorithm optimizations to solve at least some of the above-mentioned technical problems.

[0008] The present invention addresses the problem of inner-pitch inspection in large-scale integrated circuit design and proposes a technical solution based on dynamic partitioning and intelligent cropping, achieving a breakthrough innovation in the problems of computational efficiency bottleneck and high false alarm rate commonly faced by existing technologies. When traditional methods process layouts with tens of millions of polygon cells, they often adopt a full-map traversal strategy or rely on manual experience to delimit local detection regions. The former fails to meet the time window requirements of advanced process nodes due to the exponential growth of geometric relationship calculations, while the latter results in the loss of edge data integrity due to boundary effects caused by mechanical partitioning. Especially in the scenario of multi-layer superposition constraints, existing algorithms often generate a large number of pseudo-violation points because they cannot accurately capture the spatial topological relationships across regions, forcing designers to spend a lot of time on manual review. The present invention constructs an intelligent partitioning engine and innovatively divides the layout space into dynamically related blocks with semantic associations. When dividing, it comprehensively considers circuit complexity, regional density differences, and hardware resource distribution, and dynamically adjusts the local layout size through an adaptive algorithm, so that a refined partitioning strategy is adopted for high-density regions, while the processing range is appropriately expanded for low-density regions. This non-uniform partitioning mechanism effectively achieves dynamic balance of computational load. Aiming at the defects of traditional methods in edge processing, the present invention introduces an interference region expansion mechanism, which expands the edge region outward according to the preset rule constraint upper limit. For example, when processing edge pitch rules, the expansion amplitude is set as the upper limit value of the constraint condition (such as 2 nanometers) to ensure that the geometric relationships across local layouts can be completely captured. At the same time, a spatial index is constructed through the R-tree algorithm to transform the traditional linear search based on geometric coordinates into an efficient range query. Combined with the collaborative work of multiple filters, most invalid edge pairs can be quickly excluded. The cropping module of the present invention constructs a two-way cropping range and precisely intercepts the violation section among the associated edge pairs that meet the filtering conditions. The sub-nanometer cropping window constructed by using the upper and lower limits of the constraint conditions can improve the violation positioning accuracy to 1 / 5 of the process node level, directly outputting the specific coordinate interval of the edge pair that violates the minimum pitch requirement. Compared with the design of traditional methods that can only mark the approximate region, the output result of the present invention has a complete spatial coordinate mapping relationship and can guide automatic correction without manual secondary verification. Based on the development experience of traditional DRC tools, those skilled in the art usually adopt a strategy of homogenized grid partitioning combined with brute-force search. This rigid processing method cannot effectively relieve the exponentially growing computational pressure through hardware acceleration when facing process-sensitive regions (such as the gate pitch region of FinFET devices), nor can it handle complex stack constraints while maintaining detection accuracy.The present invention innovatively and deeply integrates the dynamic load balancing mechanism with the spatial correlation mining. Specifically, through the solution of "adjusting the fineness of local layout division based on the density difference of regional design", it automatically implements encrypted grid division in process-sensitive areas and uses coarse-grained division in low-risk areas; at the same time, combined with the strategy of "optimizing the call order according to the filter efficiency and filtering probability", it preferentially calls filters of different filtering types in key areas. This adaptive detection mechanism based on spatial features enables computing resources to accurately focus on areas where process rules are prone to violations. This technical path that deeply couples the physical characteristics of the layout with distributed computing breaks through the mode of separate execution of geometric processing and rule checking in traditional tools, and realizes the dynamic balance of computing density while maintaining topological integrity. In addition, the unique global compensation mechanism in the present invention establishes a cross-thread edge pair relationship database to uniformly verify geometric relationships beyond the scope of local layout, effectively solving the problem of edge missed detection existing in traditional distributed processing. In ultra-high density designs, the layout verification cycle is greatly shortened compared with traditional methods, and at the same time, the false alarm rate is controlled within an extremely low standard.

[0009] The present invention discloses a method for in-pitch inspection within a large-scale integrated circuit layout, which includes:

[0010] S1. Divide the integrated circuit layout to be processed into several local layouts according to a preset division rule, which includes an original local layout and an interference local layout. Among them, the interference local layout is: among the local layouts obtained by division, those local layouts where the data on the edge constituting the preset division rule of the corresponding local layout interferes with the adjacent layout; in a manner depending on the currently selected preset inspection rule, based on the upper limit of the constraint conditions corresponding to the selected preset inspection rule, expand the edge determined by the preset division rule of these interference local layouts outward to obtain an expanded local layout;

[0011] S2. For all local layouts including the expanded local layout and the original local layout, check whether the edges of all functional components within all local layouts meet the upper limit of the constraint conditions corresponding to the selected preset inspection rule one by one according to the currently selected preset inspection rule, so as to screen out the edges that meet the potential conditions;

[0012] S3. Form associated edge pairs from the edges that appear in pairs among these edges that meet the potential conditions, and screen these associated edge pairs through one or more filters with different filtering types to obtain associated edge pairs that meet the filtering conditions;

[0013] S4. Perform secondary clipping on these associated edge pairs according to the clipping range of each associated edge pair that meets the filtering conditions to obtain a set of clipped edge clusters that directly or indirectly form the negative result of the in-pitch inspection.

[0014] Preferably, in the integrated circuit layout inspection technology, the "preset partitioning rule" refers to a predefined strategy for dividing the complete layout into multiple local layouts; the "preset inspection rule" refers to a set of geometric relationship constraints preconfigured in the internal spacing inspection, which may include the minimum spacing, parallel margin, and / or overlapping area, etc. Among them, the upper limit of the constraint conditions corresponding to the preset inspection rule refers to the maximum value of the internal spacing in the inspection rule.

[0015] Preferably, all the original local layouts and all the interfering local layouts together constitute the integrated circuit layout to be processed. In other words, among the local layouts obtained by dividing according to the preset partitioning rule, the other local layouts except the interfering local layouts are the original local layouts, which are the initially divided areas without interference phenomena and do not need to be expanded.

[0016] Preferably, "interference" refers to the phenomenon that after the local layout is divided, the data on the edge of a certain local layout needs to interact with the data of the adjacent layout to meet the design rule check. The specific manifestations are: geometric overlap: an edge (or polygon structure) crosses the boundaries of two or more local layouts; rule constraint: the relationship between the data on both sides of the edge needs to meet specific design rules (such as spacing, projection, etc.); data dependence: only processing the data of the current local layout may lead to incorrect rule judgment (missing inspection or false alarm).

[0017] Preferably, the "edge" is determined by the preset partitioning rule and constitutes the outermost boundary of the corresponding divided local layout. "Data" refers to the set of geometric objects and their attributes in the integrated circuit layout that can be processed by the rule check engine. "Data on the edge" specifically refers to the geometric objects in the area near the edge of the local layout after the local layout is divided.

[0018] Preferably, the expanded local layout is the local layout obtained by expanding the edge of the interfering local layout determined by the preset partitioning rule outward based on the upper limit of the constraint conditions corresponding to the selected preset inspection rule. The edge of the interfering local layout can be expanded outward in a manner of an expansion amplitude to obtain the expanded local layout, where the expansion amplitude is determined according to the expansion rule corresponding to the upper limit of the constraint conditions corresponding to the selected preset inspection rule.

[0019] Preferably, a "functional component" refers to a physical structure unit that realizes a specific circuit function in an integrated circuit. The "edge of the functional component" refers to the geometric structure boundary line that realizes the electrical function of the circuit, and its physical parameters are restricted by the semiconductor manufacturing process rules and need to meet design rules such as the minimum spacing and width. Specifically, it refers to the geometric boundaries of key structures such as metal interconnects and transistor active regions, and needs to be verified by design rule check (DRC) to meet the process requirements.

[0020] Preferably, if there is a situation where the edge distance within the corresponding local layout under inspection is less than the upper limit of the constraint condition corresponding to the selected preset inspection rule, then the corresponding edge of the corresponding functional component in the corresponding local layout under inspection is preliminarily determined as the "edge meeting potential conditions". The "edge distance" refers to the minimum Euclidean distance between the edges of adjacent functional components within the same process layer, and this distance needs to meet the minimum physical isolation requirements of semiconductor manufacturing processes for specific structures (such as metal wires, transistor gates, etc.). Its value is comprehensively determined by lithography accuracy, electrical isolation requirements, and process parameters, corresponding to the preset inspection rule.

[0021] Preferably, the "edges that appear in pairs with each other" refer to a group of edges that meet the determination rule when preliminarily determining the edges meeting potential conditions, and this group of edges forms an "associated edge pair" in a pairwise manner.

[0022] Preferably, the main filters include an intersection filter, a direction filter, a projection filter, etc., and the filtering types of these filters are different from each other. The "filtering condition" is formed based on the combination of all enabled filters, that is, the associated edge pairs that pass through the screening of all enabled filters are the associated edge pairs that meet the filtering condition.

[0023] Preferably, the "cropping range" refers to the area range constructed based on the upper and lower limits of the constraint condition corresponding to the preset inspection rule with each edge of the associated edge pair that meets the filtering condition as the reference. "Secondary cropping" refers to intercepting the part of the first edge in the associated edge pair within the cropping range constructed based on the other edge (the second edge), and intercepting the part of the second edge in the associated edge pair within the cropping range constructed based on the first edge. The intercepted parts of each pair of associated edge pairs can form a group of edge clusters, and several groups of edge clusters can form an edge cluster set. The edge clusters in the edge cluster set are the targets that meet the preset inspection rule. Therefore, if the requirements of the design rule are violated, they can be used as or indirectly form a negative result for the inner distance inspection when generating the result.

[0024] According to a preferred implementation, when dividing the local layout according to the preset division rule, the optimal local layout size is determined according to the circuit complexity and physical resources, and the division fineness of the local layout can be adjusted based on the differences in design densities of different regions to ensure load balance between local layouts.

[0025] According to a preferred implementation, for all local layouts including the extended local layout and the original local layout, the divided local layouts are assigned to the available threads in a pre-created and reusable thread pool to concurrently perform the inner distance inspection of the local layouts.

[0026] According to a preferred embodiment, the determination rule for the edges meeting the potential conditions is as follows: If there is a situation where the edge spacing within the corresponding inspected partial layout is less than the upper limit of the constraint condition corresponding to the selected preset inspection rule, then the corresponding edge of the corresponding functional component in the corresponding inspected partial layout is preliminarily determined as the "edge meeting the potential conditions".

[0027] According to a preferred embodiment, the situation of "the edge spacing being less than the upper limit of the constraint condition corresponding to the selected preset inspection rule" is determined in the following way: For each edge of all functional components, the upper limit of the constraint condition is used to construct a search range based on these edges respectively, and then all the edges intersecting with this search range are located and retrieved through the R-tree algorithm.

[0028] The reason why the R-tree algorithm is preferred in the present invention is that when using the spatial indexing technology to locate and retrieve the edges in each partial layout that initially meet the rule constraint conditions to screen out the edges meeting the potential conditions, the R-tree algorithm demonstrates a series of unique advantages, especially in comparison with the Bounding Volume Hierarchy (BVH), grid index, Bloom filter, KD-tree, and quadtree. In particular, compared with the grid index, the R-tree adapts to the data distribution by dynamically adjusting the Minimum Bounding Rectangle (MBR), avoiding the problem of space waste or excessive subdivision that may be caused by the fixed-size grids in the grid index; compared with the quadtree, although the quadtree can also effectively perform two-dimensional space division, the R-tree can better handle datasets with irregular shapes and is more suitable for complex queries in multi-dimensional spaces. In comparison with the KD-tree, although the KD-tree is good at high-dimensional space division, its efficiency may decline when dealing with non-uniformly distributed data. The R-tree can flexibly organize data in different dimensions and is more suitable for handling the irregular data distributions commonly found in practical applications. In addition, in terms of the ability of dynamic update, compared with the Bloom filter mainly used for fast membership queries (which cannot directly support the insertion or deletion operations of spatial data), the R-tree allows efficient dynamic update of data, which is crucial for the integrated circuit layout design that requires frequent modification. Compared with the Bounding Volume Hierarchy (BVH), although the BVH also supports dynamic update, when dealing with a large number of overlapping objects, the R-tree can more effectively manage these overlapping regions and provide more accurate query results. Especially in terms of optimizing space coverage, compared with the quadtree and grid index, the R-tree divides the space in an adaptive manner, enabling it to optimize the storage structure according to the actual data distribution, reduce unnecessary division, and improve the query efficiency. The BVH is usually used to accelerate graphics computing tasks such as collision detection. When dealing with non-geometric type of spatial queries, the R-tree provides a more general and efficient solution. Therefore, in terms of overall performance, the R-tree combines the above advantages and can efficiently execute various operations such as range queries and nearest neighbor searches in complex multi-dimensional spaces, and is particularly suitable for application scenarios such as integrated circuit layout design that require precise management and query of a large amount of spatial data.

[0029] According to a preferred embodiment, all edges intersecting with the search range constructed using the upper limit of the constraint condition for any target edge can be associated with the target edge, where the shape profile of the search range is determined based on the measurement method, and the measurement method includes Euclidean measurement and rectangular measurement.

[0030] According to a preferred embodiment, the filters used in the filter checking stage are independently implemented in their respective filter types and have no dependencies on each other. The calling order of the filters sorted according to their efficiency and filtering probability follows the following principle: Give priority to processing the filters that take relatively less time and filter relatively more.

[0031] According to a preferred embodiment, when performing secondary clipping on any pair of associated edges, intercept the part of the first edge in the pair of associated edges within the clipping range constructed based on the second edge, and intercept the part of the second edge in the pair of associated edges within the clipping range constructed based on the first edge. The intercepted parts of each pair of associated edges form a set of edge clusters, where the edge clusters are all or part of the data of the associated edge pairs that meet the filtering conditions.

[0032] According to a preferred embodiment, after completing the inner-spacing check of all local layouts, if it is found that there is data that requires further global processing, enter the global processing stage, where the judgment conditions for global processing include: two or more edges that exceed the range of the currently processed local layout, and the relationship between them cannot be determined only by local data.

[0033] Furthermore, the judgment condition for global processing is:

[0034] Let D be the large-scale integrated circuit layout data set to be inspected, and L i represent the data subset of the i-th local layout, where i = 1, 2,..., n, and n is the total number of local layouts. Let G represent the global data set, which is used to store the data information that meets the global processing rules.

[0035] For each local layout L i , define a function f(L i ) to represent the process of performing an inner-spacing check on this local layout. If there are edges e i and e j and e k (or more edges) in L

[0036] that exceed the current local layout range, and their relationship (such as intersection or proximity) cannot be determined only by local data, then the information of these edges will be recorded and added to the global data set G. j ,e k,L i ), which represents edge e j and e k in the local layout L i to determine whether the relationship cannot be determined only by local data:

[0037]

[0038] Therefore, for each local layout L i , a global data set G can be constructed as follows:

[0039] G = G ∪ {(e j , e k , L i ) | P(e j , e k , L i ) = True}.

[0040] After checking all local layouts, that is, after applying the function f(L i ) to all L i , the global data set G will be processed. Define a global processing function g(G), which is responsible for parsing and validating all data in G to determine whether the actual relationships between them (such as intersection or proximity) comply with the design rules.

[0041] According to a preferred embodiment, after obtaining the result edge pairs through precise cutting operations, corresponding output results are generated according to specific rules. The output results include various forms such as edge output, polygon output, and error-oriented output. Among them, connected edges, polygons, and edge clusters are merged to form a complete result set.

[0042] The present invention divides the large-scale integrated circuit layout into multiple local layouts and uses multi-threaded concurrent technology for internal pitch checking, significantly improving the checking efficiency. Specifically, the method proposed by the present invention not only achieves parallel processing, but also solves the challenges brought by boundary effects by expanding the local layout, ensuring the accuracy of data at the boundaries. In addition, this method improves the search efficiency by introducing the R-tree algorithm and further optimizes the checking process by sorting the filters according to their efficiency and filtering probability, so that only those edge pairs that are truly likely to meet the rules will enter the subsequent precise clipping stage. This method not only reduces unnecessary computational effort, but also speeds up the entire checking process. Practical applications show that this processing solution can efficiently and accurately complete the internal pitch checking, greatly improving the efficiency and reliability of design verification, providing strong support for high-quality chip manufacturing. At the same time, by reducing the coupling between steps, the flexibility and maintainability of the system are enhanced, enabling designers to focus more on innovation and optimization work, thus promoting the progress of the entire industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of the design rule checking process for an integrated circuit layout;

[0044] Figure 2 is a step diagram of the method for internal pitch checking provided by the present invention;

[0045] Figure 3 is a flowchart of the method for internal pitch checking provided by the present invention;

[0046] Figure 4 is a schematic diagram of the basic internal pitch checking service;

[0047] Figure 5 is a schematic diagram of the layout division method provided by the present invention;

[0048] Figure 6 is a schematic diagram of the layout with boundary effects provided by the present invention;

[0049] Figure 7 is Figure 6 the layout data in , showing the schematic diagram after being divided into local layouts;

[0050] Figure 8 is a schematic diagram based on layout expansion provided by the present invention;

[0051] Figure 9 、 Figure 10 shows the scenarios that cannot be processed in the local layout;

[0052] Figure 11 shows the scenarios of data exceeding the adjacent local layout;

[0053] Figure 12 It is a schematic diagram of the search range in the inner pitch check provided by the present invention;

[0054] Figure 13 It shows the clipping operation on the edge pairs that meet the conditions;

[0055] Figure 14 It is the storage structure of the R-tree in the two-dimensional plane provided by the present invention;

[0056] Figure 15 It is a schematic diagram of the connection lines when the polygon is output provided by the present invention;

[0057] Figure 16 It is a schematic diagram of the clipping range and search range of the precise clipping provided by the present invention. Detailed implementation manners

[0058] The following will be described in detail with reference to the accompanying drawings.

[0059] The present invention discloses a method for inner pitch check in a large-scale integrated circuit layout. This method realizes efficient and accurate inner pitch check through technical means such as modular design, multi-threaded concurrent processing, local layout expansion, and the application of spatial indexing technologies such as the R-tree algorithm. Preferably, when performing rule checks on the integrated circuit layout data GDS, if there is an inner pitch check in the check rules, the method of the present invention can be used for processing. Figure 1 It shows a schematic diagram of the design rule check process of the integrated circuit layout. Among them, the method for inner pitch check of the present invention is at Figure 1 The position corresponding to "rule verification".

[0060] Before starting to implement the method for inner pitch check of the large-scale integrated circuit layout proposed by the present invention, a series of preparatory work needs to be completed to ensure the smooth progress of the subsequent steps. First, compile the rule check file. This process involves converting various constraint conditions in the design rule manual into a computer-readable form and constructing a rule check tree. The rule check tree not only contains all relevant check rules but also defines the hierarchical structure and logical relationship between these rules, thus providing a basic framework for subsequent automatic checks. For example, in the scenario of inner pitch check, the rules may include requirements for checking the minimum distance between two polygons or whether the distance between one layer and another layer meets specific standards. By compiling the rule check file, a complete set of rule sets that can be understood and executed by the software system can be generated.

[0061] Next, it is necessary to read in the data of the integrated circuit layout. Supporting the GDSII format is one of the current industry standards, which allows importing design data from different sources, ensuring compatibility and universality. After reading in the layout data, the system will automatically generate a cell call topology diagram. This topology diagram depicts the various components in the circuit design and their interconnections, and is the basis for understanding the entire circuit layout. It not only shows the position information of each component, but also reflects the electrical connection relationships between them, which is crucial for correctly performing design rule checking (DRC). For example, knowing which components are directly connected can help the filter accurately determine whether additional checks are required for certain edges. For instance, the connectivity filter needs to rely on such information to decide whether to measure the spacing between two edges.

[0062] Finally, after the above preparations are completed, the system will traverse the rule check tree to comprehensively check the layout data for rules. During this process, once a task involving inner spacing check is encountered, the method proposed in the present invention will be enabled for processing. This means that the system not only has to identify which parts need to be checked for inner spacing, but also needs to select appropriate algorithms and technical means according to specific rule requirements to perform the check. For example, for small rectangular areas with a width less than 2 nanometers, the system needs to pay special attention to the checks near their edges, because these places are prone to non-compliance with design specifications. By adopting techniques such as local layout partitioning, expansion, and R-tree search, potential problem points can be efficiently located and verified, ensuring that the final output results are both comprehensive and accurate, thus effectively improving the quality and reliability of large-scale integrated circuit design.

[0063] Preferably, as Figure 2 and Figure 3 shown, the method of the present invention may include the following steps:

[0064] S1. Divide the integrated circuit layout to be processed into several local layouts according to preset partitioning rules, including original local layouts and interfering local layouts. Among them, an interfering local layout is: among the local layouts obtained by partitioning, those local layouts where the data on the edge constituting the preset partitioning rule of the corresponding local layout interferes with the adjacent layout; expand the edges determined by the preset partitioning rule of these interfering local layouts outward in a manner depending on the currently selected preset check rule, based on the upper limit of the constraint conditions corresponding to the selected preset check rule, to obtain expanded local layouts;

[0065] S2. For all local layouts including expanded local layouts and original local layouts, check whether the edges of all functional components within all local layouts meet the upper limit of the constraint conditions corresponding to the currently selected preset check rule one by one, to screen out the edges that meet the potential conditions;

[0066] S3. Combine the edges that appear pairwise among these edges meeting the potential conditions into associated edge pairs, and screen these associated edge pairs through one or more filters with different filter types to obtain the associated edge pairs that meet the filtering conditions;

[0067] S4. Perform secondary clipping on these associated edge pairs according to the clipping ranges of each associated edge pair that meets the filtering conditions to obtain a set of clipped edge clusters that directly or indirectly form a negative result of the inner pitch check.

[0068] Preferably, step S1 lays the foundation for subsequent efficient parallel processing. Specifically, in order to ensure that the partitioning scheme can make full use of computing resources and guarantee the accuracy of the inspection, it is necessary to comprehensively consider the circuit complexity and available physical resources (such as the number of CPU cores, memory capacity, etc.) to determine the optimal local layout size. For example, when processing complex very large scale integrated circuits, overly fragmented partitioning may lead to an increase in task scheduling overhead; while overly large partitioning may not be able to fully utilize the advantages of multi-threaded concurrency and affect the overall efficiency.

[0069] To ensure the rationality of local layout partitioning, the actual size of the layout and the physical resources of the running machine are usually comprehensively considered. In addition, considering the complexity in practical applications, such as significant differences in design density in different regions, these factors also need to be considered when partitioning the local layout to ensure load balancing among individual local layouts. For example, in some high-density regions, the local layout may need to be more finely partitioned, while in low-density regions, the partitioning criteria can be appropriately relaxed to balance the workload of each part.

[0070] After the initial partitioning of the layout, considering the influence of boundary effects, several local layouts obtained by partitioning according to the preset partitioning rules can be divided into original local layouts and interfering local layouts. Since the data at the edges of local layouts often interferes with adjacent layouts and direct processing may lead to inaccurate results, these local layouts are the interfering local layouts. To overcome the challenges brought by boundary effects, that is, to ensure that the data at the edges can also be accurately included in the inspection scope, the present invention proposes a method of expanding the interfering local layouts according to the upper limit of the constraint conditions of their preset inspection rules, that is, expanding the edges of the interfering local layouts by a certain range according to the upper limit of the constraint conditions corresponding to the preset inspection rules, so as to ensure that the data at the edges can also be correctly included in the inspection scope, thereby improving the accuracy of the inspection results. As Figure 5 shown, Figure 5 (a) is the original layout, Figure 5 (b) is the partitioned layout, where, Figure 5 (b)'s black dotted line box is that the original layout is evenly divided into multiple smaller local layouts based on the set size, Figure 5(b)'s red dashed box is the extended partial layout to ensure the integrity of data near the edge. This extension strategy can not only solve the data inspection problem within the partial layout, but also effectively handle the data situation across the edges of multiple partial layouts, thus improving the comprehensiveness and accuracy of the inspection results. Exemplarily, as Figure 6 shown, there is a small rectangle in the layout ( Figure 6 the blue rectangle in), whose width is less than 2 nanometers. According to the preset inspection rules, it is necessary to check the data with an inner pitch less than 2 nanometers. Therefore, the distance between the two long sides of the rectangle meets the preset inspection rules and needs to be output. But if the layout is divided in the way of the Figure 6 black dashed box, the partial layout as shown in Figure 7 will be obtained, and the two long sides of the rectangle cannot be checked in the layout data of Figure 7 , that is, affected by the boundary effect. To solve this problem, it can be extended outward by 2 nanometers (the red dashed part as shown in Figure 8 ), and then by processing the layout of the red dashed part, the two long sides of the rectangle can be measured.

[0071] Furthermore, since there must be an upper limit for the constraint conditions of the preset inspection rules, when performing the extension, the extension size can be equal to the upper limit of the constraint conditions of the preset inspection rules. For example:

[0072] Inspection scenario Rule Expansion size Detect data smaller than 2 nm <2 2 nm Detect data smaller than 3 nm <3 3 nm Detect data greater than 2 nm and smaller than 3 nm >2<3 3 nm

[0073] In the process of integrated circuit layout design, for the situation where the partial layout edge involves adjacent layouts, the present invention adopts a specific extension method to ensure that all critical dimensions meet the preset design rules. This process can be summarized into the following steps:

[0074] 1. Select appropriate preset inspection rules: First, according to the design requirements or process requirements, select appropriate preset inspection rules. These rules define the specific constraint conditions to be followed at different pitches. For example, the rule of "checking data less than 3 nanometers" stipulates that if the distance between two lines is less than 3 nanometers, it needs to be corrected.

[0075] 2. Determine the extension amplitude of the outer boundary: Once the appropriate preset inspection rules are selected, next, the extension amplitude needs to be determined according to the upper limit of the constraint conditions corresponding to the rule. This step is to ensure that even when the minimum distance between lines reaches the upper limit of the constraint conditions, potential design conflicts can be avoided by extending the boundary. For example, if the selected rule is "checking data less than 3 nanometers", then the extension amplitude is 3 nanometers.

[0076] 3. Perform the expansion operation on the external boundary: Expand the external boundary of the partial layout outward according to the selected preset inspection rule and its corresponding expansion amplitude. This is done to ensure there is sufficient safety distance between the partial layout and adjacent layouts, thus avoiding potential degradation of electrical performance or other problems caused by too close physical distance.

[0077] Thus, the present invention specifically solves the problem of verifying the rationality of the expanded layout, which is conducive to a more detailed and comprehensive inspection of the expanded partial layout without dead ends, ensuring that all parts meet the design specifications and do not interfere with other adjacent layouts. This includes but is not limited to considerations such as electrical characteristics, thermal management, and signal integrity. Through this present invention, the problems related to adjacent layouts in the partial layout are effectively solved, ensuring the quality and reliability of the entire integrated circuit design. At the same time, this method also enables designers to more easily identify and correct those parts that do not meet the preset inspection rules, thereby improving the overall design efficiency.

[0078] In addition, by expanding the partial layout, most of the edge data can be effectively processed in independent threads, thereby improving the inspection efficiency. During the process of in-pitch inspection of a large-scale integrated circuit layout, in order to maximize the utilization of computing resources and accelerate the entire inspection process, the system first creates a thread pool. A thread pool is a design pattern that maintains a collection of pre-created and reusable worker threads, which can be assigned to execute different tasks. By using the thread pool, it becomes possible to concurrently perform the in-pitch inspection of the partial layout. Specifically, after the integrated circuit layout is divided into multiple partial layouts according to the set size, each partial layout is regarded as an independent task. Next, the system assigns these partial layouts to the available threads in the thread pool. Since each partial layout can be independently inspected for in-pitch, this assignment method allows multiple partial layouts to be processed simultaneously, thus significantly improving the processing speed and efficiency.

[0079] During the process of in-pitch inspection of a large-scale integrated circuit layout, how to quickly and accurately find the edge pairs that meet specific constraint conditions is a major difficulty in the inspection process. To solve this problem, the present invention adopts a solution based on the R-tree algorithm. This solution first constructs an R-tree to efficiently search for all potentially eligible (i.e., possibly meeting the constraint conditions) edges in each partial layout, and then only performs further filter checks on these potentially eligible edges, thereby greatly improving the efficiency of the entire inspection process.

[0080] Preferably, an R-tree is a tree-like data structure specifically used for storing and querying multi-dimensional spatial data (such as Figure 14As shown in Figure 1, it is particularly suitable for applications such as geographic information systems, database management systems, and real-time spatial data processing. In fact, the R-tree can be seen as an extended form of the B-tree in multidimensional space. It divides the functional components in the integrated circuit layout according to their ranges, and each node corresponds to a search range, thereby achieving efficient spatial query and data management functions. The "multidimensional spatial data" here refers to data types related to coordinates. For example, in the integrated circuit layout, these data may include the location information of components, the relative position relationship between layers, etc.

[0081] Specifically in the application scenario of internal spacing inspection, when it is necessary to filter edges according to certain constraints (such as finding edge pairs with a spacing less than 2 nanometers), the system will use the upper limit of the constraints in the search module to construct a search range (such as Figure 16 ). Preferably, the search range is constructed based on each side according to the constraints given in the design rules and the selected measurement method. These measurement methods can include various forms such as European measurement and rectangular measurement, such as Figure 12 As shown, Figure 12 (a) is European measurement, Figure 12 (b) is rectangular measurement. The characteristic of Euclidean measurement is that the edges are in the shape of a quarter arc, while rectangular measurement is a standard rectangular area. The choice between these two measurement methods depends on the specific application scenario and accuracy requirements. For example, when more accurate distance measurement is required, Euclidean measurement is preferred; while when higher processing speed or simplified calculation complexity is desired, rectangular measurement is preferred. Further preferably, for each edge of all functional components, the upper limit of the constraint condition is used to construct a search range based on these edges, wherein the search range can be a rectangular range. Figure 16 For example, if the requirement is to detect edge pairs with a spacing greater than 1 nanometer but less than 2 nanometers, a search range (i.e., the green rectangular area) will be constructed for the target edge based on this upper limit (i.e., 2 nanometers). All other edges that may meet the constraint conditions with the target edge must intersect with this search range (i.e., the green rectangular area). Next, through the R-tree algorithm, all edges that intersect with the search range can be quickly located and retrieved to obtain potentially eligible edges. This means that only more detailed filter checks are required for these potentially eligible edges in the future, which greatly reduces the amount of processing.

[0082] In the context of the application of integrated circuit layout, the functional components in the integrated circuit layout are organized into the hierarchical structure of an R-tree, where each node represents the minimum bounding shape that covers all child nodes within a certain area. This structure allows the system to quickly identify which edges may meet specific geometric constraints without having to check each edge one by one, greatly improving the search efficiency. In addition, for each edge to be checked, the system generates a corresponding search range according to its constraints (such as the green rectangular area mentioned above), and uses the R-tree to search for all other edges that may intersect with this edge, ensuring that only those edge pairs that are truly likely to meet the preset inspection rules will enter the next filter inspection stage, thus ensuring that the entire process is both efficient and accurate. This method not only significantly reduces unnecessary computational effort but also speeds up the internal pitch inspection, providing strong support for the design of large-scale integrated circuits.

[0083] Through the R-tree approach, the system can efficiently search for all edges that intersect with the search range constructed by the given constraints. This means that in subsequent operations, only these potentially eligible edge pairs need to be concerned with, greatly narrowing the processing scope and enhancing the efficiency. Specifically, after determining the search range representing the upper limit of the constraints, the R-tree algorithm identifies all edges that intersect with this search range because any edge that may meet the specific pitch requirement with the target edge must be located within or pass through this search range. This method based on spatial indexing avoids the need to compare all edges in the layout one by one, thus significantly reducing the computational effort.

[0084] Preferably, during the internal pitch inspection of large-scale integrated circuit layout, each filter is implemented in an independent filter type, and there is no dependency between filters. The main filters include the intersection filter, the direction filter, and the projection filter, etc., which are optimized for specific design rules respectively.

[0085] Specifically, by default, the intersection filter does not measure the internal pitch of intersecting edge pairs, but if there are special requirements in the design rules (such as considering the angle of intersecting edge pairs), this filter can be configured to meet these special needs. The direction filter is used to perform direction measurement on non-intersecting edge pairs and supports multiple setting options, such as measuring vertical edge pairs, edge pairs with acute or obtuse included angles, etc. The projection filter allows setting the projection length between two edges, and measurement is only carried out when the projection lengths of the two edges meet the preset conditions. Such a design enables the filters to flexibly handle various complex design rules.

[0086] To further improve the inspection efficiency, before applying these filters, the system will determine which filters need to be activated according to specific preset inspection rules. For example, if the preset inspection rules clearly require measuring intersecting edge pairs, the corresponding intersection filter will be activated. Although the selection of filters is based on preset inspection rules, the calling order of filters is determined in the software implementation and is not directly affected by the preset inspection rules. To maximize the inspection efficiency, the calling order of filters follows a basic principle: prioritize the filters that take less time and can exclude a large number of associated edge pairs that do not meet the conditions. This means that filters with a high filtering probability will be arranged to be executed first, in order to identify as early as possible the associated edge pairs that do not meet the preset inspection rules, thus avoiding unnecessary subsequent calculations, reducing resource consumption and accelerating the overall processing speed.

[0087] Once a filter determines that an associated edge pair does not meet the filtering conditions, the system immediately stops further inspection of that associated edge pair. Since there is no priority among different filters and all filters are treated equally, their execution order is entirely based on considerations of efficiency and filtering probability.

[0088] After the filter screening process is completed, the associated edge pairs that meet the filtering conditions will enter the clipping module for secondary clipping. This stage aims to select an appropriate measurement method according to the preset design rules and determine the final effective part, so as to ensure that the inner pitch inspection is both accurate and efficient. The clipping module, as a key step in the entire inspection process, performs precise clipping operations based on the search range and specific measurement methods.

[0089] In the search module, in order to ensure that all edges that may meet the conditions can be found, a search range composed of constraint upper limits is usually used for rough search. Although this approach can cover as many potentially eligible edges as possible, the result is often a relatively broad search range. Therefore, different from the relatively broad search range delimited by the search module, in the clipping module, more precise clipping operations need to be further carried out according to the specific clipping range. The difference between the clipping range of the clipping module and the search range of the search module is as Figure 16 shown. The clipping range of the clipping module is constructed based on the upper and lower limits of the constraint conditions corresponding to the preset inspection rules.

[0090] The working principle of the clipping module is to perform mutual clipping on the associated edge pairs that meet the filtering conditions, that is, from the perspective of each edge, precisely clip out the part of the other edge within its inspection range (as Figure 13As shown. In other words, "secondary clipping" means intercepting the part of the first edge in the pair of associated edges within the clipping range constructed based on the other edge (the second edge), and intercepting the part of the second edge in the pair of associated edges within the clipping range constructed based on the first edge. The intercepted parts of each pair of associated edges can form a set of edge clusters, and the edge clusters are all or part of the data of the associated edge pairs that meet the filtering conditions. In this way, the clipping module can effectively identify the actual valid distance parts between each pair of edges, ensuring that this data conforms to the initially set design rules.

[0091] The result obtained after being processed by the clipping module is several groups of edge clusters after secondary clipping, which represent the valid parts between the edge pairs that truly meet the design rules, and they form the edge cluster set. Throughout the process, the clipping module works closely with the previous search and filtering steps, jointly constituting a complete and efficient in-pitch inspection system for integrated circuit layouts.

[0092] During the actual operation process, there are still some data situations that cannot be accurately processed in a single thread. For example, as Figure 9 and Figure 10 shown, the red dashed box represents a specific local layout, which contains some edges, and the intersection relationships between these edges cannot be determined only by the data of this local layout. Suppose it is necessary to check non-intersecting edge pairs with a pitch less than 2 nanometers, and in this specific local layout, there are no edge pairs that meet this condition. However, if the overall perspective is lacking, that is, without a unified review of the entire design, it may lead to incorrect result output. For example, in the scenario of Figure 9 , it is necessary to check non-intersecting edge pairs with a distance less than 2 nanometers. In fact, there are no edge pairs in the layout that meet the constraint conditions and should not be output. But if there is no global processing step and only the layout data within the red dashed box is relied on for judgment, it may wrongly output the result, resulting in incorrect inspection results. Therefore, this scenario requires recording the edge information during thread processing and finally performing global processing.

[0093] To overcome this problem, the present invention proposes an effective solution, that is, recording all the information that may need further verification during the thread processing stage, and then performing a global processing after all local layouts are processed. The main purpose of global processing is to solve the data problems that cannot be correctly judged in a single local layout, which has nothing to do with the specific preset inspection rules. Exemplarily, when two edges simultaneously meet the following two conditions, global processing is required: First, these two edges must be non-parallel, because two parallel edges will definitely not intersect, so there will be no misjudgment in the local layout; Second, both of these two edges must exceed the range of the currently processed local layout, which includes two situations. One is that both edges are completely outside the currently processed local layout, as Figure 9The situation shown by the red part of the layout. Another case is that although these two sides do not completely exceed the scope of the current local layout, a part of them exceeds the scope of the adjacent local layout. This situation can be seen in the example in Figure 11 After summarizing and re-evaluating the data of these special cases, it can be ensured that the final inspection results are both accurate and comprehensive, avoiding misjudgments caused by insufficient information or one-sided understanding.

[0094] Preferably, after completing the inner-spacing inspection of all local layouts, if it is found that there is data that needs further global processing, it enters the global processing stage. The goal of this stage is to re-evaluate and confirm the pairs of edges that cannot be accurately judged whether they meet the design rules in a single local layout. Specifically, when two or more edges exceed the scope of the currently processed local layout, and their relationship (such as intersection or proximity) cannot be determined only by local data, the information of these edges needs to be summarized for comprehensive analysis. First, the system collects all data related to such special cases to ensure that every pair of edges that may affect the final result is recorded. Next, for all pairs of edges obtained by summarization, the system uses the same inspection method as the local layout to perform inner-spacing inspection. In this way, it can be ensured that all pairs of edges follow the same design rules and inspection standards at both the local and global levels.

[0095] Preferably, after all local layouts are processed, the results can be summarized and output to complete the entire inner-spacing inspection process. The goal of this stage is to generate accurate and easy-to-understand output results according to predefined rules, so that designers can quickly identify the parts that do not meet the design specifications and make necessary adjustments and optimizations accordingly.

[0096] Preferably, based on the results obtained by the cropping module, the system will generate corresponding output results according to specific preset inspection rules. These output results can have various forms. For example, edge output, polygon output, error-oriented output, etc., to adapt to different requirements and application scenarios.

[0097] When the preset inspection rules are set to output all edges that meet or do not meet the conditions in a certain layer, what the system outputs is the edge. This output method is particularly useful for cases where it is necessary to further analyze which edges on a specific layer meet or do not meet the design standards.

[0098] In the "polygon output" mode, the system will connect a pair of qualified edges into a polygon according to the preset inspection rules and output the polygon. During the process of constructing the polygon, it must be ensured that there is no intersection between the two connecting lines (as shown in Figure 15 ) to avoid geometric errors.

[0099] The default output method of "error-oriented output" focuses on outputting the trimmed edge clusters of edge pairs that meet the conditions. This method is mainly used to identify areas with potential problems and is usually presented to the user as the final result. In this way, designers can directly locate specific positions in the layout and understand which parts fail to meet the expected design requirements.

[0100] Whether it is the output of polygons or edges, they can serve as the basis for further inspection, helping designers analyze the problems existing in the circuit layout more deeply. However, "error-oriented output" is usually only used to display the final inspection results because it mainly focuses on the discovered problem points and is not suitable for further complex analysis. Finally, to ensure that all local layout data is correctly integrated, the system merges connected edges, polygons, and edge clusters to form a complete result set. If it is an operation generated at the intermediate layer, the result is temporarily stored in the intermediate layer; for inspection operations, the final result is exported to the result file specified by the rule file for subsequent review and reference. This entire process ensures the comprehensiveness and accuracy of the internal pitch inspection of large-scale integrated circuit layouts, providing a solid technical guarantee for high-quality chip manufacturing.

[0101] It should be noted that the above specific embodiments are exemplary. Those skilled in the art can come up with various solutions inspired by the disclosure of the present invention, and these solutions also fall within the scope of the disclosure of the present invention and within the protection scope of the present invention. Those skilled in the art should understand that the specification and drawings of the present invention are illustrative and do not constitute a limitation on the claims. The protection scope of the present invention is defined by the claims and their equivalents. The specification of the present invention contains multiple inventive concepts. Phrases such as "preferably" or "according to a preferred embodiment" indicate that the corresponding paragraphs disclose an independent concept. The applicant reserves the right to file divisional applications based on each inventive concept. Throughout the text, the features guided by "preferably" are only optional and should not be construed as mandatory. Therefore, the applicant reserves the right to waive or delete relevant preferred features at any time.

Claims

1. A method for checking spacing within a large-scale integrated circuit layout, characterized in that: It includes: S1. Divide the integrated circuit layout to be processed into a plurality of local layouts according to a preset division rule, which includes an original local layout and an interference local layout, wherein the interference local layout is: in the local layout obtained by division, data on the edge of the preset division rule of the corresponding local layout interferes with the adjacent layout; in a manner depending on the currently selected preset check rule, the edges of these interference local layouts determined by the preset division rule are expanded outward based on the upper limit of the constraint condition corresponding to the corresponding selected preset check rule to obtain an extended local layout; S2. For all local layouts including the extended local layout and the original local layout, check whether the edges of all functional components in all local layouts meet the upper limit of the constraint condition corresponding to the corresponding selected preset inspection rule one by one according to the currently selected preset inspection rule, so as to screen out the edges that meet the potential conditions; S3. The edges that appear in pairs among the edges that meet the potential conditions are combined into associated edge pairs, and the associated edge pairs are filtered by one or more filters with different filtering types to obtain associated edge pairs that meet the filtering conditions; S4. Perform secondary trimming on the associated edge pairs that meet the filtering conditions according to their trimming ranges, so as to obtain a set of trimmed edge clusters that serve as or indirectly form a negative result of the inner spacing check.

2. The method according to claim 1, characterized in that When performing local layout division according to preset division rules, the optimal local layout size is determined based on circuit complexity and physical resources, and the degree of division of the local layout can be adjusted based on the differences in design density in different areas to ensure load balance between local layouts.

3. The method according to claim 1 or 2, characterized in that: For all local layouts including the extended local layout and the original local layout, each local layout obtained by division is allocated to an available thread in a pre-created and reusable thread pool to concurrently execute the internal spacing check of the local layout.

4. The method according to any one of claims 1 to 3, characterized in that: The rule for determining edges that meet potential conditions is: if there is a situation in which the edge spacing in the corresponding inspected local layout is less than the upper limit of the constraint condition corresponding to the corresponding selected preset inspection rule, then the corresponding edge of the corresponding functional component of the corresponding inspected local layout will be preliminarily determined as an "edge that meets potential conditions".

5. The method according to any one of claims 1 to 4, characterized in that: "The situation where the edge spacing is less than the upper limit of the constraint corresponding to the corresponding selected preset inspection rule" is determined as follows: for each edge of all functional components, the upper limit of the constraint is used to construct a search range based on these edges respectively, and then all edges that intersect with the search range are located and retrieved through the R-tree algorithm.

6. The method according to any one of claims 1 to 5, characterized in that: All edges intersecting a search range constructed using a constraint upper bound for any target edge can be associated with the target edge, wherein a shape outline of the search range is determined based on a measurement method including a Euclidean measurement and a rectangular measurement.

7. The method according to any one of claims 1 to 6, characterized in that: The filters used in the filter checking phase are implemented independently in their respective filter types and have no dependencies on each other. The calling order of the filters sorted by their efficiency and filtering probability follows the following principle: prioritize filters that take relatively less time and filter relatively more.

8. The method according to any one of claims 1 to 7, characterized in that: When performing secondary trimming on any associated edge pair, the portion of the first edge in the associated edge pair within the trimming range constructed based on the second edge is intercepted, and the portion of the second edge of the associated edge pair within the trimming range constructed based on the first edge is intercepted. The intercepted portions of each pair of associated edge pairs form a group of edge clusters, where an edge cluster is all or part of the data of the associated edge pairs that meet the filtering conditions.

9. The method according to any one of claims 1 to 8, characterized in that: After completing the internal spacing check of all local layouts, if data that needs further global processing is found, the global processing stage is entered. The judgment conditions for global processing include: two or more edges that exceed the scope of the local layout currently being processed, and the relationship between them cannot be determined only by local data.

10. The method according to any one of claims 1 to 9, characterized in that: After the edge pairs are obtained through precise clipping, the corresponding output results are generated according to specific rules. The output results include edge output, polygon output, error-guided output and other forms. Among them, the connected edges, polygons and edge clusters are merged to form a complete result set.

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