Phase interpolator controlled by digital signal

Abstract

The invention discloses a digital signal controlled phase interpolator, which comprises a digital control module, a phase rotator, a mirror image phase rotator and a clock selection module, and is characterized in that the digital control module receives a phase discrimination result from a phase discriminator and obtains a control signal, and the phase discrimination result comprises a high-level Early signal and a low-level Late signal; the phase rotator receives the four-phase orthogonal clock signal and generates a first clock signal with a fixed phase according to the control signal, and the mirror image phase rotator receives the four-phase orthogonal clock signal and generates a second clock signal with a fixed phase according to the control signal; the clock selection module selectively outputs the first clock signal or the second clock signal. The digital control module is adopted to control the phase interpolator, the octagonal phase rotator is adopted to realize high linearity of phase interpolation, and the mirror image phase rotator is adopted to effectively eliminate clock jitter generated during conversion of a phase interpolation quadrant.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a phase interpolator controlled by a digital signal. Background Art

[0002] In recent years, with the rapid development of global cloud computing, Internet, and 5G communication technologies, higher-quality and higher-rate interface SerDes technologies are required. The SerDes technology mainly consists of three parts: a transmitter, a receiver, and clock generation. The SerDes technology usually operates asynchronously between the transmitter and the receiver. Therefore, the receiving end must have a clock and data recovery (CDR) circuit to extract the clock signal from the received data. In addition, the received data must also be re-timed and latched using the recovered clock.

[0003] A phase interpolator (PI) plays an important role in CDR. The phase interpolator changes the clock phase according to the result of a phase detector (PD), and then uses these clock signals to sample the received data, and identifies the phase of the sampled data through the phase detector to perform a PD-PI loop. Finally, the clock is sampled at the best sampling point in the middle of the data, and finally the clock and data recovery are realized.

[0004] In a traditional phase interpolator, the phase capture range is limited, the phase interpolation linearity is average, and large jitter occurs during quadrant transformation in phase synthesis. The performance of the phase interpolator affects the effect of CDR and even causes the bit error rate not to meet the requirements. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a phase interpolator controlled by a digital signal. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a phase interpolator controlled by a digital signal, including a digital control module, a phase rotator, a mirror phase rotator, and a clock selection module, wherein,

[0007] The digital control module receives the phase detection result from the phase detector, and respectively obtains control signals for the phase rotator, the mirror phase rotator, and the clock selection module. Among them, the phase detection result includes an Early signal and a Late signal, the Early signal is at a high level, and the Late signal is at a low level;

[0008] The phase rotator is used to receive a four-phase quadrature clock signal and generate a first clock signal with a fixed phase according to a control signal from the digital control module.

[0009] The mirror image phase rotator is used to receive a four-phase quadrature clock signal and generate a second clock signal with a fixed phase according to a control signal from the digital control module.

[0010] The clock selection module is used to selectively output the first clock signal or the second clock signal under the control of the digital control module.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0012] The present invention designs a CMOS integrated phase interpolator with a mirror image phase rotator controlled by a digital signal. The digital control module is used to control the phase interpolator. The digital control module can achieve high linearity of phase interpolation and has an unlimited phase capture range. The integrated phase interpolator architecture is adopted, and an octagonal phase rotator is used, which has higher phase interpolation linearity and improves integral nonlinearity (INL) and differential nonlinearity (DNL); the CMOS phase interpolator is adopted, and phase interpolation is realized by turning on and off a three-state inverter, providing better power / area efficiency; the mirror image phase rotator can effectively eliminate the clock jitter generated when the phase interpolation quadrant is transformed, eliminates the jitter at the cost of a small area and low power consumption, avoids the error code of the CDR, and improves the interpolation linearity.

[0013] The following will further describe the present invention in detail with reference to the accompanying drawings and embodiments. Description of the Drawings

[0014] Figure 1 is a schematic diagram of the basic principle of phase interpolation provided by an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of the module of a phase interpolator controlled by a digital signal provided by an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram of the structure of a digital control module provided by an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of the principle of an octagonal phase rotator provided by an embodiment of the present invention;

[0018] Figure 5 is a schematic diagram of the circuit structure of a phase rotator provided by an embodiment of the present invention;

[0019] Figure 6It is a schematic structural diagram of a first parallel three-state inverter unit provided by an embodiment of the present invention;

[0020] Figure 7 It is a schematic diagram of abnormal two-way clocks when a quadrant changes provided by an embodiment of the present invention;

[0021] Figure 8 It is a schematic diagram of the introduction of a mirror phase rotator provided by an embodiment of the present invention;

[0022] Figure 9 It is a schematic diagram of the principle of a mirror phase rotator provided by an embodiment of the present invention;

[0023] Figure 10 It is a schematic circuit structure diagram of a clock selection module provided by an embodiment of the present invention. Detailed implementation manners

[0024] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in combination with the accompanying drawings and specific implementation manners, details a phase interpolator controlled by a digital signal according to the present invention.

[0025] The foregoing and other technical contents, features, and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific implementation manners, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.

[0026] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant is intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the article or device including the said element.

[0027] Please refer to Figure 1 , Figure 1 It is a schematic diagram of the basic principle of phase interpolation provided by an embodiment of the present invention. The basic principle of phase interpolation is based on interpolation weight coefficients K A and K B to generate a new phase between two known phases. As Figure 1 shown, according to the weight coefficient KA and K B , composed of two orthogonal clocks CLK A and CLK B to synthesize a new-phase clock CLK PI .

[0028] Please refer to Figure 2 , Figure 2 which is a schematic diagram of a module of a phase interpolator with a mirror phase rotator controlled by a digital signal provided by an embodiment of the present invention. The phase interpolator includes a digital control module, a phase rotator, a mirror phase rotator, and a clock selection module. Among them, the digital control module receives the phase discrimination result from the phase discriminator and respectively obtains the control signals for the phase rotator, the mirror phase rotator, and the clock selection module. Among them, the phase discrimination result includes an Early signal and a Late signal, the Early signal is at a high level, and the Late signal is at a low level; the phase rotator is used to receive the control signal from the digital control module and generate a first clock signal with a fixed phase under the control of the control signal, and the mirror phase rotator is used to receive the control signal from the digital control module and generate a second clock signal with a fixed phase under the control of the control signal; the clock selection module is used to selectively output the first clock signal or the second clock signal under the control of the digital control module.

[0029] It should be noted that a phase discriminator is connected to the front end of the digital control module, and the phase discrimination result output by the phase discriminator is the positional relationship of the sampling clock with respect to the ideal sampling point. That is, when the sampling clock is ahead of the ideal sampling point, the phase discrimination result is the Early signal, and when the sampling clock lags behind the ideal sampling point, the phase discrimination result is the Late signal. In addition, in this embodiment, a clock with a fixed frequency is generated by a phase-locked loop, and a four-phase orthogonal clock signal is generated through a four-phase clock generation circuit, including a Phase0 clock signal, a Phase90 clock signal, a Phase180 clock signal, and a Phase270 clock signal, and this four-phase orthogonal clock is input to the phase rotator and the mirror phase rotator.

[0030] Specifically, please refer to Figure 3 , Figure 3It is a schematic structural diagram of a digital control module provided by an embodiment of the present invention. The digital control module includes an accumulator and a decoder, which are implemented by Verilog code. The phase interpolator in this embodiment divides the 360° phase within one period into 64 parts, with an ideal resolution of 5.625°, and uses a 6-bit accumulator to implement the encoding of 64 phases. In this embodiment, the accumulator result is set as S[5:0] (indicating that the S signal has 6-bit data, namely S[5], S[4], S[3], S[2], S[1], S[0]), which corresponds to 64 values (decimal values). The 64 values correspond to 64 phase intervals, and the degree of each phase interval is 5.625°. When the phase discrimination result is Early, the input of the accumulator is at a high level, and the value corresponding to the accumulator result S[5:0] is incremented by 1, and the clock phase generated by the subsequent phase rotator moves backward by 5.625°; when the phase discrimination result is Late, the input of the accumulator is at a low level, and the value corresponding to the accumulator result S[5:0] is decremented by 1, and the clock phase generated by the phase rotator moves forward by 5.625°. Exemplarily, assume that the current accumulator result S[5:0] is 000001, and the corresponding decimal value is 1; when the phase discrimination result is an Early signal, the input of the accumulator is at a high level, and the decimal value corresponding to the accumulator result S[5:0] is incremented by 1, becoming 000010, and the corresponding decimal value is 2. Assume that the current accumulator result S[5:0] is 000001. When the phase discrimination result is a Late signal, the input of the accumulator is at a low level, and the decimal value corresponding to the accumulator result S[5:0] is decremented by 1, becoming 000000, and the corresponding decimal value is 0.

[0031] The normal operation of the accumulator also requires a reset signal and a reference clock. Among them, the reset signal resets the accumulator. When it is at a low level, the accumulator does not work, and when it is at a high level, the accumulator starts to work, which is equivalent to a switch; the reference clock is at the rising edge of each clock. The accumulator identifies the phase discrimination result and then increments or decrements S[5:0] by 1.

[0032] Furthermore, the decoder is used to obtain the control signals of the phase rotator, the mirror phase rotator, and the clock selection module respectively according to the accumulator result.

[0033] First of all, it should be noted that the phase rotator of the present invention adopts an octagonal phase rotator. Its 64 phases correspond to the accumulator result S[5:0] of 6 bits. Its control signal is generated by the decoder, and the four-phase quadrature clock signal it needs is provided by a four-phase clock generation circuit. Please refer to Figure 4 , Figure 4It is a schematic diagram of the principle of the octagonal phase rotator provided by the embodiments of the present invention. The coordinate axes are the phases 0°, 90°, 180°, and 270° of the four-phase orthogonal clock signals. The phase rotator interpolates two orthogonal clocks controlled by the quadrant control codes Phase_ctrl_A and Phase_ctrl_B, that is, it controls the quadrant of the phase interpolation. The weight control codes SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0] control the weight coefficients K I and K Q , and by changing the above control signals, clocks with different phases can be generated. The new clock phase is between the phases of the two-phase orthogonal clocks. The relationship between SIQ_P[7:0] and SIQ_N[7:0] is the opposite of each other, that is:

[0034]

[0035] That is, when SIQ_P[7:0] = 11111111, SIQ_N[7:0] = 00000000.

[0036] The decoder is used to obtain the quadrant control codes Phase_ctrl_A and Phase_ctrl_B of the phase rotator according to the accumulator result. Specifically, the decoder takes the highest two bits S[5:4] of the accumulator result as the quadrant control codes Phase_ctrl_A and Phase_ctrl_B. The change of the quadrant control codes with the increase of S[5:0] is as follows:

[0037] When the decimal value corresponding to the accumulator result S[5:0] is 0 to 15, Phase_ctrl_A = 0, Phase_ctrl_B = 0; when the decimal value corresponding to the accumulator result S[5:0] is 16 to 31, Phase_ctrl_A = 0, Phase_ctrl_B = 1; when the decimal value corresponding to the accumulator result S[5:0] is 32 to 47, Phase_ctrl_A = 1, Phase_ctrl_B = 0; when the decimal value corresponding to the accumulator result S[5:0] is 48 to 63, Phase_ctrl_A = 1, Phase_ctrl_B = 1.

[0038] The decoder obtains the weight control codes SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0] of the phase rotator according to the lowest four bits S[3:0] in the accumulator result S[5:0]. The change is as follows:

[0039] When the decimal value corresponding to the lowest four bits S[3:0] is 0, SI[3:0] = 1111, SQ[3:0] = 0000, SIQ_P[7:0] = 11111111, SIQ_N[7:0] = 00000000.

[0040] When the decimal value corresponding to the lowest four bits S[3:0] is 1 to 4, SI[3:0] = 1111, SIQ_P[7:0] = 11111111, SIQ_N[7:0] = 00000000. When the decimal value corresponding to the lowest four bits S[3:0] changes from 1 to 4, the 4-bit value of SQ[3:0] changes from the lowest bit to the highest bit from 0 to 1 successively. Specifically, when the decimal value corresponding to the lowest four bits S[3:0] is 1, that is, the lowest four bits S[3:0] = 0001, then SQ[3:0] = 0001; when the decimal value corresponding to the lowest four bits S[3:0] is 2, that is, the lowest four bits S[3:0] = 0010, then SQ[3:0] = 0011; when the decimal value corresponding to the lowest four bits S[3:0] is 3, that is, the lowest four bits S[3:0] = 0011, then SQ[3:0] = 0111; when the decimal value corresponding to the lowest four bits S[3:0] is 4, that is, the lowest four bits S[3:0] = 0100, then SQ[3:0] = 1111.

[0041] When the decimal value corresponding to the lowest four bits S[3:0] is 5 to 12, SI[3:0] = 1111, SQ[3:0] = 1111. When the decimal value corresponding to the lowest four bits S[3:0] changes from 5 to 12, the 8-bit value of SIQ_P[7:0] changes from the lowest bit to the highest bit from 1 to 0 successively, and the 8-bit value of SIQ_N[7:0] changes from the lowest bit to the highest bit from 0 to 1 successively.

[0042] Specifically, when the decimal value corresponding to the lowest four bits S[3:0] is 5, that is, the lowest four bits S[3:0] = 0101, then SIQ_P[7:0] = 11111110 and SIQ_N[7:0] = 00000001; when the decimal value corresponding to the lowest four bits S[3:0] is 6, that is, the lowest four bits S[3:0] = 0110, then SIQ_P[7:0] = 11111100 and SIQ_N[7:0] = 00000011; when the decimal value corresponding to the lowest four bits S[3:0] is 7, that is, the lowest four bits S[3:0] = 0111, then SIQ_P[7:0] = 11111000 and SIQ_N[7:0] = 00000111; when the decimal value corresponding to the lowest four bits S[3:0] is 8, that is, the lowest four bits S[3:0] = 1000, then SIQ_P[7:0] = 11110000 and SIQ_N[7:0] = 00001111; when the decimal value corresponding to the lowest four bits S[3:0] is 9, that is, the lowest four bits S[3:0] = 1001, then SIQ_P[7:0] = 11100000 and SIQ_N[7:0] = 00011111; when the decimal value corresponding to the lowest four bits S[3:0] is 10, that is, the lowest four bits S[3:0] = 1010, then SIQ_P[7:0] = 11000000 and SIQ_N[7:0] = 00111111; when the decimal value corresponding to the lowest four bits S[3:0] is 11, that is, the lowest four bits S[3:0] = 1011, then SIQ_P[7:0] = 10000000 and SIQ_N[7:0] = 01111111; when the decimal value corresponding to the lowest four bits S[3:0] is 12, that is, the lowest four bits S[3:0] = 1100, then SIQ_P[7:0] = 00000000 and SIQ_N[7:0] = 11111111.

[0043] When the decimal value corresponding to the lowest four bits S[3:0] is 13 - 15, SQ[3:0] = 1111, SIQ_P[7:0] = 00000000, SIQ_N[7:0] = 11111111. When the decimal value corresponding to the lowest four bits S[3:0] changes from 13 to 15, SI[3:0] changes from 1 to 0 successively from the low bit to the high bit.

[0044] Specifically, when the decimal value corresponding to the lowest four bits S[3:0] is 13, that is, the lowest four bits S[3:0] = 1101, then SI[3:0] = 1110; when the decimal value corresponding to the lowest four bits S[3:0] is 14, that is, the lowest four bits S[3:0] = 1110, then SI[3:0] = 1100; when the decimal value corresponding to the lowest four bits S[3:0] is 15, that is, the lowest four bits S[3:0] = 1111, then SI[3:0] = 1000.

[0045] Further, please refer to Figure 5 , Figure 5 which is a schematic circuit diagram of a phase rotator provided by an embodiment of the present invention. The phase rotator includes a multiplexer MUX1, a multiplexer MUX2, a multiplexer MUX3, a multiplexer MUX4, a multiplexer MUX5, a multiplexer MUX6, a buffer BUF1, a buffer BUF2, a capacitor C1, a capacitor C2, a first parallel three-state inverter unit, a second parallel three-state inverter unit, a high-pass amplifier, and a buffer BUF3. The first input terminal of the multiplexer MUX1 is used to input the Phase0 clock signal in the four-phase quadrature clock signal, the second input terminal of the multiplexer MUX1 is used to input the Phase180 clock signal in the four-phase quadrature clock signal, the first input terminal of the multiplexer MUX2 is used to input the Phase90 clock signal in the four-phase quadrature clock signal, the second input terminal of the multiplexer MUX2 is used to input the Phase270 clock signal in the four-phase quadrature clock signal, the first input terminal of the multiplexer MUX3 is used to input the Phase90 clock signal in the four-phase quadrature clock signal, the second input terminal of the multiplexer MUX3 is used to input the Phase270 clock signal in the four-phase quadrature clock signal, the first input terminal of the multiplexer MUX4 is used to input the Phase180 clock signal in the four-phase quadrature clock signal, and the second input terminal of the multiplexer MUX4 is used to input the Phase0 clock signal in the four-phase quadrature clock signal.

[0046] The control terminals of data selector MUX1, the control terminal of data selector MUX2, the control terminal of data selector MUX3, and the control terminal of data selector MUX4 all input the quadrant control code Phase_ctrl_A; the output terminals of data selector MUX1 and data selector MUX2 are respectively connected to two input terminals of data selector MUX5, the output terminals of data selector MUX3 and data selector MUX4 are respectively connected to two input terminals of data selector MUX6, and the control terminals of data selector MUX5 and data selector MUX6 both input the quadrant control code Phase_ctrl_B; the output terminal of data selector MUX5 is connected to the input terminal of buffer BUF1, the output terminal of data selector MUX6 is connected to the input terminal of buffer BUF12, and the output terminal of buffer BUF1 is connected to the input terminal of the first parallel three-state inverter unit; the output terminal of buffer BUF2 is connected to the input terminal of the second parallel three-state inverter unit; capacitor C1 is connected between the output terminal of buffer BUF1 and the ground terminal, and capacitor C2 is connected between the output terminal of buffer BUF2 and the ground terminal.

[0047] The input terminals of the high-pass amplifier are respectively connected to the output terminals of the first parallel three-state inverter unit and the second parallel three-state inverter unit, the input terminal of buffer BUF3 is connected to the output terminal of the high-pass amplifier, and the output terminal of buffer BUF3 as a phase rotator is connected to the clock selection module.

[0048] Furthermore, the first parallel three-state inverter unit and the second parallel three-state inverter unit in this embodiment have the same structure, both including a plurality of parallel three-state inverters, and the on / off of each three-state inverter in the first parallel three-state inverter unit is controlled by the weight control codes SI[3:0] and SIQ_P[7:0], and the on / off of each three-state inverter in the second parallel three-state inverter unit is controlled by the weight control codes SQ[3:0] and SIQ_N[7:0].

[0049] Please refer to Figure 6 , Figure 6It is a schematic structural diagram of a first parallel three-state inverter unit provided by an embodiment of the present invention. The first parallel three-state inverter unit includes a first three-state inverter, a second three-state inverter, a third three-state inverter, a fourth three-state inverter, a fifth three-state inverter, a sixth three-state inverter, a seventh three-state inverter, an eighth three-state inverter, a ninth three-state inverter, a tenth three-state inverter, an eleventh three-state inverter, and a twelfth three-state inverter connected in parallel. Among them, the first three-state inverter is controlled by the SI[0] bit in SI[3:0] and its opposite number SI[0]; the second three-state inverter is controlled by the SI[1] bit in SI[3:0] and its opposite number SI[1]; the third three-state inverter is controlled by the SI[2] bit in SI[3:0] and its opposite number SI[2]; the fourth three-state inverter is controlled by the SI[3] bit in SI[3:0] and its opposite number SI[3]; the fifth three-state inverter is controlled by the SIQ_P[0] bit in SIQ_P[7:0] and its opposite number SIQ_P[0]; the sixth three-state inverter is controlled by the SIQ_P[1] bit in SIQ_P[7:0] and its opposite number SIQ_P[1]; the seventh three-state inverter is controlled by the SIQ_P[2] bit in SIQ_P[7:0] and its opposite number SIQ_P[2]; the eighth three-state inverter is controlled by the SIQ_P[3] bit in SIQ_P[7:0] and its opposite number SIQ_P[3]; the ninth three-state inverter is controlled by the SIQ_P[4] bit in SIQ_P[7:0] and its opposite number SIQ_P[4]; the tenth three-state inverter is controlled by the SIQ_P[5] bit in SIQ_P[7:0] and its opposite number SIQ_P[5]; the eleventh three-state inverter is controlled by the SIQ_P[6] bit in SIQ_P[7:0] and its opposite number SIQ_P[6]; the twelfth three-state inverter is controlled by the SIQ_P[7] bit in SIQ_P[7:0] and its opposite number SIQ_P[7].

[0050] Similarly, the second parallel three-state inverter unit of this embodiment also includes twelve parallel three-state inverters. Each three-state inverter is sequentially controlled by the SQ[0] bit in SQ[3:0] and its opposite number, the SQ[1] bit in SQ[3:0] and its opposite number, the SQ[0] bit in SQ[3:2] and its opposite number, the SQ[0] bit in SQ[3:3] and its opposite number, the SIQ_N[0] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[1] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[2] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[3] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[4] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[5] bit in SIQ_N[7:0] and its opposite number, the SIQ_N[6] bit in SIQ_N[7:0] and its opposite number, AND the SIQ_N[7] bit in SIQ_N[7:0] and its opposite number.

[0051] Specifically, the phase rotator inputs a four-phase quadrature clock signal. Under the control of the quadrant control signals Phase_ctrl_A and Phase_ctrl_B, each data selector selects two-phase quadrature clock signals. After passing through the corresponding buffers and capacitors, the I and Q two-phase quadrature clock signals pass through their respective parallel three-state inverter units. The on / off states of the parallel three-state inverter units of the I and Q channels are controlled by the weight control codes SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0]. They are turned on when the input is high level and turned off when the input is low level, so as to change the weight coefficients of the two-phase quadrature clock signals. Then they are synthesized at the common node. The high-pass amplifier improves the duty cycle distortion of the synthesized clock signal by suppressing the DC bias and setting the operating point to the optimal value, generating a clock signal with an interpolated phase, and outputting it after passing through a buffer.

[0052] It should be noted that when the phase rotator switches quadrants, Phase_ctrl_A or Phase_ctrl_B will change, and the I and Q two-phase clocks for phase interpolation will have a 90° phase change, resulting in an abnormal period of the interpolated clock, causing clock jitter, affecting the linearity of the phase interpolator, and even causing bit errors in the CDR. Taking the switch from the first quadrant to the second quadrant as an example, at this time S[5:0] = 16, the clock selected by the I channel changes from Phase0 to Phase90, and the clock selected by the Q channel changes from Phase90 to Phase180. The interpolated clock will have an abnormal period as Figure 7 shown in the highlighted part.

[0053] To eliminate the clock jitter caused by quadrant changes, a mirror phase rotator is introduced, and the corresponding relationship of the control signals is as Figure 9As shown in the figure. The circuit of the mirror phase rotator is the same as that of the phase rotator, but the control codes are different. The quadrant control codes of the mirror phase rotator are Mirrorr_phase_ctrl_A and Mirrorr_phase_ctrl_B, and the weight control codes are Mirrorr_SI[3:0], Mirrorr_SQ[3;0], Mirrorr_SIQ_P[7:0], and Mirrorr_SIQ_N[7:0]. During phase interpolation, the control codes of the mirror phase rotator will be changed in advance to the nearest quadrant intersection. When the quadrant of the original phase rotator changes, the clock selection module will switch the clock generated by the phase rotator to the clock generated by the mirror phase rotator until the original phase rotator leaves the quadrant intersection.

[0054] Please refer to Figure 8 , Figure 8 which is a schematic diagram of the principle of a mirror phase rotator provided by an embodiment of the present invention. As Figure 8 shown, when the accumulator result S[5:0] changes from 57 to 63 or from 0 to 8, the mirror phase rotator outputs a clock with a phase of 0°; when the accumulator result S[5:0] changes from 9 to 24, the mirror phase rotator outputs a clock with a phase of 90°; when the accumulator result S[5:0] changes from 25 to 40, the mirror phase rotator outputs a clock with a phase of 180°; when the accumulator result S[5:0] changes from 41 to 56, the mirror phase rotator outputs a clock with a phase of 270°. The clock phase generated by the mirror phase rotator only changes among the four phases of 0°, 90°, 180°, and 270°, corresponding to the four regions divided by the dotted line in the schematic diagram.

[0055] The variation of the quadrant control codes with the increase of S[5:0] is as follows:

[0056] When the decimal value corresponding to the accumulator result S[5:0] is 57 - 63 and 0 - 8, Mirrorr_phase_ctrl_A = 0, Mirrorr_phase_ctrl_B = 0; when the decimal value corresponding to the accumulator result S[5:0] is 9 - 24, Mirrorr_phase_ctrl_A = 0, Mirrorr_phase_ctrl_B = 1; when the decimal value corresponding to the accumulator result S[5:0] is 25 - 40, Mirrorr_phase_ctrl_A = 1, Mirrorr_phase_ctrl_B = 0; when the decimal value corresponding to the accumulator result S[5:0] is 41 - 56, Mirrorr_phase_ctrl_A = 1, Mirrorr_phase_ctrl_B = 1.

[0057] The weight control code of the mirror phase rotator remains unchanged all the time, Mirrorr_SI[3:0]=1111, Mirrorr_SIQ_P[7:0]=11111111, Mirrorr_SQ[3:0]=0000, Mirrorr_SIQ_N[7:0]=00000000.

[0058] Subsequently, the first clock signal and the second clock signal generated by the phase rotator and the mirror phase rotator are input into the clock selection module. Generally, the clock selection module outputs the first clock signal generated by the phase rotator; when the phase interpolation quadrant of the phase rotator changes, that is, when S[5:0] is 0, 16, 32, or 48, the clock selection module will output the second clock signal generated by the mirror phase rotator. In this way, the phase interpolator will not generate a large clock jitter during the quadrant change. Please refer to Figure 10 , Figure 10 FIG. is a schematic circuit diagram of a clock selection module provided by an embodiment of the present invention. The clock selection module includes a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, and an NMOS transistor NM5. Among them, the source electrodes of the PMOS transistor PM1, the PMOS transistor PM3, and the PMOS transistor PM5 are all connected to the power supply terminal VDD, and the drain electrode of the PMOS transistor PM1 is connected to the source electrode of the PMOS transistor PM2; the drain electrode of the PMOS transistor PM2 is connected to the drain electrode of the NMOS transistor NM1, the drain electrode of the PMOS transistor PM4, the drain electrode of the NMOS transistor NM3, the gate electrode of the PMOS transistor PM5, and the gate electrode of the NMOS transistor NM5; the source electrode of the NMOS transistor NM1 is connected to the drain electrode of the NMOS transistor NM2, the source electrodes of the NMOS transistor NM2, the NMOS transistor NM5, and the NMOS transistor NM4 are all connected to the ground terminal GND; the drain electrode of the PMOS transistor PM3 is connected to the source electrode of the PMOS transistor PM4, and the source electrode of the NMOS transistor NM3 is connected to the drain electrode of the NMOS transistor NM4.

[0059] The gate electrodes of the PMOS transistor PM2 and the NMOS transistor NM3 both receive the clock signal CLK_ctrl from the digital control module, and the gate electrodes of the PMOS transistor PM4 and the NMOS transistor NM1 both receive the clock signal CLK_ctrl from the digital control module; the gate electrodes of the PMOS transistor PM1 and the NMOS transistor NM2 receive the first clock signal from the phase rotator, and the gate electrodes of the PMOS transistor PM3 and the NMOS transistor NM4 receive the second clock signal from the mirror phase rotator; the drain electrode of the PMOS transistor PM5 is connected to the drain electrode of the NMOS transistor NM5 and serves as the output of the clock selection module.

[0060] Further, the decoder of this embodiment is further configured to: obtain a clock signal CLK_ctrl according to the accumulator result S[5:0]. When the decimal value corresponding to the accumulator result S[5:0] is 0, 16, 32, or 48, CLK_ctrl = 0; when the decimal value corresponding to the accumulator result S[5:0] takes other values, CLK_ctrl = 1; the clock signal CLK_ctrl and the clock signal CLK_ctrl are opposite signals.

[0061] The phase interpolator of the present invention is composed of a digital control module, a phase rotator, a mirror phase rotator, and a clock selection module. The digital control module receives the phase detector results Early / Late and outputs control signals for the phase rotator, the mirror phase rotator, and the clock selection module respectively. The phase-locked loop generates a clock with a fixed frequency, and a quadrature clock is generated by a quadrature clock generation circuit and input to the phase rotator and the mirror phase rotator. Under the influence of the control signal, the phases of the input quadrature clock are rotated. The clocks with fixed phases generated by the phase rotator and the mirror phase rotator are input to the clock selection module. According to the control signal, the clock selection module selects the two clocks after phase transformation, and finally outputs a clock signal.

[0062] The present invention designs a CMOS integrated phase interpolator with a mirror phase rotator controlled by a digital signal. The digital control module is used to control the phase interpolator. The digital control module can achieve high linearity of phase interpolation and has an unrestricted phase capture range. The integrated phase interpolator architecture is adopted, and an octagonal phase rotator is used, which has higher phase interpolation linearity and improves the integral nonlinearity (INL) and differential nonlinearity (DNL); the CMOS phase interpolator is adopted, and the phase interpolation is realized by the on / off of the tri-state inverter, providing better power / area efficiency; the mirror phase rotator can effectively eliminate the clock jitter generated when the phase interpolation quadrant is transformed, eliminates the jitter at the cost of a small area and power consumption, avoids the bit error of the CDR, and improves the interpolation linearity.

[0063] In several embodiments provided by the present invention, it should be understood that the devices and methods disclosed by the present invention can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0064] In addition, in each embodiment of the present invention, each functional module can be integrated into one processing module, can exist physically alone for each module, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, or in the form of a combination of hardware and software functional modules.

[0065] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A phase interpolator controlled by a digital signal, characterized in that: It includes a digital control module, a phase rotator, a mirror phase rotator and a clock selection module, wherein: The digital control module receives the phase detection result of the phase detector, and obtains control signals for the phase rotator, the mirror phase rotator and the clock selection module respectively, wherein the phase detection result includes an Early signal and a Late signal, the Early signal is a high level, and the Late signal is a low level; The phase rotator is used to receive a four-phase orthogonal clock signal and generate a first clock signal with a fixed phase according to a control signal from the digital control module. The mirror phase rotator is used to receive a four-phase quadrature clock signal and generate a second clock signal with a fixed phase according to a control signal from the digital control module; The clock selection module is used to selectively output the first clock signal or the second clock signal under the control of the digital control module.

2. The digital signal controlled phase interpolator according to claim 1, characterized in that: The digital control module includes an accumulator and a decoder, wherein: The accumulator is a 6-bit accumulator, and is used to obtain an accumulation result S[5:0] according to the phase detection result Early / Late, wherein the accumulation result S[5:0] has 6-bit data, including 64 values, and the 64 values ​​correspond to 64 phase intervals, and the degree of each phase interval is 5.625°. When the phase detection result is an Early signal, the value corresponding to the accumulator result S[5:0] is increased by 1; when the phase detection result is a Late signal, the value corresponding to the accumulator result S[5:0] is reduced by 1; The decoder is used to obtain control signals of the phase rotator, the mirror phase rotator and the clock selection module respectively according to the accumulator result.

3. The digital signal controlled phase interpolator according to claim 2, characterized in that: The decoder is used for: Selecting the highest 2 bits of data corresponding to the accumulator result S[5:0] as quadrant control codes Phase_ctrl_A and Phase_ctrl_B of the phase rotator; The weight control codes SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0] of the phase rotator are obtained according to the lowest four bits S[3:0] in the accumulator result S[5:0]: When the decimal value corresponding to the lowest four bits S[3:0] is 0, SI[3:0]=1111, SQ[3:0]=0000, SIQ_P[7:0]=11111111, SIQ_N[7:0]=00000000; When the decimal value corresponding to the lowest four bits S[3:0] is 1-4, SI[3:0]=1111, SIQ_P[7:0]=11111111, SIQ_N[7:0]=00000000, when the decimal value corresponding to the lowest four bits S[3:0] changes from 1 to 4, the 4-bit value of SQ[3:0] changes from 0 to 1 from the lowest bit to the highest bit; When the decimal value corresponding to the lowest four bits S[3:0] is 5 to 12, SI[3:0]=1111, SQ[3:0]=1111. When the decimal value corresponding to the lowest four bits S[3:0] changes from 5 to 12, the 8-bit value of SIQ_P[7:0] changes from 1 to 0 from the lowest bit to the highest bit, and the 8-bit value of SIQ_N[7:0] changes from 0 to 1 from the lowest bit to the highest bit. When the decimal value corresponding to the lowest four bits S[3:0] is 13-15, SQ[3:0]=1111, SIQ_P[7:0]=00000000, SIQ_N[7:0]=11111111. When the decimal value corresponding to the lowest four bits S[3:0] changes from 13 to 15, SI[3:0] changes from 1 to 0 from the lowest bit to the highest bit.

4. The digital signal controlled phase interpolator according to claim 3, characterized in that: The phase rotator includes a data selector MUX1, a data selector MUX2, a data selector MUX3, a data selector MUX4, a data selector MUX5, a data selector MUX6, a buffer BUF1, a buffer BUF2, a capacitor C1, a capacitor C2, a first parallel three-state inverter unit, a second parallel three-state inverter unit, a high-pass amplifier and a buffer BUF3, wherein: The first input end of the data selector MUX1 is used to input the Phase0 clock signal in the four-phase orthogonal clock signal, the second input end of the data selector MUX1 is used to input the Phase180 clock signal in the four-phase orthogonal clock signal, the first input end of the data selector MUX2 is used to input the Phase90 clock signal in the four-phase orthogonal clock signal, the second input end of the data selector MUX2 is used to input the Phase270 clock signal in the four-phase orthogonal clock signal, the first input end of the data selector MUX3 is used to input the Phase90 clock signal in the four-phase orthogonal clock signal, the second input end of the data selector MUX3 is used to input the Phase270 clock signal in the four-phase orthogonal clock signal, the first input end of the data selector MUX4 is used to input the Phase180 clock signal in the four-phase orthogonal clock signal, and the second input end of the data selector MUX4 is used to input the Phase0 clock signal in the four-phase orthogonal clock signal; The control end of the data selector MUX1, the control end of the data selector MUX2, the control end of the data selector MUX3 and the control end of the data selector MUX4 all input the quadrant control code Phase_ctrl_A; the output end of the data selector MUX1 and the output end of the data selector MUX2 are respectively connected to the two input ends of the data selector MUX5, the output end of the data selector MUX3 and the output end of the data selector MUX4 are respectively connected to the two input ends of the data selector MUX6, and the control end of the data selector MUX5 and the control end of the data selector MUX6 all input the quadrant control code Phase_ctrl_B; The output end of the data selector MUX5 is connected to the input end of the buffer BUF1, the output end of the data selector MUX6 is connected to the input end of the buffer BUF2, the output end of the buffer BUF1 is connected to the input end of the first parallel three-state inverter unit; the output end of the buffer BUF2 is connected to the input end of the second parallel three-state inverter unit; the capacitor C1 is connected between the output end of the buffer BUF1 and the ground end, and the capacitor C2 is connected between the output end of the buffer BUF2 and the ground end; The input end of the high-pass amplifier is respectively connected to the output end of the first parallel three-state inverter unit and the output end of the second parallel three-state inverter unit, the input end of the buffer BUF3 is connected to the output end of the high-pass amplifier, and the buffer BUF3 is connected to the clock selection module as the output end of the phase rotator.

5. The digital signal controlled phase interpolator according to claim 4, characterized in that: The first parallel three-state inverter unit and the second parallel three-state inverter unit have the same structure, both including a plurality of parallel three-state inverters, and, The on-off of each tri-state inverter in the first parallel tri-state inverter unit is controlled by weight control codes SI[3:0] and SIQ_P[7:0], and the on-off of each tri-state inverter in the second parallel tri-state inverter unit is controlled by weight control codes SQ[3:0] and SIQ_N[7:0].

6. The digital signal controlled phase interpolator according to claim 4, characterized in that: The first parallel three-state inverter unit includes a first three-state inverter, a second three-state inverter, a third three-state inverter, a fourth three-state inverter, a fifth three-state inverter, a sixth three-state inverter, a seventh three-state inverter, an eighth three-state inverter, a ninth three-state inverter, a tenth three-state inverter, an eleventh three-state inverter and a twelfth three-state inverter connected in parallel, wherein: The first tri-state inverter is controlled by the SI[0] bit and its opposite SI[0] in SI[3:0], the second tri-state inverter is controlled by the SI[1] bit and its opposite SI[1] in SI[3:0], the third tri-state inverter is controlled by the SI[2] bit and its opposite SI[2] in SI[3:0], and the fourth tri-state inverter is controlled by the SI[3] bit and its opposite SI[3] in SI[3:0]; The fifth tri-state inverter is controlled by the SIQ_P[0] bit and its opposite SIQ_P[0] in SIQ_P[7:0], the sixth tri-state inverter is controlled by the SIQ_P[1] bit and its opposite SIQ_P[1] in SIQ_P[7:0], the seventh tri-state inverter is controlled by the SIQ_P[2] bit and its opposite SIQ_P[2] in SIQ_P[7:0], the eighth tri-state inverter is controlled by the SIQ_P[3] bit and its opposite SIQ_P[3] in SIQ_P[7:0], and the The ninth tri-state inverter is controlled by the SIQ_P[4] bit and its opposite SIQ_P[4] in SIQ_P[7:0], the thirteenth tri-state inverter is controlled by the SIQ_P[5] bit and its opposite SIQ_P[5] in SIQ_P[7:0], the eleventh tri-state inverter is controlled by the SIQ_P[6] bit and its opposite SIQ_P[6] in SIQ_P[7:0], and the twelfth tri-state inverter is controlled by the SIQ_P[7] bit and its opposite SIQ_P[7] in SIQ_P[7:0].

7. The digital signal controlled phase interpolator according to claim 2, characterized in that: The decoder is also used for: The quadrant control codes Mirrorr_phase_ctrl_A and Mirrorr_phase_ctrl_B of the mirror phase rotator are obtained according to the accumulator result S[5:0]: When the decimal value corresponding to the accumulator result S[5:0] is 57-63 and 0-8, Mirrorr_phase_ctrl_A=0, Mirrorr_phase_ctrl_B=0; When the decimal value corresponding to the accumulator result S[5:0] is 9 to 24, Mirrorr_phase_ctrl_A=0, Mirrorr_phase_ctrl_B=1; When the decimal value corresponding to the accumulator result S[5:0] is 25-40, Mirrorr_phase_ctrl_A=1, Mirrorr_phase_ctrl_B=0; When the decimal value corresponding to the accumulator result S[5:0] is 41-56, Mirrorr_phase_ctrl_A=1, Mirrorr_phase_ctrl_B=1; The weight control code of the mirror phase rotator is obtained: Mirrorr_SI[3:0]=1111, Mirrorr_SIQ_P[7:0]=11111111, Mirrorr_SQ[3:0]=0000, Mirrorr_SIQ_N[7:0]=00000000.

8. The digital signal controlled phase interpolator according to claim 1, characterized in that: The mirror phase rotator has the same circuit structure as the phase rotator.

9. The digital signal controlled phase interpolator according to any one of claims 2 to 8, characterized in that: The clock selection module includes a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4 and an NMOS tube NM5, wherein: The source of the PMOS tube PM1, the source of the PMOS tube PM3 and the source of the PMOS tube PM5 are all connected to the power supply terminal VDD, the drain of the PMOS tube PM1 is connected to the source of the PMOS tube PM2; the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM1, the drain of the PMOS tube PM4, the drain of the NMOS tube NM3, the gate of the PMOS tube PM5 and the gate of the NMOS tube NM5; The source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM2, and the source of the NMOS tube NM2, the source of the NMOS tube NM5 and the source of the NMOS tube NM4 are all connected to the ground terminal GND; The drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM4, and the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4; The gate of the PMOS tube PM2 and the NMOS tube NM3 both input the clock signal CLK_ctrl from the digital control module, and the gate of the PMOS tube PM4 and the NMOS tube NM1 both input the clock signal CLK_ctrl from the digital control module. The gate inputs of the PMOS transistor PM1 and the NMOS transistor NM2 are from the first clock signal of the phase rotator, and the gate inputs of the PMOS transistor PM3 and the NMOS transistor NM4 are from the second clock signal of the mirror phase rotator; The drain of the PMOS transistor PM5 is connected to the drain of the NMOS transistor NM5 and serves as the output of the clock selection module.

10. The digital signal controlled phase interpolator according to claim 2, characterized in that: The decoder is also used for: The clock signal CLK_ctrl is obtained according to the accumulator result S[5:0]. When the decimal value corresponding to the accumulator result S[5:0] is 0, 16, 32, or 48, CLK_ctrl=0. When the decimal value corresponding to the accumulator result S[5:0] is other values, CLK_ctrl=1. The clock signal CLK_ctrl and the clock signal is the opposite signal.

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