Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method of forming a semiconductor device includes forming a first transistor and a second transistor on a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of the first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on a backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. A backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same. Background Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, so that more components can be integrated into a given area. As the semiconductor industry further develops in the direction of increasing device density, improving performance, and reducing costs, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, which include complementary field effect transistors (CFETs). However, as the minimum component size decreases, additional features are introduced. Summary of the Invention

[0004] According to one aspect of embodiments of the present application, there is provided a semiconductor device, including: a plurality of first nanostructures extending between a first source / drain region; a plurality of second nanostructures located above the plurality of first nanostructures and extending between a second source / drain region; a first gate stack surrounding the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a backside gate etch stop layer (ESL) located on the backside of the first gate stack, wherein the backside gate ESL includes a metal; and a backside gate contact extending through the backside gate ESL and electrically coupled to the first gate stack.

[0005] According to another aspect of embodiments of the present application, there is provided a method of forming a semiconductor device, including: forming a first transistor and a second transistor above a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked; exposing the backside of a first gate stack of the first transistor, wherein exposing the backside of the first gate stack includes removing the semiconductor substrate; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening, wherein the backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

[0006] According to another aspect of an embodiment of the present application, a method of forming a semiconductor device is provided, including: forming a multi-layer stack above a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions above the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; replacing the pseudo-nanostructures with a lower gate stack surrounding the lower semiconductor nanostructures and an upper gate stack surrounding the upper semiconductor nanostructures; exposing a back side of the lower gate stack; depositing a metal-containing back side gate etch stop layer (ESL) on the back side of the lower gate stack; and forming a back side gate contact extending through the metal-containing back side gate ESL to electrically connect to the lower gate stack, wherein the back side gate contact overlaps with the lower semiconductor nanostructures and the upper semiconductor nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor in accordance with some embodiments is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11A and Figure 11B are views of intermediate stages of manufacturing a stacked transistor in accordance with some embodiments.

[0010] Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15 、 Figure 16 、 Figure 17A and Figure 17B are views of intermediate stages of manufacturing a stacked transistor in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0012] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relationship terms are intended to encompass different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0013] A stacked transistor (e.g., a CFET) and a method of forming the same are provided. In various embodiments, the stacked transistor includes two vertically stacked transistors, and a gate etch stop layer (ESL) is formed on the back side of the lower gate stack of the stacked transistor. The channel region of the stacked transistor may overlap with the gate ESL. In some embodiments, the gate ESL includes a metal such as cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum, their oxides, combinations thereof, etc. Including a back side gate ESL advantageously reduces the aspect ratio of the back side gate contact and reduces damage to the metal gate during the back side gate formation process. Additionally, by using a metal as the back side gate ESL, the contact resistance between the back side gate contact and the gate electrode can be advantageously reduced.

[0014] The back side gate ESL allows for the formation of a connection to the lower gate stack at a location where the back side gate contact overlaps with the channel region of the stacked transistor during the back side gate contact formation process without damaging the channel region. As a result, when forming the back side gate contact, there is no need to avoid the location of the channel region overlap, thereby allowing improved routing flexibility. Additionally, since the channel region can directly overlap with the back side gate contact, the channel region can be designed and fabricated to have a greater width to increase device speed. For example, by increasing the width of the channel region, a device speed improvement between 14.4% and 19% has been observed in example devices. As a result, various embodiments allow for improved process integration, increased routing flexibility, and increased device performance.

[0015] Figure 1 Shows an example of a stacked transistor 10 (including FETs (field effect transistors) 10U and 10L) according to some embodiments. Figure 1 Is a three-dimensional view, and for ease of illustration, some features of the stacked transistor are omitted.

[0016] The stacked transistor includes a plurality of vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), where the semiconductor nanostructure 26 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is for the upper nanostructure FET 10U. In other embodiments, the stacked transistor can also be applied to other types of transistors (e.g., finFETs, etc.).

[0017] The gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. The gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are above the gate dielectric 78. The source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are provided on opposite sides of the gate dielectric 78 and the corresponding gate electrodes 80. Each of the source / drain regions 62 can refer to the source or the drain individually or jointly, depending on the context. An isolation component (not shown) can be formed to separate the desired source / drain regions in the source / drain regions 62 and / or the desired gate electrodes in the gate electrodes 80.

[0018] Figure 1 Further illustrates the reference cross-sections used in the subsequent figures. The cross-section A-A' is a vertical cross-section that is parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and in the direction of current flow between, for example, the source / drain regions 62 of the stacked transistor 10. The cross-section B-B' is a vertical cross-section that is perpendicular to the cross-section A-A' and along the longitudinal axis of the gate electrode 80 of the stacked transistor 10.

[0019] Figures 2 to 11B Shows different views of an intermediate stage in the formation process of a stacked transistor (as Figure 1 shown). Figure 2 Displays a perspective view similar to Figure 1 this.

[0020] Figure 3 and Figure 4 and Figure 5A and Figure 6 and Figure 11A show cross-sectional views along a cross-section similar to the reference cross-section A-A' in Figure 1 . Figure 5B and Figure 7 and Figure 8 and Figure 9 and Figure 10 and Figure 11B are shown as cross-sectional views along a cross-section similar to the reference cross-section B-B' in Figure 1 .

[0021] In Figure 2 , a wafer including a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with a p-type or n-type dopant) or undoped. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or combinations thereof. In some embodiments, each substrate 20 can include an embedded CMP stop layer (not shown separately), such as a silicon-germanium layer embedded (e.g., sandwiched) between silicon material layers.

[0022] Semiconductor strips 28 are formed extending upward from the semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multi-layer stack 22. The stacked components of the multi-layer stack 22 are hereinafter referred to as nanostructures. Specifically, the multi-layer stack 22 includes pseudo-nanostructures 24A, pseudo-nanostructures 24B, lower semiconductor nanostructures 26L, and upper semiconductor nanostructures 26U. The pseudo-nanostructures 24A and the pseudo-nanostructures 24B can be further collectively referred to as pseudo-nanostructures 24, and the lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U can be further collectively referred to as semiconductor nanostructures 26.

[0023] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from the candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have a high etching selectivity with respect to each other. Thus, in subsequent processes, the pseudo-nanostructure 24B can be removed at a faster rate than the pseudo-nanostructure 24A.

[0024] The semiconductor nanostructure 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor materials can be selected from the candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be formed of the same semiconductor material or can be formed of different semiconductor materials. In addition, the first and second semiconductor materials of the pseudo-nanostructure 24 have a high etch selectivity with respect to the third semiconductor material of the semiconductor nanostructure 26. Thus, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-nanostructure 24A is formed of or includes silicon germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-semiconductor nanostructure 24B can be formed of germanium or silicon germanium with a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0025] The lower semiconductor nanostructure 26L will provide a channel region for the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26U will provide a channel region for the upper nanostructure FET of the CFET. The semiconductor nanostructure 26 directly above / below (e.g., in contact with) the pseudo-nanostructure 24B can be used for isolation and can or cannot be used as the channel region of the CFET. The pseudo-nanostructure 24B will subsequently be replaced by an isolation structure that defines the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0026] To form the semiconductor strip 28, first, second, and third semiconductor material layers (arranged as shown and described above) may be deposited over the semiconductor substrate 20. The first, second, and third semiconductor material layers may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by processes such as chemical vapor deposition (CVD) processes or atomic layer deposition (ALD) processes. Then, a patterning process may be applied to the first, second, and third semiconductor material layers and the semiconductor substrate 20 to define the semiconductor strip 28, which includes semiconductor fins 20', pseudo-nanostructures 24, and semiconductor nanostructures 26. The semiconductor fins and nanostructures may be patterned by any suitable method. For example, the patterning process may include one or more lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with pitches, for example, smaller than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacer may be used as an etch mask for the patterning process to etch the first, second, and third semiconductor material layers and the semiconductor substrate 20. The etching may be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0027] As Figure 2 shown, the STI region 32 is formed above the substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric liner and a dielectric material on the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc., or a combination thereof. The formation of the STI region 32 may include depositing a dielectric layer and performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove the excess portion of the dielectric material. The deposition process may include ALD, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. Then, the dielectric layer is recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multi-layer stack 22) protrudes higher than the remaining STI region 32. Although Figure 2 shown that the top surface of the STI region 32 is flat, the top surface of the STI region 32 may be concave (see Figure 5B and Figure 7a more detailed view), depending on the etching process used for the recessed STI region 32.

[0028] After the STI region 32 is formed, a dummy gate stack 42 can be formed on the sidewalls of the upper portion of the semiconductor strip 28 (the portion that protrudes higher than the STI region 32) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 can include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 can be formed of or include, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 is conductive or non-conductive and can be selected from the group including amorphous silicon, polysilicon, poly-silicon germanium (poly-SiGe), etc. A mask layer 40 is formed on the planarized dummy gate layer 38 and can include, for example, silicon nitride, silicon oxynitride, etc. Next, the mask layer 40 can be patterned by a lithography and etching process to form a mask, and then the mask is used to etch and pattern the dummy gate layer 38, and possibly the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0029] In Figure 3 this step, gate spacers 44 and source / drain recesses 46 are formed. First, the gate spacers 44 are formed above the multi-layer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacers 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0030] Subsequently, source / drain recesses 46 are formed in the semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multi-layer stack 22 and into the semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or at the same level as the top surface of the STI region 32. In the etching process, the gate spacers 44 and the dummy gate stack 42 mask some portions of the semiconductor strip 28. The etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop the etching of the source / drain recesses 46 when the source / drain recesses 46 reach the desired depth.

[0031] In Figure 4In this case, an internal spacer 54 and a dielectric isolation layer 56 are formed. Forming the internal spacer 54 and the dielectric isolation layer 56 may include an etching process that etches the pseudo-nanostructures 24A laterally and removes the pseudo-nanostructures 24B. The etching process may be isotropic and may be selective to the material of the pseudo-nanostructures 24, such that the pseudo-nanostructures 24 are etched at a faster rate than the semiconductor nanostructures 26. The etching process may also be selective to the material of the pseudo-nanostructures 24B, such that the pseudo-nanostructures 24B are etched at a faster rate than the pseudo-nanostructures 24A. In this way, the pseudo-nanostructures 24B can be completely removed between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively) without completely removing the pseudo-nanostructures 24A. In some embodiments, where the pseudo-nanostructures 24B are formed of germanium or silicon germanium having a high percentage of germanium atoms, the pseudo-nanostructures 24A are formed of a low percentage of germanium atoms, and the semiconductor nanostructures 26 are formed of silicon without germanium, the etching process may include a dry etching process (with or without plasma) using chlorine gas. Since the pseudo-gate stack 42 is around the sidewalls of the semiconductor nanostructures 26 (see Figure 2 ), the pseudo-gate stack 42 can support the upper semiconductor nanostructures 26U such that the upper semiconductor nanostructures 26U do not collapse when the pseudo-nanostructures 24B are removed. Additionally, although the sidewalls of the pseudo-nanostructures 24A are illustrated as being straight after etching, the sidewalls can be concave or convex.

[0032] The internal spacer 54 is formed on the sidewalls of the recessed pseudo-nanostructures 24A, and the dielectric isolation layer 56 is formed between the upper semiconductor nanostructures 26U (collectively) and the lower semiconductor nanostructures 26L (collectively). As described in more detail subsequently, source / drain regions will then be formed in the source / drain recesses 46, and the pseudo-nanostructures 24A will be replaced by corresponding gate structures. The internal spacer 54 acts as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structures. Additionally, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (such as the etching process for forming the gate structures). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructures 26U (collectively) from the lower semiconductor nanostructures 26L (collectively). Additionally, the intermediate semiconductor nanostructures (those of the semiconductor nanostructures 26 that contact the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0033] The internal spacer 54 and the dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the pseudo-nanostructures 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon oxycarbide, silicon oxynitride, etc. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. When etched, the insulating material has a portion that remains on the sidewalls of the pseudo-nanostructure 26A (thus forming the internal spacer 54), and has a portion that remains between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thereby forming the dielectric isolation layer 56).

[0034] As Figure 4 shown, lower and upper epitaxial source / drain regions 62L and 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower part of the source / drain recess 46. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L and does not contact the upper semiconductor nanostructure 26U. The internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0035] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon, which is doped with an n-type dopant, such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon germanium, which is doped with a p-type dopant, such as boron, indium, etc. The lower epitaxial source / drain region 62L can be in-situ doped and can be implanted or not implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surface (e.g., sidewalls) of the upper semiconductor nanostructure 26U can be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can be removed.

[0036] As a result of the epitaxial process for forming the lower epitaxial source / drain region 62L, the upper surface of the lower epitaxial source region 62L has facets that laterally extend outwardly beyond the sidewalls of the multi-layer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after completion of the epitaxial process. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0037] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source / drain region 62L. The first CESL 66 can be formed of a dielectric material having a high etch selectivity to the etch of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed of a dielectric material that can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Applicable dielectric materials for the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0038] The formation process can include depositing a conformal CESL layer, depositing the material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the unetched first CESL 66. Then an anisotropic etch process is performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0039] Then an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can grow epitaxially from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source region / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to the conductivity type of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped oppositely to the lower epitaxial source / drain region 62L. Alternatively, the conductivity types of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can be the same. The upper epitaxial source / drain region 62U can be in-situ doped, and / or n-type or p-type dopants can be implanted. Adjacent upper source / drain regions 62U can remain separated or can merge after the epitaxial process.

[0040] After forming the upper epitaxial source / drain regions 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be respectively similar to those of the first CESL 66 and the first ILD 68, and will not be discussed in detail herein. The formation process can include depositing layers for the second CESL 70 and the second ILD 72, and performing a planarization process to remove the excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the mask 40 (if present) or the dummy gate layer 38 are substantially coplanar (within process variations). Thus, the top surface of the mask 40 (if present) or the dummy gate layer 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 remains after the removal process. In other embodiments, the mask 40 is removed such that the top surface of the dummy gate layer 38 is exposed through the second ILD 72.

[0041] Figure 5A and Figure 5B Different cross-sections of a replacement gate process of replacing the dummy gate stack 42 and the dummy nanostructure 24A with a gate stack 90 are shown. Figure 5A Shows along Figure 1 Cross-sectional views taken along reference line A-A'; Figure 5B Shows along Figure 1 Cross-sectional views taken along reference line B-B'. The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes such that a recess is defined between the gate spacers 44 and the upper portion of the semiconductor strip 28 is exposed. Then, the remaining portion of the dummy nanostructure 24A is removed by etching such that the recess extends between the semiconductor nanostructures 26. In the etching process, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructures 26, the dielectric isolation layer 56, and the inner spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructures 26 are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0042] Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructures 26. The gate dielectric 78 conformally forms on the exposed surfaces of the recesses (removed dummy gate stack 42 and dummy nanostructures 24A) including the semiconductor nanostructures 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 surrounds all (e.g., four) sides of the semiconductor nanostructures 26. Specifically, the gate dielectric 78 can be formed on the top surface of the semiconductor fin 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructures 26; and on the sidewalls of the gate spacers 44. The gate dielectric 78 can include oxides such as silicon oxide or metal oxide, silicates such as metal silicate, combinations thereof, multilayers thereof, etc. The gate dielectric 78 can include a high dielectric constant (high-k) material with a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 78 can be deposited using a conformal deposition process such that the portion of the gate dielectric 78 on the STI region 32 can have the same profile as the upper surface of the STI region 32 (e.g., a concave profile as Figure 5B shown). The method of forming the gate dielectric 78 can include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 can include multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0043] A lower gate electrode 80L is formed on the gate dielectric 78 around the lower semiconductor nanostructures 26L. For example, the lower gate electrode 80L surrounds the lower semiconductor nanostructures 26L. The lower gate electrode 80L can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 80L can include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and filling materials.

[0044] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function tuning layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or alternatively, the lower gate electrode 80L may include a dipole-induced element suitable for the device type of the lower nanostructure FET. Acceptable dipole-induced elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0045] The lower gate electrode 80L may be formed by conformally depositing one or more gate electrode layers that recess the gate electrode layer. The conformal deposition process for depositing the lower gate electrode 80L may result in a portion of the lower gate electrode portion 80L on the STI region 32 having the same profile as the upper surface of the STI region 32 (e.g., a concave profile as Figure 5B shown). Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to recess the gate electrode layer. The etching may be isotropic. Etching the lower gate electrode 80L may expose the upper semiconductor nanostructure 26U.

[0046] In some embodiments, an isolation layer (not explicitly shown) may be selectively formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, combinations thereof, etc.) and then recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0047] Then, the upper gate electrode 80U is formed on the above isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U surrounds the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed of the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function tuning layers (e.g., an n-type work function tuning layer and / or a p-type work function tuning layer) formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer upper gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and filling materials.

[0048] In addition, a removal process is performed to make the top surface of the upper gate electrode 80U flush with the top surface of the second ILD 72. The removal process for forming the gate dielectric 78 can be the same removal process as that for forming the upper gate electrode 80U. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etchback process, combinations thereof, etc. can be used. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each pair of the gate dielectric 78 and the gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a "gate structure" 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 ). The lower gate structure 90L can also extend along the sidewalls and / or the top surface of the semiconductor fin 20'.

[0049] In Figure 6 , a metal-semiconductor alloy region 94 and source / drain contacts 96 are formed through the second ILD 72 to be electrically coupled to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. As an example of forming the source / drain contacts 96, openings are formed through the second ILD 72 and the second CESL 70 using acceptable lithography and etching techniques. Liners (not shown separately) such as diffusion barrier layers, adhesion layers, etc. and conductive materials are formed in the openings. The liners can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive materials can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process can be performed to remove excess materials from the top surfaces of the gate spacer 44 and the second ILD 72. The remaining liners and conductive materials form the source / drain contacts 96 in the openings. In some embodiments, a planarization process such as CMP, etchback process, combinations thereof, etc. can be used. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contacts 96 are substantially coplanar (within process variations).

[0050] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 can be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, and nickel germanide, etc.), a germanosilicide region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 94 can be formed prior to the material of the source / drain contact 96 by depositing a metal in the opening of the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the source / drain region 62 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the opening of the source / drain contact 96, e.g., to remove any residual metal from the surface of the metal-semiconductor alloy region 94. Then, the material of the source / drain contact 96 can be formed on the metal-semiconductor alloy region 94.

[0051] Then, an ESL 104 and a third ILD 106 are formed. In some embodiments, the ESL 104 can include a dielectric material having a high etch selectivity to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 106 can be formed using flowable CVD, ALD, etc., and the material can include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0052] Subsequently, gate contacts 108 and source / drain vias 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contacts 108 and the source / drain vias 110, openings for the gate contacts 108 and the source / drain vias 110 are formed through the third ILD 106 and the ESL 104. Acceptable lithography and etching techniques can be used to form the openings. Liners (not shown separately) such as diffusion barrier layers, adhesion layers, etc. and conductive materials are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove the excess material from the top surface of the third ILD 106. The remaining liner and conductive material form the gate contacts 108 and the source / drain vias 110 in the openings. The gate contacts 108 and the source / drain vias 110 can be formed in different processes or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contacts 108 and the source / drain vias 110 can be formed in a different cross-section, which can avoid contact short circuits.

[0053] A front-side interconnect structure 114 is formed on the device layer 112. The front-side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 92 / 92L in the dielectric layer 116. The dielectric layer 116 can include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 can also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc. or a combination thereof above the low-k dielectric material. The dielectric layer 116 can also include a polymer layer.

[0054] The conductive components 92 can include wires and vias, which can be formed using a damascene process. The conductive components 92 can include metal wires and metal vias, and the metal vias include a diffusion barrier layer and a copper-containing material on the diffusion barrier layer. Aluminum pads can also be present above the metal wires and vias and the aluminum pads are electrically connected to the metal wires and vias. As will be explained in more detail below, contacts to the lower gate structure 90L and the lower source / drain region 62L can be formed through the back side (e.g., the side opposite to the front-side interconnect structure 114) of the device layer 112.

[0055] Figures 7 to 11B A cross-sectional view showing an intermediate step of forming back-side gate contacts and source / drain contacts to the lower gate structure 90L and the lower source / drain region 62L according to some embodiments is shown. In Figures 7 to 10 and Figure 11B For ease of illustration, features above the upper gate electrode 80U on the front side of the device layer 112 are omitted, but it should be understood that in Figures 7 to 10and Figure 11B In the cross-section shown, the ESL 104, the third ILD 106, and the front-side interconnect structure 114 are disposed below the upper gate electrode 80U. Referring Figure 7 , the direction of the device can be flipped. For example, a carrier substrate (not explicitly shown) can be bonded to the front-side interconnect structure 114 by dielectric-to-dielectric bonding, and the device can be flipped to expose the backside of the device layer 112 (e.g., the side of the substrate 20 opposite to the front-side interconnect structure 114).

[0056] A planarization process can then be performed on the backside of the device layer 112 (e.g., on the substrate 20). In some embodiments, for example, the planarization process can include a combination of CMP and / or etch-back processes. The planarization process and / or the etching process can remove the substrate 20, exposing the semiconductor strip 20' and the STI region 32. Then, one or more etching processes are performed to remove the semiconductor strip 20' and the STI region 32. Removing the semiconductor substrate 20 and the semiconductor strip 20' advantageously improves the electrical performance by improving the isolation between the subsequently formed backside gate contact and / or the backside source / drain contact. For example, by removing the semiconductor substrate 20 and the semiconductor strip 20', the problem of short-circuiting of the backside contact through the semiconductor substrate 20 / semiconductor strip 20' can be solved. The STI region 32 can also be removed so that the backside gate ESL can cover the backside of the lower gate electrode 80L. The semiconductor strip 20' and the STI region 32 can be removed in any order by any suitable etching process. The etching process can selectively etch the material of the semiconductor strip 20' and / or the STI region 32 at a faster rate than the surrounding components, such that the lower source / drain region 62L is not significantly etched or damaged during the removal of the semiconductor strip 20' or the removal of the STI region 32. In some embodiments, the semiconductor strip 20' is removed by a wet etching process while the STI region 32 is removed by a dry etching process. Removing the semiconductor strip 20' and the STI region 32 exposes the gate dielectric layer 78. Optionally, in some embodiments, removing the semiconductor strip 20' can partially recess the lower source / drain region 62L to the same level as or below the back surface of the lower gate structure 90L (not explicitly shown).

[0057] In Figure 8In [the figure], a backside gate ESL 120 and a backside ESL 122 are sequentially deposited on the backside of the device layer 112, such as on the gate dielectric layer 78. As a result, the gate dielectric layer 78 can be disposed between the backside gate ESL 120 and the lower gate electrode 80L along a line perpendicular to the backside of the lower gate electrode 80L. The backside gate ESL 120 can be a layer including a metal, such as a metal oxide, etc. In some embodiments, the backside gate ESL 120 has a k value of at least 9 and includes aluminum oxide, hafnium silicon oxide, zirconium oxide, etc. In other embodiments, the backside gate ESL can include different materials, such as silicon oxynitride, silicon nitride, etc. The backside gate ESL 120 can be deposited by any suitable process, such as PVD, CVD, ALD, etc. The backside gate ESL 120 protects the lower gate electrode 80L and the semiconductor nanostructure 26 during subsequent patterning processes to form a backside gate contact opening (e.g., contact opening 130, see Figure 10 ). In some embodiments, the backside gate ESL 120 can have a thickness T1 thick enough to provide sufficient protection to the lower gate electrode 80L and the semiconductor nanostructure 26. In some embodiments, the thickness T1 of the backside gate ESL 120 is at least 2 nm to provide sufficient protection to the lower gate electrode 80L and the semiconductor nanostructure 26 during subsequent gate contact opening steps. For example, the thickness T1 of the backside gate ESL 120 can be in the range of 2 nm to 10 nm. When the thickness T1 of the backside gate ESL 120 is greater than 10 nm, it may result in inappropriate contact resistance.

[0058] The backside gate ESL 120 allows a subsequently formed backside gate contact (e.g., gate contact 132, see Figure 11A and Figure 11B ) to directly overlap with the semiconductor nanostructure 26. When forming the backside gate contact, there is no longer a need to avoid the position where the channel regions (e.g., semiconductor nanostructure 26) of stacked transistors overlap. As a result, improved wiring flexibility can be achieved and a semiconductor nanostructure 26 with a larger width W1 that provides improved device speed can be provided. For example, by increasing the width of the channel region, a device speed improvement between 14.4% and 19% has been observed in the exemplary devices. In some embodiments, the width W1 of the nanostructure is greater than 34 nm, such as in the range of 10 nm to 65 nm, thereby achieving improved device performance. Therefore, various embodiments allow for improved process integration, increased wiring flexibility, and increased device performance (e.g., speed).

[0059] The dorsal ESL 122 can be formed using materials and processes similar to those of the aforementioned ventral ESL 104. For the sake of brevity, a detailed description of the dorsal ESL 122 is omitted. The dorsal ESL 122 can provide additional etch control during the formation of the dorsal gate contact and etch control during the formation of the dorsal source / drain contact. For example, the dorsal ESL 122 can provide endpoint control for patterning the endpoints of the dorsal source / drain contact openings that expose the lower source / drain regions 62L.

[0060] In Figure 9 the first dorsal ILD 124, dorsal ESL 126, and second dorsal ILD 128 are sequentially deposited over the dorsal ESL 122. The dorsal ESL 126 can be formed using materials and processes similar to those of the aforementioned ventral ESL 104, and the first and second dorsal ILDs 124 and 128 can be formed using materials or processes similar to those of the third ILD 106 described above.

[0061] In some embodiments, between the deposition of the first dorsal ILD 124 and the deposition of the dorsal ESL 126, dorsal source / drain contacts 134 and metal-semiconductor alloy regions 136 (also referred to as silicide regions 136) are formed (see Figure 11A ). The dorsal source / drain contacts 134 and metal-semiconductor alloy regions 136 can be formed using materials and processes similar to those of the source / drain contacts 96 and metal-semiconductor metal alloy regions 94 described above, respectively. In some embodiments, a planarization process can be performed on the first dorsal ILD 124 to remove excess material while forming the source / drain contacts 134. The planarization process (e.g., CMP process, etc.) can further remove any undesirable topography from the top surface of the first dorsal ILD 124 to provide a relatively flat (within process variations) surface on which subsequent layers can be formed. The dorsal source / drain contacts 134 can extend through the first dorsal ILD 124, dorsal ESL 122, and dorsal gate ESL 120 to electrically couple to the dorsal side of the lower source / drain regions 62L. The dorsal ESL 122 can provide endpoint control for etching the dorsal source / drain contact openings, which are subsequently filled to form the dorsal source / drain contacts 134.

[0062] In Figure 10In [description], the back-gate contact opening 130 is patterned through the second backside ILD 128, backside ESL 126, first backside ILD 124, backside ESL 122, back-gate ESL 120, and gate dielectric 78 to expose the lower gate electrode 80L. The patterning of the back-gate contact opening 130 can be achieved by a combination of photolithography and etching processes. Specifically, the etching of the back-gate ESL 120 can use an etchant that selectively etches the back-gate ESL 120 at a faster rate than the surrounding components of the lower nanostructure FET (e.g., the lower gate electrode 80L and / or semiconductor nanostructure 26). In some embodiments, the etching of the back-gate ESL 120 can include an anisotropic etching process using an etching gas (e.g., a fluorine-based etchant). Examples of the fluorine-based etchant of the embodiments include F2, HF, etc. Additionally, an inert carrier gas can also flow during the anisotropic etching process. For example, the carrier gas can include Ar, He, N2, combinations thereof, etc.

[0063] The back-gate contact opening 130 can overlap and be laterally aligned with the semiconductor nanostructure 26, which provides the channel regions of the upper and lower nanostructure FETs in the device layer 112. The back-gate ESL 120 is made of a suitable material and is thick enough to allow the back-gate contact opening 130 to be patterned with precise endpoint control. For example, the back-gate ESL 120 is made of a metal oxide (e.g., aluminum oxide) and is at least 2 nm thick in various embodiments. As a result, the back-gate contact opening 130 can directly overlap the semiconductor nanostructure 26 without damaging the semiconductor nanostructure 26 (e.g., by over-etching). The backside ESL 122 is also included to further improve the endpoint control of etching the back-gate contact opening 130.

[0064] In Figure 11A and Figure 11BIn [the figure], the backside gate contact 132 and the backside source / drain via 138 are formed to contact the lower gate electrode 80L and the source / drain contact 134, respectively. Specifically, the backside gate contact 132 may be formed in the backside gate contact opening 130 and overlap with the semiconductor nanostructure 26. As an example of forming the backside gate contact 132, a liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the backside gate contact opening 130. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum, etc. A planarization process, such as CMP, may be performed to remove the excess material from the top surface of the second backside ILD 128. The remaining liner and conductive material form the backside gate contact 132 in the backside gate contact opening 130. The backside source / drain via 138 may be formed of materials and processes similar to those of the source / drain via 110 described above. The backside gate contact 132 and the backside source / drain via 138 may be formed by different processes or may be formed by the same process. Although shown as formed in the same cross-section, it should be understood that each of the backside gate contact 132 and the backside source / drain via 138 may be formed in different cross-sections, which may avoid short circuits of the contacts. In addition, although the backside gate contact 132 is shown as extending through a specific number of backside ILDs (e.g., backside ILDs 124 and 128) and backside ESLs (e.g., ESLs 120, 122, and 126), the backside gate contact 132 may extend through any number of backside ILDs and backside ESLs, depending on the backside wiring configuration and the corresponding processing steps for forming the backside wiring (e.g., backside source / drain contacts, backside interconnects, etc.). For example, in other embodiments, the backside gate contact 132 may extend through at least an additional backside ESL on the second backside ILD 128 and at least an additional backside ILD on the additional backside ESL.

[0065] Figures 12A to 17B A cross-sectional view showing an intermediate stage in the formation process of a stacked transistor (as Figure 1 shown) according to some embodiments is provided. In Figures 12A to 17B , unless otherwise specified, the same reference numerals denote the same elements formed by the same processes as described above Figures 2 to 11B in Figures 12A to 17B , a backside gate ESL 140 is selectively deposited on the backside of the lower gate electrode 80L instead of forming a blanket-deposited backside gate ESL 120. Figure 12A , Figure 13A , Figure 14A and Figure 17A show cross-sectional views along a cross-section similar to the reference cross-section A-A' in Figure 1 . Figure 12B ,Figure 13B , Figure 14B , Figure 15 , Figure 16 and Figure 17B are shown as cross-sectional views along a cross-section similar to the reference cross-section B-B' in Figure 1 .

[0066] Figure 12A and Figure 12B show a device in an intermediate processing stage similar to the intermediate structure of Figure 7 , where the same reference numerals represent the same elements formed by the same process. Specifically, in Figure 12A and Figure 12B , the device layer 112 (including the gate stack 90, source / drain regions 62, and semiconductor nanostructure 26) is formed as described above, and the front-side interconnect structure 114 is formed on the device layer 112. Then, a carrier substrate (not explicitly shown) is bonded to the front-side interconnect structure 114; the intermediate structure is flipped; and the semiconductor substrate 20 and semiconductor tape 20' are removed using a similar process as described above. However, in Figure 12A and Figure 12B , the STI region 32 has not been removed yet. Removing the semiconductor tape 20' defines an opening 142 in the STI region 32, and the opening 142 corresponds to the position of the removed semiconductor tape 20'. The opening 142 exposes a portion of the gate dielectric layer 78 on the back side of the lower gate electrode 80L.

[0067] In Figure 13A and Figure 13B , a portion of the gate dielectric 78 in the opening 142 is etched away to expose the lower gate electrode 80L. For example, the STI region 32 acts as a mask during the etching of the gate dielectric 78, such that only the portion of the gate dielectric 78 overlapping with the semiconductor nanostructure 26 is etched away. The gate dielectric 78 can be selectively etched with an etchant (e.g., diluted hydrofluoric acid (dHF), etc.) that removes the material of the gate dielectric 78 at a faster rate than the surrounding structures. For example, the gate dielectric 78 in the opening 142 can be etched away without significantly removing the material of the lower gate electrode 80L or the material of the lower source / drain region 62L. In some embodiments, etching the gate dielectric 78 includes first etching the interface layer of the gate dielectric 78 and then etching the high-k gate dielectric of the gate dielectric 78. In some embodiments, etching the gate dielectric 78 may also include slightly etching the inner spacer 54 exposed by the opening 142. For example, after the etching process, the side surfaces of the gate dielectric 78 and the inner spacer 54 in the opening 142 may be set at the same level. In other embodiments, the lateral surface of the gate dielectric 78 may be set at a level lower or higher than the lateral surface of the inner spacer 54 in the opening 142.

[0068] In Figure 14A and Figure 14B the dorsal gate ESL 140 is selectively deposited on the lower gate electrode 80L exposed in the opening 142. Thus, the resulting dorsal gate ESL 140 can be in direct physical contact with the dorsal side of the lower gate electrode 80L. The dorsal gate ESL 140 can be a metal layer made of, for example, cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum, combinations thereof, etc. The dorsal gate ESL 140 is grown on the lower gate electrode 80L by a bottom-up selective process that grows directionally (e.g., in a direction away from the lower gate electrode 80L). For example, the dorsal gate ESL 140 can be grown by an electroless plating process using the lower gate electrode 80L as a seed layer. Since the electroless plating process is a selective bottom-up process, the dorsal gate ESL 140 can be grown on the lower gate electrode 80L without being formed on the lower source / drain region 62L or the inner spacer 54.

[0069] The dorsal gate ESL 140 protects the lower gate electrode 80L and the semiconductor nanostructure 26 during subsequent patterning to form a dorsal gate contact opening (e.g., the contact opening of the dorsal gate contact 132, see Figure 17A and Figure 17B ). As a result, each of the dorsal gate ESLs 140 can have a thickness T2 that is thick enough to provide sufficient protection to the lower gate electrode 80L and the semiconductor nanostructure 26. In some embodiments, the thickness T2 of the dorsal gate ESL 140 is at least 4 nm to provide sufficient protection to the lower gate electrode 80L and the semiconductor nanostructure 26 during a subsequent gate contact opening step. For example, the thickness T2 of the ESL 140 can be in the range of 4 nm to 10 nm. When the thickness T2 of the dorsal gate ESL 140 is greater than 10 nm, an inappropriate contact resistance may result.

[0070] The dorsal gate ESL 140 allows for the subsequent formation of a dorsal gate contact (e.g., the gate contact 132, see Figure 11A and Figure 11B)Overlap directly with the semiconductor nanostructure 26. When forming the back-gate contact, there is no longer a need to avoid the position that overlaps with the channel region (e.g., the semiconductor nanostructure 26) of the stacked transistor. As a result, improved routing flexibility can be achieved, as well as nanostructures 26 with a greater width, which provides improved device speed. For example, by increasing the width of the channel region, a device speed improvement between 14.4% and 19% has been observed in the exemplary devices. Additionally, by forming the back-gate ESL 140 from the above-mentioned metals (e.g., cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum), the contact resistance between the back-gate contact and the lower gate electrode 80L can be reduced. Thus, various embodiments allow for improved process integration, increased routing flexibility, and increased device performance (e.g., speed and lower contact resistance).

[0071] In Figure 15 , a process similar to that described above with respect to Figure 7 is used to remove the STI region 32. Removing the STI region 32 allows the STI region 32 to be replaced with a dielectric layer of better quality (e.g., the first backside ILD 124) to improve the isolation of the backside contact and metallization components. In Figure 16 , the first backside ILD 124, the backside ESL 126, and the second backside ILD 128 are sequentially deposited on the back-gate ESL 140 and the lower gate electrode 80L. The deposition of the first backside ILD 124, the backside ESL 125, and the second backside ILD 128 can be formed by processes and methods similar to those described above with respect to Figure 9 , and for the sake of brevity, will not be repeated herein. In some embodiments, the first backside ILD 124 can extend along the sidewalls of the back-gate ESL 140 and the side surfaces of the internal spacer 54 and be in direct contact therewith (see Figure 17A ). The first backside ILD 124 can further extend between the back-gate ESL 140 and the lower source / drain region 62L.

[0072] In some embodiments, between the deposition of the first backside ILD 124 and the deposition of the backside ESL 126, the backside source / drain contact 134 and the metal-semiconductor alloy region 136 (also referred to as the silicide region 136) are formed (see Figure 17A ). The backside source / drain contact 134 and the metal-semiconductor alloy region 136 can be formed using materials and processes similar to those described above. The backside source / drain contact 134 can extend through the first backside ILD 124 to be electrically coupled to the backside of the lower source / drain region 62L.

[0073] In Figure 17A and Figure 17BIn this case, a back gate contact 132 is formed to extend through the second backside ILD 128, the backside ESL 126, the first backside ILD 124, and the back gate ESL 140 to electrically couple the lower gate electrode 80L. The back gate contact 132 can be formed by processes and materials similar to those discussed above. For example, using a combination of photolithography and etching processes, a gate contact opening is patterned through the second backside ILD 128, the backside ESL 126, the first backside ILD 124, and the back gate ESL 140 to expose the lower gate electrode 80L. The back gate ESL 140 can be etched using an etchant that selectively etches the back gate ESL 140 at a faster rate than the surrounding components of the lower nanostructure FET (such as the lower gate electrode 80L and / or the semiconductor nanostructure 26).

[0074] The back gate contact 132 can overlap and be laterally aligned with the semiconductor nanostructure 26, which provides the channel regions of the upper and lower nanostructure FETs in the device layer 112. The back gate ESL 140 is made of a suitable material and is thick enough to allow the back gate contact opening to be patterned with precise endpoint control. For example, the back gate ESL 140 is made of a metal (such as cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum, etc.) and is at least 4 nm thick in various embodiments. As a result, the back gate contact 132 can directly overlap the semiconductor nanostructure 26 without damaging the semiconductor nanostructure 26 (e.g., by over-etching). In addition, the metal back gate ESL provides the additional benefit of reducing the contact resistance between the back gate contact 132 and the lower gate electrode 80L.

[0075] As an example of forming the back gate contact 132, a liner (not shown separately) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the back gate contact opening 130. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, molybdenum, etc. A planarization process, such as CMP, can be performed to remove the excess material from the top surface of the second backside ILD 128. The remaining liner and conductive material form the back gate contact 132 in the back gate contact opening 130.

[0076] As Figure 17A and Figure 17BAs shown, the backside source / drain via 138 is formed using a process and materials similar to those described above to contact the source / drain contact 134. The backside gate contact 132 and the backside source / drain via 138 may be formed using different processes or may be formed using the same process. Although shown as being formed in the same cross-section, it should be understood that each of the backside gate contact 132 and the backside source / drain via 138 may be formed in a different cross-section, which can avoid short circuits in the contacts. Although the backside gate contact 132 is shown as extending through a specific number of backside ILDs (e.g., backside ILDs 124 and 128) and backside ESLs (e.g., ESLs 140 and 126), the backside gate contact 132 may extend through any number of backside ILDs and backside ESLs, depending on the backside wiring configuration and the corresponding processing steps used to form the backside wiring (e.g., backside source / drain contacts, backside interconnects, etc.). For example, in other embodiments, the backside gate contact 132 may extend through at least an additional backside ESL over the second backside ILD 128 and at least an additional backside ILD over the additional backside ESL.

[0077] Various embodiments provide a backside gate ESL that allows a backside gate contact to be formed on a lower gate stack at a location where the backside gate contact overlaps the channel region of a stacked transistor during the backside gate contact formation process without damaging the channel region. As a result, when forming the backside gate contact, there is no need to avoid the location that overlaps the channel region, thereby allowing improved wiring flexibility. In addition, since the channel region can directly overlap the backside gate contact, the channel region can be designed and fabricated to have a greater width to increase device speed. For example, by increasing the width of the channel region, a device speed improvement between 14.4% and 19% has been observed in the embodiment devices. The backside gate ESL may be made of metal or metal oxide, which further reduces the contact resistance in the device. As a result, various embodiments allow improved process integration, increased wiring flexibility, and increased device performance.

[0078] In some embodiments, a semiconductor device includes: a plurality of first nanostructures extending between a first source / drain region; a plurality of second nanostructures located above the plurality of first nanostructures and extending between a second source / drain region; a first gate stack surrounding the plurality of first nanostructures; and a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures. The semiconductor device further includes: a backside gate etch stop layer (ESL) located on a backside of the first gate stack; and a backside gate contact extending through the backside gate ESL and electrically coupled to the first gate stack. The backside gate ESL includes a metal. Optionally, in some embodiments, the backside gate ESL is made of a metal oxide, and wherein the metal oxide is alumina, hafnium silicon oxide, or zirconium oxide. Optionally, in some embodiments, the thickness of the backside gate ESL is at least 2 nm. Optionally, in some embodiments, the backside gate ESL is made of a metal, and wherein the metal is cobalt, titanium, tungsten, ruthenium, tantalum, aluminum, or molybdenum. Optionally, in some embodiments, the thickness of the backside gate ESL is at least 4 nm. Optionally, in some embodiments, the plurality of first nanostructures overlap with the backside gate contact. Optionally, in some embodiments, the backside gate ESL is in direct physical contact with a first gate of the first gate stack. Optionally, in some embodiments, the first gate stack includes one or more gate dielectrics located between a first gate electrode of the first gate stack and the plurality of first nanostructures, wherein the one or more gate dielectrics are further disposed between the backside gate ESL and the first gate electrode. Optionally, in some embodiments, the semiconductor device further includes a backside ESL contacting a surface of the backside gate ESL opposite to the first gate stack, wherein the backside gate contact extends through the backside ESL. Optionally, in some embodiments, the semiconductor device further includes a backside interlayer dielectric (ILD) on a side of the backside gate ESL opposite to the first gate stack, wherein the backside gate contact extends through the backside ILD. Optionally, in some embodiments, the backside ILD contacts sidewalls of the backside gate ESL.

[0079] In some embodiments, a method of forming a semiconductor device includes: forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked; exposing a backside of a first gate stack of the first transistor, wherein exposing the backside of the first gate stack includes removing the semiconductor substrate; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack. Optionally, in some embodiments, the first gate stack includes a gate dielectric and a gate electrode, and wherein forming the backside gate ESL includes blanket depositing the backside gate ESL over the gate dielectric. Optionally, in some embodiments, the method further includes: blanket depositing an additional ESL on a surface of the backside gate ESL opposite the first transistor, wherein patterning the contact opening includes patterning the contact opening through the additional ESL and the gate dielectric. Optionally, in some embodiments, the first gate stack includes a gate dielectric and a gate electrode, and wherein forming the backside gate ESL includes selectively depositing the backside gate ESL on the gate electrode. Optionally, in some embodiments, exposing the backside of the first gate stack further includes defining an opening in a shallow trench isolation (STI) region by removing a semiconductor fin, wherein the method further includes: removing a portion of the gate dielectric exposed by the opening in the STI region, and wherein forming the backside gate ESL includes selectively depositing the backside gate ESL in the opening. Optionally, in some embodiments, the backside gate ESL includes a metal or a metal oxide, wherein the first transistor includes a plurality of nanostructures, and wherein patterning the contact opening includes patterning the contact opening at a location overlapping the plurality of nanostructures.

[0080] In some embodiments, a method of forming a semiconductor device includes: forming a multi-layer stack above a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions above the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; replacing the pseudo-nanostructures with a lower gate stack surrounding the lower semiconductor nanostructures and an upper gate stack surrounding the upper semiconductor nanostructures; exposing a backside of the lower gate stack; depositing a metal-containing backside gate etch stop layer (ESL) on the backside of the lower gate stack; and forming a backside gate contact that extends through the metal-containing backside gate ESL to electrically connect to the lower gate stack. The backside gate contact overlaps with the lower semiconductor nanostructures and the upper semiconductor nanostructures. Optionally, in some embodiments, depositing the metal-containing backside gate ESL includes a blanket deposition process. Optionally, in some embodiments, depositing the metal-containing backside gate ESL includes a selective deposition process.

[0081] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a plurality of first nanostructures extending between the first source / drain regions; A plurality of second nanostructures, located above the plurality of first nanostructures, the plurality of second nanostructures extending between the second source / drain regions; a first gate stack surrounding the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a backside gate etch stop layer on a backside of the first gate stack, wherein the backside gate etch stop layer comprises a metal; and A backside gate contact extends through the backside gate etch stop layer and is electrically coupled to the first gate stack.

2. The semiconductor device according to claim 1, wherein The backside gate etch stop layer is made of metal oxide, and wherein the metal oxide is aluminum oxide, hafnium silicon oxide or zirconium oxide.

3. The semiconductor device according to claim 1, wherein The backside gate etch stop layer is made of metal, and wherein the metal is cobalt, titanium, tungsten, ruthenium, tantalum, aluminum or molybdenum.

4. The semiconductor device according to claim 1, wherein The plurality of first nanostructures overlap the backside gate contact.

5. The semiconductor device according to claim 1, wherein The first gate stack includes one or more gate dielectrics between a first gate electrode of the first gate stack and the plurality of first nanostructures, wherein the one or more gate dielectrics are further disposed between the backside gate etch stop layer and the first gate electrode.

6. The semiconductor device according to claim 1, further comprising a backside etch stop layer contacting a surface of the backside gate etch stop layer opposite to the first gate stack, wherein The backside gate contact extends through the backside etch stop layer.

7. A method of forming a semiconductor device, comprising: forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked; exposing a back side of a first gate stack of the first transistor, wherein exposing the back side of the first gate stack comprises removing the semiconductor substrate; forming a backside gate etch stop layer on the backside of the first gate stack; patterning a contact opening through the backside gate etch stop layer to expose the first gate stack; and A backside gate contact is formed in the contact opening, wherein the backside gate contact extends through the backside gate etch stop layer to be electrically connected to the first gate stack.

8. The method according to claim 7, wherein: The first gate stack includes a gate dielectric and a gate electrode, and wherein forming the backside gate etch stop layer includes blanket depositing the backside gate etch stop layer over the gate dielectric.

9. The method according to claim 7, wherein: The first gate stack includes a gate dielectric and a gate electrode, and wherein forming the backside gate etch stop layer includes selectively depositing the backside gate etch stop layer on the gate electrode.

10. A method of forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating semiconductor nanostructures and dummy nanostructures; forming a lower source / drain region, wherein the lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain region; forming an upper source / drain region above the lower source / drain region, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain region; replacing the dummy nanostructure with a lower gate stack surrounding the lower semiconductor nanostructure and an upper gate stack surrounding the upper semiconductor nanostructure; exposing a back side of the lower gate stack; depositing a metal-containing backside gate etch stop layer on the backside of the lower gate stack; and A backside gate contact is formed extending through the metal-containing backside gate etch stop layer to be electrically connected to the lower gate stack, wherein the backside gate contact overlaps the lower semiconductor nanostructure and the upper semiconductor nanostructure.

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