Semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device which comprises an epitaxial structure, a first passivation layer, a second passivation layer and a gate metal structure, the first passivation layer is arranged on the epitaxial structure, the first passivation layer is provided with a through hole, and the through hole penetrates from the upper surface of the first passivation layer to the lower surface of the first passivation layer; the side wall, at the through hole, of the first passivation layer is a bent side wall, the second passivation layer is located in the through hole and covers the bent side wall of the first passivation layer, and the gate metal structure is connected with the epitaxial structure through the through hole. By means of the arrangement, the formed semiconductor device has smaller gate length, and the stability of the semiconductor device is improved.

Description

Semiconductor device and method for manufacturing the same Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] The GaN-based High-Electron Mobility Transistor (HEMT) is a commonly used semiconductor device. In the fabrication of compound semiconductor RF power devices, gate electrode fabrication is a critical process, and the processing of T-type gates is particularly challenging. Currently, in deep-submicron compound semiconductor device fabrication, T-type gates are generally fabricated using electron beam lithography and multilayer resists. A T-type gate is a T-shaped gate electrode with a mushroom-shaped cross-section. This allows for a narrow gate root at the bottom, where the gate contacts the semiconductor surface, to increase the device's cutoff frequency, while a wide gate cap at the top reduces gate resistance. In actual fabrication, I-line UV exposure lithography can achieve gate line widths as low as approximately 0.35 microns, while electron beam lithography can achieve line widths below 0.1 microns. However, due to equipment limitations, electron beam lithography can only perform point-by-point scanning, resulting in extremely low processing efficiency.

[0003] Currently, manufacturers are limited by the limitations of stepper lithography machines, preventing them from further reducing the gate length (i.e., gate width). The resulting gate line width cannot meet current usage requirements. Therefore, how to further reduce the gate length using traditional i-line stepper lithography machines has become a technical challenge that those skilled in the art urgently need to solve.

[0004] It should be noted that the information disclosed in this background technology section is only intended to increase understanding of the overall background of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The present invention provides a semiconductor device comprising an epitaxial structure, a first passivation layer, a second passivation layer, and a gate metal structure. The first passivation layer is disposed on the epitaxial structure, the first passivation layer having a through hole, the through hole extending from the upper surface of the first passivation layer to the lower surface of the first passivation layer, and the sidewalls of the first passivation layer at the through hole are curved sidewalls. The second passivation layer is located within the through hole and covers the curved sidewalls of the first passivation layer. The gate metal structure is connected to the epitaxial structure through the through hole. The size of the epitaxial structure exposed by the through hole is at least 70 nm. The size of the epitaxial structure exposed by the through hole is less than or equal to 250 nm.

[0006] The present invention also provides a semiconductor device comprising an epitaxial structure, a first passivation layer, a second passivation layer, and a gate metal structure. The first passivation layer is disposed on the epitaxial structure, the first passivation layer having a through hole and a groove, the through hole extending from the upper surface of the first passivation layer to the lower surface of the first passivation layer, and the groove is spaced apart from the epitaxial structure. The gate metal structure is connected to the epitaxial structure via the through hole. The second passivation layer is located within the groove of the first passivation layer. The sidewalls of the first passivation layer at the groove are curved sidewalls. The size of the epitaxial structure exposed by the through hole is at least 70 nm. The size of the epitaxial structure exposed by the through hole is less than or equal to 250 nm.

[0007] The present invention also provides a method for preparing a semiconductor device, which includes the following steps: depositing a first passivation layer on an epitaxial structure; removing the periphery of the first passivation layer, and providing a metal layer on the epitaxial structure, wherein the metal layer is connected to the outer wall of the first passivation layer; removing part of the first passivation layer to form a first pit, wherein the distance between the bottom of the first pit and the epitaxial structure is greater than 0; depositing a second passivation layer on the first pit and the first passivation layer, wherein the second passivation layer has a second pit, and the second pit is located on the first pit; and dry etching the second passivation layer until the epitaxial structure corresponding to the bottom of the first pit is exposed.

[0008] An embodiment of the present invention provides a semiconductor device and a method for preparing the same. By setting a curved sidewall, the T-shaped gate manufactured using a traditional stepper lithography machine can simultaneously take into account the gate length, production capacity requirements and device performance requirements, thereby enabling the semiconductor device to have a smaller gate length and improve the performance of the semiconductor device.

[0009] Other features and beneficial effects of the present invention will be described in the following description, and some of the technical features and beneficial effects can be obviously derived from the description or understood by practicing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0011] FIG1 is a schematic structural diagram of a semiconductor device provided by a first embodiment of the present invention;

[0012] FIG2 is a partial enlarged schematic diagram of area A in FIG1 ;

[0013] 3 is a schematic structural diagram of a semiconductor device provided by a second embodiment of the present invention;

[0014] FIG4 is a partial enlarged schematic diagram of area A in FIG3 ;

[0015] 5 to 11 are schematic structural diagrams of the semiconductor device shown in FIG3 at various stages in the manufacturing process;

[0016] 12 is a schematic structural diagram of a semiconductor device provided in a third embodiment of the present invention;

[0017] 13 is a schematic structural diagram of a semiconductor device provided in accordance with a fourth embodiment of the present invention;

[0018] 14 is a schematic structural diagram of a semiconductor device provided in accordance with a fifth embodiment of the present invention;

[0019] FIG15 is a schematic structural diagram of a semiconductor device provided in accordance with a sixth embodiment of the present invention.

[0020] Reference numerals:

[0021] 10-substrate; 12-epitaxial structure; 14-first passivation layer; 141-through hole; 142-curved sidewall; 1421-first curved sidewall; 1422-second curved sidewall; 143-recess; 144-inner wall; 16-second passivation layer; 162-convex sidewall; 18-gate metal structure; 20-source metal structure; 22-drain metal structure; 24-nucleation layer; 26-buffer layer; 28-insertion layer; 30-barrier layer; 32-capping layer; 3 4 - first pit; 36 - second pit; 38 - inner recess; 40 - third passivation layer; 42 - first passivation sublayer; 44 - second passivation sublayer; X1 - dimension of the epitaxial structure exposed by the through-hole; Z1 - central symmetry line; M1 - first intersection point; M2 - second intersection point; D1 - first line segment; D2 - second line segment; C1 - angle between the first line segment and the central symmetry line; C2 - angle between the second line segment and the central symmetry line; H1 - first vertical distance; H2 - second vertical distance. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0024] Referring to Figures 1 and 2 , Figure 1 is a schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention, and Figure 2 is a partially enlarged schematic diagram of region A in Figure 1 . To achieve at least one of the aforementioned advantages, or other advantages, one embodiment of the present invention provides a semiconductor device that can be used in AlGaN or GaN HEMT devices, as well as in GaAs pHEMT devices and other devices, depending on actual needs. Furthermore, it can be used in AlGaN or GaN HEMT or MISHEMT structures, and so on.

[0025] As shown in the figure, the semiconductor device includes an epitaxial structure 12 , a first passivation layer 14 , a second passivation layer 16 and a gate metal structure 18 .

[0026] The epitaxial structure 12 can be disposed on a substrate 10. The substrate 10 can be a Si substrate, a SiC substrate, or the like. The epitaxial structure 12 includes a III-nitride heterojunction. In some embodiments, the epitaxial structure 12 can include a nucleation layer 24, a buffer layer 26, an insertion layer 28, a barrier layer 30, and a capping layer 32 stacked sequentially on the substrate 10. The nucleation layer 24 can be made of AlN, the buffer layer 26 can be made of GaN, the insertion layer 28 can be made of AlN, the barrier layer 30 can be made of AlGaN, and the capping layer 32 can be made of GaN. The Al content in the AlGaN barrier layer 30 can range from 10% to 30%, and the thickness of the barrier layer 30 can range from 10 to 30 nm. It should be noted that some of the aforementioned structural layers are optional. For example, the AlN insertion layer 28 can be omitted, and the capping layer 32 can also be omitted.

[0027] The first passivation layer 14 is arranged on the epitaxial structure 12. The material of the first passivation layer 14 can be selected from at least one of the group consisting of silicon oxide, silicon nitride and silicon oxynitride. For example, the first passivation layer 14 can be a SiO2 layer. The first passivation layer 14 can be a single-layer structure or a multi-layer stacked structure. The thickness of the first passivation layer 14 can range from 50 to 200 nm. The first passivation layer 14 has a through hole 141, which is formed from the upper surface of the first passivation layer 14 to the lower surface of the first passivation layer 14 to expose the epitaxial structure 12 below. In the gate length direction, the size X1 of the epitaxial structure 12 exposed by the through hole 141 is at least 70 nm, that is, the gate length of the semiconductor device can be 70 nm when using a traditional stepper lithography machine. Current loss occurs as it flows from source to drain, and the gate length (the gate's dimension in the direction of the gate length) determines this loss. For example, this can reduce heat generation and power consumption in common devices like mobile phones; a narrower gate length reduces power consumption. It can also increase the device's cutoff frequency, enabling applications at higher frequencies. X1 in the figure represents the gate length (the gate's dimension in the direction of the gate length). X1 can range from 70 to 250 nm.

[0028] The sidewall of the first passivation layer 14 at the through hole 141 is a curved sidewall 142. The curved sidewall 142 refers to a sidewall that is not perpendicular to the upper surface of the epitaxial structure 12. For example, it can be a complete continuous arc-shaped sidewall, or it can be composed of n segments of arc-shaped sidewalls connected to each other, or it can be formed by connecting multiple short straight lines with different slopes, or it can be formed by combining multiple arc-shaped sidewalls and multiple short straight lines, etc. In the illustrated embodiment, the curved sidewall 142 is formed by connecting two segments of arc-shaped sidewalls. By setting the curved sidewall 142, the T-type gate manufactured can take into account the gate length, production capacity requirements and device performance requirements while using a traditional stepper lithography machine, so that the semiconductor device can have a smaller gate length and improve the performance of the semiconductor device.

[0029] The curved sidewall 142 includes a first curved sidewall 1421 and a second curved sidewall 1422. The upper and lower ends of the first curved sidewall 1421 are respectively connected to the second curved sidewall 1422 and the lower surface of the first passivation layer 14, while the upper and lower ends of the second curved sidewall 1422 are respectively connected to the upper surface of the first passivation layer 14 and the first curved sidewall 1421. The first curved sidewall 1421 is an arc cut from one circle, and the second curved sidewall 1422 is an arc cut from another circle. The radii of the two circles are different, that is, the curvature radii of the first curved sidewall 1421 and the second curved sidewall 1422 are different. The curvature radius of the first curved sidewall 1421 can range from 35 to 65 nm, and the curvature radius of the second curved sidewall 1422 must be greater than the curvature radius of the first curved sidewall 1421. The sidewall of the second passivation layer 16 at the through hole 141 is a convex sidewall 162. Compared with the curved sidewall 142, the convex sidewall 162 convexes toward the through hole 141. Compared with the convex sidewall 162, the curved sidewall 142 convexes toward the first passivation layer 16, that is, the two convex directions are different. The curvature radius of the convex sidewall 162 can range from 60 to 150 nm.

[0030] The outer convex side wall 162 is beneficial to the coverage of the gate metal structure 18, reducing the metal void problem caused by poor coverage, and can modulate the gate electric field distribution, reduce the gate edge field strength, and optimize the device reliability; the inner curved side wall 142 can increase the side area, which is beneficial to the diffusion and transport of various active groups to the thin film growth surface during vapor deposition, thereby improving the uniformity of the deposited film thickness of the second passivation layer 16 in the step area, and the curved side wall 142 formed by the non-through groove can effectively shorten the etching time, thereby making the semiconductor device have a smaller gate length.

[0031] The second passivation layer 16 is located within the through-hole 141 and is connected to the curved sidewall 142 of the first passivation layer 14. The material of the second passivation layer 16 can be at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The second passivation layer 16 can have a single-layer structure or a multi-layer stacked structure.

[0032] The gate metal structure 18 is connected to the epitaxial structure 12 via the through-hole 141. The gate metal structure can be in contact with the first passivation layer 14 and the second passivation layer 16 respectively. The gate metal structure 18 can be a T-shaped gate. In some embodiments, the gate metal structure 18 can also form a double T-shaped gate.

[0033] The semiconductor device further includes a source metal structure 20 and a drain metal structure 22. The source metal structure 20 and the drain metal structure 22 are disposed on the epitaxial structure 12, the source metal structure 20 and the drain metal structure 22 are disposed opposite to each other, and the gate metal structure 18 is located between the source metal structure 20 and the drain metal structure 22.

[0034] In some embodiments, as shown in FIG2 , the curved sidewall 142 has an inwardly concave arc shape, which can effectively increase the side surface area compared to the sidewall with a vertical shape, thereby facilitating the diffusion and transport of various active groups to the thin film growth surface during vapor deposition, thereby improving the uniformity of the film thickness of the second passivation layer 16 in different step areas and enhancing the stability of the semiconductor device.

[0035] Please refer to Figures 3 and 4. Figure 3 is a structural schematic diagram of the semiconductor device provided by the second embodiment of the present invention, and Figure 4 is a partially enlarged schematic diagram of area A in Figure 3. Compared with the semiconductor device shown in the first embodiment of Figure 1, the difference of the semiconductor device provided by the second embodiment is mainly that: a groove 143 is further provided on the first passivation layer 14, and the groove 143 has a spacing with the epitaxial structure 12, and the spacing is greater than 0. The second passivation layer 16 is arranged in the groove 143 of the first passivation layer 14. It should be noted that, compared with Figure 1, the groove 143 refers to the groove 143 space formed when the lower end of the curved side wall 142 and the epitaxial structure 12 have a spacing greater than 0, and the space is connected to the through hole 141.

[0036] In order to reduce the gate length of the semiconductor device, the sidewalls of the first passivation layer 14 at the groove 143 are curved sidewalls 142. The dimension X1 of the epitaxial structure 12 exposed by the through hole 141 is at least 70 nm, that is, the gate length is at least 70 nm. Optionally, X1 ranges from 70 to 250 nm. The first passivation layer 14 has an inner wall 144 at the through hole 141. The inner wall 144 can be perpendicular to the upper surface of the epitaxial structure 12. In some embodiments, the second passivation layer 16 does not cover the inner wall 144, but is located above the inner wall 144. The intersection of the central symmetry line Z1 of the through hole 141 and the horizontal plane where the upper surface of the first passivation layer 14 is located is defined as the first intersection M1. The line segment connecting the upper end point of the inner wall 144 and the first intersection M1 is the first line segment D1. The angle C1 between the first line segment D1 and the central symmetry line Z1 ranges from 10 to 15 degrees.

[0037] To further reduce the gate length of the semiconductor device, the first passivation layer 14 has a first curved sidewall 1421 and a second curved sidewall 1422 at the recess 143. Specifically, the curved sidewall 142 includes the first curved sidewall 1421 and the second curved sidewall 1422. The upper and lower ends of the first curved sidewall 1421 are connected to the second curved sidewall 1422 and the inner wall 144, respectively. The upper and lower ends of the second curved sidewall 1422 are connected to the upper surface of the first passivation layer 14 and the first curved sidewall 1421, respectively. The intersection point between the first curved sidewall 1421 and the second curved sidewall 1422 is defined as a second intersection point M2. The line segment connecting the second intersection point M2 and the first intersection point M1 is defined as a second line segment D2. The angle C2 between the second line segment D2 and the central symmetry line Z1 ranges from 20 to 33 degrees. Optionally, a first vertical distance H1 between the second intersection M2 and the central symmetry line Z1 is less than a second vertical distance H2 between the upper endpoint of the second curved sidewall 1422 and the central symmetry line Z1. The first vertical distance H1 ranges from 90 to 100 nm, and the second vertical distance H2 ranges from 100 to 125 nm. The spacing between the bottom of the groove 143 and the epitaxial structure 12 ranges from 10%h to 20%h, where h is the thickness of the first passivation layer 14. If this spacing is too small, due to machine stability considerations, a margin is left to prevent overetching due to machine etch rate drift (2%), which will completely etch the remaining dielectric layer, hindering the formation of the groove 143 structure. Furthermore, this structure is intended to reduce the number of etching passes on the surface of the epitaxial structure 12, thereby reducing damage. If the spacing is set too large, the thickness of the dielectric layer required to be etched during the through-etch of the second passivation layer 16 (the total thickness of the remaining etching amount of the first passivation layer 14 + the thickness of the second passivation layer 16) increases, hindering the formation of smaller gate lengths.

[0038] In some embodiments, the material of the first passivation layer 14 includes SiN x The material of the second passivation layer 16 includes SiN y , y>x. Thus, the N:Si ratio of the second passivation layer 16 is greater than that of the first passivation layer 14. The larger the N:Si ratio, the faster the etching rate and the denser the SiN x As the first surface layer of the contact epitaxial structure 12, it has a better passivation effect and can reduce negative effects such as interface leakage. In addition, due to the SiN y It is set in the groove 143 and does not directly contact the epitaxial structure 12. y The slightly lower density of the second passivation layer 16 effectively increases the etching rate without affecting the interface state between the SiN and epitaxial structure 12, thereby shortening the etching time and thus achieving the goal of reducing the gate length. In addition, since the second passivation layer 16 does not directly contact the first passivation layer 14, surface damage to the epitaxial structure 12 caused by multiple over-etching can be reduced.

[0039] In some embodiments, as shown in FIG4 , the second passivation layer 16 has an outward convex arc shape. Compared with a right-angled or concave shape, the overall contour of the second passivation layer 16 is smoother, thereby enabling better coverage of subsequent metals, reducing void problems between the metal and the second passivation layer 16 and the first passivation layer 14, optimizing the nearby electric field distribution, reducing the gate edge field strength, and improving the reliability of semiconductor devices.

[0040] Please refer to Figures 5 to 11, which are schematic diagrams of the structure of the semiconductor device shown in Figure 3 at various stages during the manufacturing process. As shown in the figures, the manufacturing process of the semiconductor device is as follows:

[0041] First, as shown in FIG5 , an epitaxial structure 12 is formed on a substrate 10. Specifically, using MOCVD epitaxial growth technology, an AlN nucleation layer 24, a GaN buffer layer 26, an AlN insertion layer 28, an AlGaN barrier layer 30, and a GaN cap layer 32 are sequentially grown on the substrate 10. The Al content in the AlGaN barrier layer 30 can range from 10% to 30%, and the thickness of the barrier layer 30 can range from 10 to 30 nm.

[0042] Next, as shown in Figure 6, a first SiN passivation layer 14 is deposited on the epitaxial structure 12 using a PECVD machine. The growth temperature can be 200-400°C, using primary gases such as SiH₄, NH₃, N₂, and He. The deposited SiN thickness T is approximately 50-200 nm. After deposition, an RTA machine is used for annealing at a temperature of 400-600°C, using primary gas N₂, for a duration of 0-300 seconds.

[0043] Then, as shown in FIG7 , the periphery of the first passivation layer 14 is removed, and a metal layer is then provided on the epitaxial structure 12. The metal layer is connected to the outer wall of the first passivation layer 14 to prepare the source metal structure 20 and the drain metal structure 22. A stepper lithography machine is used to perform the resist coating, exposure, and development steps, and the electrode area pattern is patterned. Then, an electron beam evaporation machine is used to deposit an ohmic metal. The ohmic metal can use a stacked metal structure of Ti / Pt / Au / Ti. After the evaporation is completed, metal stripping is performed to remove excess metal. Then, an RTA machine is used to perform ohmic annealing at 400-800°C in an N2 atmosphere to alloy the ohmic metal and obtain the source metal structure 20 and the drain metal structure 22.

[0044] Then, as shown in Figure 8, a portion of the first passivation layer 14 is removed, forming a first pit 34 (the groove 143 of the first passivation layer 14 is part of the remaining portion of the first pit 34). The gap between the bottom of the first pit 34 and the epitaxial structure 12 is greater than 0. Specifically, a conventional i-line lithography machine is used to create a gate trench pattern with a size of approximately 160-180 nm. The first passivation layer 14 is then etched using ICP to form the first pit 34, a nearly arc-shaped submicron gate trench. The photoresist is then removed using a photoresist stripper. In other words, the first pit 34 is formed using a lithography process using a stepper lithography machine.

[0045] Then, as shown in FIG9 , a second passivation layer 16 is deposited on the first pit 34 and the first passivation layer 14. The second passivation layer 16 has a second pit 36, and the second pit 36 ​​is located on the first pit 34. Specifically, a PECVD machine is used to deposit the second passivation layer 16 of SIN, with a growth temperature of 200-400°C, the main gases being SiH4, NH3, N2, and He, and the deposition thickness being approximately 5-200nm. Since the first pit 34 of the first passivation layer 14 does not penetrate to the epitaxial structure 12, the non-penetrating etching can reduce the size of the first pit 34 of the first passivation layer 14, thereby making the second pit 36 ​​of the second passivation layer 16 smaller in size, providing a larger process window, and ultimately making the gate length of the semiconductor device smaller. In addition, the surface of the epitaxial structure 12 can be prevented from being etched and damaged.

[0046] Then, as shown in FIG10 , the second passivation layer 16 is dry-etched until the epitaxial structure 12 corresponding to the bottom of the first pit 34 is exposed. Specifically, the second passivation layer 16 can be etched by ICP to form a gate groove; the etching gas is CF3 at 40-200 sccm. 4 , 10-50 sccm of N2; upper electrode RF power 100-400W, lower electrode RF power 0-20W. After completing the dry etching step of the second passivation layer 16, a through hole 141 is formed in the first passivation layer 14. The through hole 141 extends from the upper surface of the first passivation layer 14 to the lower surface of the first passivation layer 14, exposing the epitaxial structure 12. The dimension X1 of the epitaxial structure 12 exposed by the through hole 141 is at least 70nm. The sidewalls of the finally formed first passivation layer 14 at the through hole 141 are curved sidewalls 142. Curved sidewalls 142 refer to sidewalls that are not perpendicular to the upper surface of the epitaxial structure 12. For example, they can be a complete continuous curved sidewall, or they can be composed of n connected curved sidewalls, or they can be formed by connecting multiple short straight lines of different slopes, or they can be formed by combining multiple curved sidewalls and multiple short straight lines, etc. The second passivation layer 16 is connected to the curved sidewall 142.

[0047] Finally, as shown in FIG. 11 , a gate metal structure 18 is disposed on the first passivation layer 14 and the second passivation layer 16 . The gate metal structure 18 is connected to the epitaxial structure 12 through a through hole 141 .

[0048] The above is only one disclosed method for manufacturing the semiconductor device shown in FIG3 . The present invention is not limited to this method and is merely used to illustrate one method for manufacturing a semiconductor device. In addition, when etching the first passivation layer 14 , a through-etching step is performed to form the semiconductor device shown in FIG1 .

[0049] Please refer to Figure 12, which is a schematic diagram of the structure of a semiconductor device provided by a third embodiment of the present invention. Compared to the semiconductor device shown in Figure 1, the semiconductor device provided by this embodiment differs primarily in that the curved sidewall 142 of the first passivation layer 14 is a single arc-shaped structure that bulges (protrudes) toward the through hole 141, whereas the curved sidewall 142 of the first embodiment is concave.

[0050] Please refer to Figure 13, which is a schematic diagram of the structure of a semiconductor device provided by the fourth embodiment of the present invention. Compared with the semiconductor device shown in Figure 3, the semiconductor device provided by this embodiment is different mainly in that: the upper surface of the epitaxial structure 12 has an inwardly recessed inner recess 38 at the through hole 141. The inner recess 38 can be etched using chlorine-based ICP etching or RIE etching to a depth range of 1-3nm. The inner recess 38 can suppress the threshold voltage negative drift problem caused by the gate dielectric, improve the gate's control over the channel, and enhance transconductance. By controlling the etching depth, the interface state density between the passivation layer and the epitaxial structure 12 can be reduced at a small etching depth (1-3nm), weakening the current collapse effect.

[0051] Please refer to Figure 14, which is a schematic diagram of the structure of a semiconductor device provided by the fifth embodiment of the present invention. Compared with the semiconductor device shown in Figure 3, the semiconductor device provided by this embodiment mainly differs in that a third passivation layer 40 is further provided on the surface of the first passivation layer 14, the second passivation layer 16, and the epitaxial structure 12, and the gate metal structure 18 is provided on the third passivation layer 40. The material of the third passivation layer 40 can be Si3N4, HfO2, Al2O3, etc., and the deposition method can be ALD deposition with a thickness of 3-10nm. By introducing the third passivation layer 40 of the under-gate insulating dielectric, a metal-insulator-semiconductor MIS-HEMT structure is formed, which can significantly reduce gate leakage current, increase the device's breakdown voltage, increase the device's gate voltage swing, and improve linearity. At the same time, the gate dielectric acts as a surface passivation to stabilize the surface state of the semiconductor material, suppress current collapse, and enhance the long-term reliability of the device.

[0052] Please refer to Figure 15, which is a schematic structural diagram of a semiconductor device provided by the sixth embodiment of the present invention. Compared with the semiconductor device shown in Figure 3, the difference of the semiconductor device provided by this embodiment is mainly that: the first passivation layer 14 is a multi-layer structure, which includes a first passivation sublayer 42 and a second passivation sublayer 44. The first passivation sublayer 42 is located between the second passivation sublayer 44 and the epitaxial structure 12. By adjusting the film quality of the first passivation sublayer 42 and using SiN with better density as the bottom layer (that is, the density of the first passivation sublayer 42 is greater than that of the second passivation sublayer 44), its etching rate is slower than that of the second passivation sublayer 44, which is conducive to controlling the etching depth and improving the controllability of the non-through etching process. In addition, compared with the single-layer first passivation layer 14, this structure can use a thin first passivation sublayer 42 to improve the device passivation and interface optimization effects, and the second passivation sublayer 44 still uses the original structure. In this way, the device passivation effect can be optimized without having a significant impact on the etching process (mainly the etching rate), and the surface state density at the interface between the epitaxial structure 12 and the passivation layer can be changed to achieve the effect of suppressing current collapse.

[0053] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: epitaxial structure; A first passivation layer is disposed on the epitaxial structure, wherein the first passivation layer has a through hole, the through hole penetrates from the upper surface of the first passivation layer to the lower surface of the first passivation layer, and the side wall of the first passivation layer at the through hole is a curved side wall; a second passivation layer, located in the through hole and covering the curved sidewall of the first passivation layer; A gate metal structure is connected to the epitaxial structure through the through hole.

2. The semiconductor device according to claim 1, wherein: The curved side wall includes a first curved side wall and a second curved side wall, two ends of the first curved side wall are respectively connected to the second curved side wall and the lower surface of the first passivation layer, two ends of the second curved side wall are respectively connected to the upper surface of the first passivation layer and the first curved side wall, and the first curved side wall and the second curved side wall have different curvature radii.

3. The semiconductor device according to claim 2, wherein: The curvature radius of the first curved side wall is in the range of 35-65 nm, and the curvature radius of the second curved side wall is greater than the curvature radius of the first curved side wall.

4. The semiconductor device according to claim 1, wherein: The sidewall of the second passivation layer at the through hole is a convex sidewall, which protrudes toward the through hole compared to the curved sidewall, and the curved sidewall protrudes toward the first passivation layer compared to the convex sidewall, and the curvature radius of the convex sidewall ranges from 60 to 150 nm.

5. The semiconductor device according to claim 1, wherein: The material of the first passivation layer and the second passivation layer is at least one selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride; The size of the epitaxial structure exposed by the through hole is at least 70 nm.

6. The semiconductor device according to claim 1, wherein: The thickness of the first passivation layer is in the range of 50 to 200 nm; The size of the epitaxial structure exposed by the through hole is less than or equal to 250 nm.

7. A semiconductor device, characterized in that: The semiconductor device comprises: epitaxial structure; A first passivation layer is disposed on the epitaxial structure, wherein the first passivation layer has a through hole and a groove, wherein the through hole penetrates from the upper surface of the first passivation layer to the lower surface of the first passivation layer, and the groove is spaced apart from the epitaxial structure; a gate metal structure, wherein the gate metal structure is connected to the epitaxial structure through the through hole; a second passivation layer, located in the groove of the first passivation layer; Wherein, the sidewall of the first passivation layer at the groove is a curved sidewall.

8. The semiconductor device according to claim 7, wherein: The first passivation layer is a single-layer structure or a multi-layer stacked structure; the size range of the epitaxial structure exposed by the through hole is at least 70 nm.

9. The semiconductor device according to claim 7, wherein: The first passivation layer has an inner wall at the through hole, defining the intersection of the central symmetry line of the through hole and the horizontal plane where the upper surface of the first passivation layer is located as the first intersection, and the line segment connecting the upper end point of the inner wall and the first intersection as the first line segment, and the angle between the first line segment and the central symmetry line is in the range of 10~15°.

10. The semiconductor device according to claim 9, wherein: The curved side wall includes a first curved side wall and a second curved side wall, the two ends of the first curved side wall are respectively connected to the second curved side wall and the inner wall, the two ends of the second curved side wall are respectively connected to the upper surface of the first passivation layer and the first curved side wall, the connection intersection of the first curved side wall and the second curved side wall is defined as the second intersection, the line segment connecting the second intersection and the first intersection is the second line segment, and the angle range between the second line segment and the central symmetry line is 20~33°.

11. The semiconductor device according to claim 10, wherein: A first vertical distance from the second intersection point to the central symmetry line is smaller than a second vertical distance from the upper end point of the second arc-shaped side wall to the central symmetry line.

12. The semiconductor device according to claim 11, characterized in that: The first vertical distance ranges from 90 to 100 nm, and the second vertical distance ranges from 100 to 125 nm.

13. The semiconductor device according to claim 7, wherein: The thickness of the first passivation layer is in the range of 50-200 nm; and the size of the epitaxial structure exposed by the through hole is less than or equal to 250 nm.

14. The semiconductor device according to claim 7, wherein: The distance between the bottom of the groove and the epitaxial structure is in the range of 10%h to 20%h, where h is the thickness of the first passivation layer.

15. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a substrate, the epitaxial structure is disposed on the substrate, and the epitaxial structure includes a III-nitride heterojunction.

16. The semiconductor device according to claim 7, wherein: The material of the first passivation layer includes SiN x The material of the second passivation layer includes SiN y , y>x.

17. The semiconductor device according to claim 7, wherein: The semiconductor device further includes a third passivation layer, the third passivation layer covers the first passivation layer, the second passivation layer and the epitaxial structure, and the gate metal structure is located on the third passivation layer.

18. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises the following steps: depositing a first passivation layer on the epitaxial structure; removing a portion of the first passivation layer to form a first pit, wherein the distance between the bottom of the first pit and the epitaxial structure is greater than 0; Depositing a second passivation layer on the first pit and the first passivation layer, wherein the second passivation layer has a second pit, and the second pit is located on the first pit; The second passivation layer is dry-etched until the epitaxial structure corresponding to the first pit is exposed.

19. The method for preparing a semiconductor device according to claim 18, characterized in that: After completing the step of dry etching the second passivation layer, a through hole is formed in the first passivation layer, and the through hole penetrates from the upper surface of the first passivation layer to the lower surface of the first passivation layer to expose the epitaxial structure. The size of the epitaxial structure exposed by the through hole is at least 70nm.

20. The method for preparing a semiconductor device according to claim 19, characterized in that: The sidewall of the first passivation layer at the through hole is a curved sidewall.

21. The method for preparing a semiconductor device according to claim 20, characterized in that: The curved side wall includes a first curved side wall and a second curved side wall, two ends of the first curved side wall are respectively connected to the second curved side wall and the lower surface of the first passivation layer, two ends of the second curved side wall are respectively connected to the upper surface of the first passivation layer and the first curved side wall, and the first curved side wall and the second curved side wall have different curvature radii.

22. The method for preparing a semiconductor device according to claim 18, wherein: The step of forming the second passivation layer includes: depositing the second passivation layer on the first pit and the first passivation layer by means of a chemical vapor deposition machine.

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