High-precision low-jitter waveform generation method and device based on FPGA

Abstract

The invention provides a high-precision low-jitter waveform generation method and device based on an FPGA, and relates to the technical field of signal processing. According to the phase accumulated value obtained through preprocessing, calculation is carried out according to a preset mathematical model, and a model output value is determined; performing phase comparison according to the phase accumulated value, and performing waveform selection in combination with a model output value to obtain an initial output waveform; according to the phase accumulated value, generating a sine wave through a preset CORDIC IP; according to the initial output waveform and the sine wave, waveform selection is carried out, and a secondary output waveform is determined; and performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal, and outputting a final waveform. By combining the high-precision characteristic of DDS frequency control and the flexibility of edge interpolation, low-jitter pulse waves with adjustable parameters such as edge time, pulse width, duty ratio and degree of symmetry are generated; advantages of linear interpolation and nonlinear interpolation are integrated, and edge jitter of pulse signals is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular, to a high-precision and low-jitter waveform generation method and device based on FPGA. Background Art

[0002] In traditional pulse wave generation schemes, there are mainly two schemes to achieve this; one is a DDS (Direct Digital Frequency Synthesis) signal generating device, which stores waveforms in a wave table, and then uses the high-bit truncation of the phase accumulator as the address index to read waveform data. By adjusting the frequency control word, signals of different frequencies can be generated, and it is easy to achieve precise control of frequency and phase; the other is real-time generation of waveform data. The traditional real-time pulse wave generation scheme is to use a counter or other means to generate a pulse width of a certain length, and insert straight lines (linear interpolation) with different slopes at the edges to generate edges at different times, and real-time generate a pulse wave data with adjustable pulse width and edge.

[0003] For the former method, as shown in Figure 2 it has the following defects: The method is limited to the generation of signals with only parameters such as frequency and phase, such as sine waves, cosine waves, and sawtooth waves. For the configuration of these parameters, only the initial phase and frequency control word of the DDS need to be changed, and there is no need to modify the wave table. However, to generate square waves and pulse waves with adjustable edge time, pulse width, symmetry, duty cycle, etc., the wave table needs to be refreshed in real time, lacking flexibility. And a high-precision interpolation wave table requires a large amount of storage resources, especially high resource occupancy on platforms such as FPGA. Moreover, traditional DDS can also be used for the generation of square waves, but due to the excessive step of the edge of the square wave waveform lookup table, obvious overshoot occurs, as shown in Figure 2 and, due to the limited length of the waveform lookup table, when the output waveform frequency is very low, each waveform data point will last for multiple clock cycles, and obvious staircase or sawtooth phenomena will occur as shown in the following figure, thereby introducing some additional noise: as shown in Figure 3 For the latter method, it has the following disadvantages: It loses the advantage of precise frequency adjustment of DDS, and for ordinary linear interpolation, in the case of a small edge time, due to the too large slope and insufficient response time of the DAC, different degrees of jitter and overshoot phenomena will occur, as shown in Figure 4 In addition, the CORDIC algorithm can calculate sine and cosine values in real time. Traditional DDS combined with the CORDIC algorithm is used for sine wave generation. Traditional CORDIC is mainly used for sine wave generation, but it lacks optimization for the generation of square waves, pulse waves, and ramp waves. Therefore, the present application proposes a high-precision and low-jitter waveform generation method based on FPGA to at least partially solve the problems that may exist in the prior art. Summary of the Invention

[0004] To overcome the above problems or at least partially solve the above problems, an embodiment of the present invention provides a high-precision and low-jitter waveform generation method and device based on FPGA.

[0005] The embodiments of the present invention are implemented as follows: An embodiment of the present application provides a high-precision and low-jitter waveform generation method based on FPGA, including: Calculating according to a preset mathematical model based on the phase accumulation value obtained by preprocessing to determine the model output value; Performing phase comparison according to the phase accumulation value, and combining with the model output value to perform waveform selection to obtain an initial output waveform; and generating a sine wave through a preset CORDIC IP according to the phase accumulation value; Performing waveform selection according to the initial output waveform and the sine wave to determine a secondary output waveform; Performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal to output a final waveform.

[0006] In some embodiments of the present invention, before calculating according to the phase accumulation value obtained by preprocessing according to a preset mathematical model to determine the model output value, a preprocessing step is further included: Accumulating according to a preset rule by combining a preset reference clock signal and a preset frequency control value ftw to obtain an increasing number; Performing phase overflow detection through the increasing number to determine the phase accumulation value.

[0007] In some embodiments of the present invention, calculating according to the phase accumulation value obtained by preprocessing according to a preset mathematical model to determine the model output value includes: According to the phase accumulation value obtained by preprocessing, it is divided into four parts: rising edge, high level, falling edge, and low level; Interpolating according to the edges of the waveform in different cases. When the edge time is large and not enough to cause a step overshoot, linear interpolation is used.

[0008] In some embodiments of the present invention, it further includes: when the edge time is small, resulting in overshoot or jitter, using a sine 1 / 4 cycle waveform for non-linear interpolation.

[0009] In some embodiments of the present invention, interpolating according to the edges of the waveform in different cases. When the edge time is large and not enough to cause a step overshoot, using linear interpolation includes: Performing linear interpolation through a mathematical model transformed by an interpolation method, where the mathematical model is: In the formula, A is the peak value of the waveform, a is the value at the rising edge of the waveform, b is the value at the falling edge of the waveform, h is the value at the high level, T is the period of the generated signal, m is the bit width of the phase accumulator; x is the phase accumulator; n is the number of bits shifted left when the CORDIC inputs fixed-point radian data; the frequency of the generated signal is: f x = 1 / T; when the CORDIC inputs fixed-point radian data: CORDIC is the iteration count calculation model.

[0010] In some embodiments of the present invention, when the edge time is small, resulting in overshoot or jitter, using a sine 1 / 4 cycle waveform for non-linear interpolation, including: Performing non-linear interpolation through a mathematical model transformed by interpolation, where the mathematical model is: Since the rising edge is the function image of the first 1 / 4 cycle of y = sin(x), therefore: Similarly, it can be obtained that: In summary, it can be obtained that: In the formula, A is the peak value of the waveform, a is the value at the rising edge of the waveform, b is the value at the falling edge of the waveform, h is the value at the high level, T is the period of the generated signal, m is the bit width of the phase accumulator; x is the phase accumulator; n is the number of bits shifted left when the CORDIC inputs fixed-point radian data; the frequency of the generated signal is: f x = 1 / T; when the CORDIC inputs fixed-point radian data: CORDIC is the iteration count calculation model.

[0011] In some embodiments of the present invention, performing phase comparison according to the phase accumulation value, and combining with the model output value to perform waveform selection to obtain an initial output waveform; and generating a sine wave according to the phase accumulation value through a preset CORDIC IP, including: Obtaining a sine wave according to the phase accumulation value through CORDIC as the iteration count calculation model, where the CORDIC iteration count calculation model is: In the formula, K n is the constant gain, A is the peak value of the waveform, n is the number of bits shifted left when the CORDIC inputs fixed-point radian data; x is the phase accumulator.

[0012] In some embodiments of the present invention, obtaining an increment number by accumulating according to a preset reference clock signal in combination with a preset frequency control value ftw according to a preset rule includes: According to the preset frequency control value ftw, accumulate ftw once every other reference clock cycle to obtain an increment number, where the frequency calculation formula is: In the formula, m is a phase accumulator.

[0013] The embodiments of the present application also provide a high-precision and low-jitter waveform generation device based on FPGA, including: A phase processing module, configured to calculate according to a preset mathematical model based on the phase accumulation value obtained by preprocessing to determine a model output value, including: when the edge time is small, resulting in overshoot or jitter, using a sine 1 / 4 cycle waveform for non-linear interpolation; A waveform comparison module, configured to perform phase comparison according to the phase accumulation value, and combine the model output value to perform waveform selection to obtain an initial output waveform; and generate a sine wave through a preset CORDIC IP according to the phase accumulation value; A waveform selection module, configured to perform waveform selection according to the initial output waveform and the sine wave to determine a secondary output waveform; A waveform data conversion module, configured to perform digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal to output a final waveform.

[0014] An electronic device includes a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the computer program is executed by the processor, the above-mentioned high-precision and low-jitter waveform generation method based on FPGA is implemented.

[0015] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned high-precision and low-jitter waveform generation method based on FPGA is implemented.

[0016] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects: Calculate the model output value according to the phase accumulation value obtained by preprocessing and in accordance with a preset mathematical model; perform phase comparison based on the phase accumulation value, and in combination with the model output value, perform waveform selection to obtain an initial output waveform; generate a sine wave according to the phase accumulation value through a preset CORDIC IP; perform waveform selection based on the initial output waveform and the sine wave to determine a secondary output waveform; perform digital-to-analog conversion based on the secondary output waveform and a preset reference clock signal to output a final waveform. By combining the high-precision characteristics of DDS frequency control with the flexibility of edge interpolation, generate a low-jitter pulse wave with adjustable parameters such as edge time, pulse width, duty cycle, and symmetry; integrate the advantages of linear interpolation and non-linear interpolation to effectively reduce the edge jitter of the pulse signal. Description of the Drawings

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a flowchart of the steps of a method for generating a high-precision and low-jitter waveform based on FPGA provided by an embodiment of the present invention; Figure 2 It is a waveform diagram generated by a traditional DDS in the prior art; Figure 3 It is an obvious step or sawtooth phenomenon that occurs when waveform data points generated by a traditional DDS in the prior art continue for multiple clock cycles; Figure 4 It is the phenomenon of different degrees of jitter and overshoot generated by ordinary linear interpolation in the prior art; Figure 5 It is a system structure block diagram of a method for generating a high-precision and low-jitter waveform based on FPGA provided by an embodiment of the present invention; Figure 6 It is a specific implementation system structure block diagram of a method for generating a high-precision and low-jitter waveform based on FPGA provided by an embodiment of the present invention; Figure 7 It is a non-linear interpolation waveform diagram of a method for generating a high-precision and low-jitter waveform based on FPGA provided by an embodiment of the present invention; Figure 8 It is a linear interpolation waveform diagram of a method for generating a high-precision and low-jitter waveform based on FPGA provided by an embodiment of the present invention; Figure 9The waveform diagram without any interpolation in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 10 The waveform diagram with a relatively small edge time of linear interpolation in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 11 The waveform diagram with a relatively small edge time of non-linear sine interpolation in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 12 The waveform diagram with a relatively large edge time of non-linear interpolation in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 13 The waveform diagram with a relatively large edge time of linear interpolation in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 14 The waveform diagram with high and low levels set to 0 in the actual test of a high-precision and low-jitter waveform generation method based on FPGA provided by an embodiment of the present invention; Figure 15 The structural schematic diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0020] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following various embodiments and the various features in the embodiments can be combined with each other.

[0021] Please refer to Figure 1 , the embodiment of the present invention provides a step flowchart of a high-precision and low-jitter waveform generation method based on FPGA, and the method includes: Step S100: Calculate according to a preset mathematical model based on the phase accumulation value X obtained by preprocessing to determine the model output value; Step S200: Perform phase comparison according to the phase accumulation value X, and combine with the model output value to perform waveform selection to obtain an initial output waveform; and generate a sine wave through a preset CORDIC IP according to the phase accumulation value X; Step S300: Perform waveform selection based on the initial output waveform and the sine wave to determine the secondary output waveform; Step S400: Perform digital-to-analog conversion based on the secondary output waveform and the preset reference clock signal f c , and output the final waveform.

[0022] In this embodiment, the high-precision and low-jitter waveform generation method based on FPGA has obvious advantages. It gets rid of the limitations of the traditional DDS scheme, such as inflexible wave table refreshing and high resource occupancy when generating complex pulse waves, as well as overshoot and staircase noise in square wave generation. At the same time, it overcomes the disadvantages of the traditional real-time generation scheme, such as the inability to adjust the precise frequency, and easy jitter and overshoot when the edge time is small. Through a unique step process, calculate according to the preset mathematical model based on the phase accumulation value, combine phase comparison and waveform selection, then generate a sine wave-assisted waveform selection with the preset CORDIC IP, and finally output the final waveform through digital-to-analog conversion, realizing high-precision and low-jitter generation of various waveforms (including square waves, pulse waves, etc.), taking into account precise frequency control and flexible waveform adjustment, and effectively solving the problems existing in the traditional scheme. Specifically, the present invention proposes a low-jitter basic digital signal generation method based on FPGA, which realizes the generation of low-jitter pulse waves with adjustable parameters such as edge time, pulse width, duty cycle, and symmetry by combining the high-precision characteristics of DDS frequency control and the flexibility of edge interpolation. This method adopts a conditional branch selection interpolation method, integrating the advantages of linear interpolation and non-linear interpolation, and effectively reducing the edge jitter of pulse signals.

[0023] In an embodiment of the present invention, a high-precision and low-jitter waveform generation method based on FPGA, wherein, before the step S100 described above "determine the model output value according to the phase accumulation value X obtained by preprocessing according to the preset mathematical model", there is also a preprocessing step: According to the preset reference clock signal f c , combine with the preset frequency control value ftw, and perform accumulation according to the preset rule to obtain the increasing number x; Perform phase overflow detection through the increasing number x to determine the phase accumulation value X.

[0024] The step of "determine the model output value according to the phase accumulation value X obtained by preprocessing according to the preset mathematical model" includes: According to the phase accumulation value X obtained by preprocessing, divide it into four parts: rising edge, high level, falling edge, and low level; Perform interpolation according to the edge of the waveform in different cases. When the edge time is large and not enough to generate step overshoot, use linear interpolation; when the edge time is small resulting in overshoot or jitter, use a sine 1 / 4 cycle waveform for non-linear interpolation.

[0025] As an example, such as Figure 5 and Figure 6 shown, through the above-mentioned phase accumulator, which is part of the structure of the DDS, with the known frequency control value ftw, the phase accumulator accumulates ftw once every reference clock period f c , and obtains an increasing number x. The frequency calculation formula is as follows: When the phase accumulator has a phase overflow (exceeding one waveform period), the phase accumulator is reduced to one period by subtraction, and the cumulative phase of each period is retained to achieve precise frequency adjustment.

[0026] Through the waveform real-time generator, which is used for the real-time generation of waveform data, the basic signals can be divided into two categories. One is the sine wave, and the other is the square wave, pulse and sawtooth wave. Through the waveform selector, it is selected whether to output the sine wave or the square wave, pulse or sawtooth wave. The above-mentioned sine wave can be directly generated using the CORDIC IP. Specifically, the phase comparison is performed according to the phase accumulation value X, and combined with the model output value, the waveform selection is performed to obtain the initial output waveform; and according to the phase accumulation value X, the sine wave is generated through the preset CORDIC IP, including: According to the phase accumulation value X, the sine wave is obtained through the CORDIC iteration number calculation model. Among them, the CORDIC iteration number calculation model is: In the formula, K n is the constant gain, A is the peak value of the waveform, n is the number of bits of data left shift when the CORDIC inputs fixed-point radian data; x is the phase accumulator.

[0027] In an embodiment of the present invention, the phase is judged by comparing the phase accumulation value X with parameters such as the rising edge and falling edge, and it is judged whether the current output is a rising edge, high level, falling edge or low level waveform. Interpolation is performed according to the edge of the waveform. When the edge time is large and not enough to cause a step overshoot, linear interpolation is used. When the edge time is small and causes overshoot or jitter, the sine 1 / 4 cycle waveform is used for non-linear interpolation.

[0028] As an example, in actual engineering applications, square waves, pulse waves, ramp waves, etc. can all be regarded as being composed of rising edges, high levels, falling edges, and low levels. Among them, the rising and falling edges of an ideal square wave are infinitely close to 0. However, in actual situations, due to the limitations of the sampling rate and slew rate of the DAC, all square waves will have a certain edge time. Moreover, the smaller the edge time, the more significant the overshoot phenomenon. The present invention aims to achieve a lower edge time than traditional technologies and realize the generation of low-overshoot square waves. Among them, a ramp wave can be considered a pulse wave with both high and low levels being 0, and each period only contains a rising edge and a falling edge.

[0029] Interpolate according to different situations at the edges of the waveform. When the edge time is large and not sufficient to cause a step overshoot, linear interpolation is used. When the edge time is small, resulting in overshoot or jitter, a sine 1 / 4-cycle waveform (non-linear) interpolation is used, and the phase accumulator in the DDS is used as the time index. Therefore, the cumulative phase of each period can be retained to achieve precise frequency adjustment.

[0030] Advantages of sine 1 / 4-cycle waveform non-linear interpolation: pre-distortion of the waveform digital signal. The sine 1 / 4-cycle waveform is closer to the step response curve of the DAC hardware compared to a slanted line, and can significantly reduce overshoot compared to traditional interpolation methods, and is easy to implement in hardware.

[0031] Derivation process of the mathematical models of square waves, pulse waves, and ramp waves: Rising edge time: a (s); Falling edge time: b (s); High level time: h (s); Period of the generated signal: T (s); Frequency of the generated signal: f x = 1 / T (Hz); Reference clock frequency of the FPGA system: f c (Hz); Bit width of the phase accumulator: m (typical value: 48); Phase accumulator: x; When the CORDIC inputs fixed-point radian data, the number of bits shifted left for the data: n (typical value: 15. For example, when the radian data is π / 2, it needs to be shifted left by 15 bits first to convert to the fixed-point number 51472 as the CORDIC input).

[0032] The phase data word lengths of the rising and falling edges can be obtained: Phase data word length of the rising edge: (a / T) * 2^m; Phase data word length of the falling edge: (b / T) * 2^m; Phase data word length of the high level: (h / T) * 2^m; So as Figure 7 shown, the phase accumulator is in the rising edge (interpolation data) in the interval [0, (a / T) * 2^m); in the interval [(a / T) * 2^m, ((a + h) / T) * 2^m) is in the high level state; In the interval [((a + h) / T)*2^m, ((a + h + b) / T)*2^m), it is the falling edge (interpolated data); In the interval [((a + h + b) / T)*2^m, 2^m], it is in the low - level state; As Figure 7 shown, when performing non - linear interpolation, the waveform is decomposed into four parts: rising edge, high level, falling edge, and low level. Their mathematical expressions are respectively: Since the rising edge is the image of the first 1 / 4 - period function of y = sin(x), so: Similarly, it can be obtained that: In summary, it can be obtained that: Let the threshold for switching the interpolation method be q (for the specific threshold boundary value, due to the differences in different hardware circuits and DAC performance, the actual optimal value needs to be measured through experiments). When the edge time a or b is greater than or equal to the threshold q, the output is linear interpolation, as Figure 8 shown; The mathematical model for the transformation of the interpolation method can be obtained as: This mathematical model is simply designed and only requires basic operations such as CORDIC, multiplier, and divider inside the FPGA, which is easy to implement in hardware.

[0033] Sine - wave generation: Since CORDIC can directly generate a sine - wave, the generation principle will not be elaborated here. The mathematical model is directly listed in this article: ; It should be noted that in any of the above - mentioned mathematical model formulas, A is the peak value of the waveform, a is the value at the rising edge of the waveform, b is the value at the falling edge of the waveform, h is the value at the high - level, T is the period of the generated signal, m is the bit - width of the phase accumulator; x is the phase accumulator; n is the number of bits shifted left when the CORDIC inputs fixed - point radian data; the frequency of the generated signal is: f x = 1 / T; when the CORDIC inputs fixed - point radian data: CORDIC is the calculation model for the number of iterations.

[0034] The present invention proposes a method for generating low-jitter basic digital signals based on FPGA, a waveform generation scheme that combines the high-precision characteristics of DDS and real-time interpolation methods. By conditional branch selection interpolation (linear and non-linear), the advantages of linear interpolation and non-linear interpolation are integrated to achieve the generation of low-jitter pulse waves with adjustable parameters such as edge time, pulse width, duty cycle, and symmetry. Under the same hardware performance conditions, the generated waveform has higher quality and has the following advantages: 1. High precision and low jitter, including: directly generating sine waves by the CORDIC algorithm, calculating trigonometric functions in real time through the CORDIC IP core, avoiding the errors of looking up wave tables in traditional DDS methods, and ensuring the high-precision output of sine waves. Edge time interpolation optimization, using the conditional branch selection interpolation method, and using non-linear sine interpolation for smaller edge times, effectively reducing the jitter and overshoot of pulse waves.

[0035] 2. Support for generating multiple waveforms: The system supports generating multiple waveforms such as sine waves, square waves, pulse waves, triangular waves, and sawtooth waves, with comprehensive functions. Square waves, pulse waves, and ramp waves can be decomposed into four stages: rising edge, high level, falling edge, and low level, and parameters such as pulse width, duty cycle, and symmetry can be flexibly controlled.

[0036] 3. Flexible interpolation selection and high waveform quality: For non-linear interpolation, in the case of smaller edge times, sine 1 / 4 cycle non-linear interpolation is used, significantly reducing overshoot and waveform distortion, and improving waveform quality. For linear interpolation, in the case of larger edge times, linear interpolation is used to avoid the excessive processing and computational complexity brought by non-linear interpolation. Through the dynamic switching of interpolation methods, the computational complexity and waveform accuracy are effectively balanced.

[0037] 4. Achieving precise frequency and phase control: Based on DDS (Direct Digital Synthesis) technology, high-precision control of frequency and phase is achieved through a phase accumulator. Combining the CORDIC core and interpolation technology, the generated waveform has high stability and accuracy.

[0038] 5. Low resource occupancy and easy hardware implementation: The present invention is implemented in FPGA, including basic arithmetic units such as a phase accumulator, CORDIC IP core, and interpolation module. Using addition, subtraction, and shift operations, the hardware resource consumption is low, and it is suitable for implementation on low-cost FPGA platforms.

[0039] 6. Strong practicality and suitable for a variety of application scenarios: Suitable for high-precision signal generators, communication systems, automatic control systems, motor control, digital measurement equipment and other fields. Especially suitable for pulse signal generation applications that require low jitter, low overshoot, and real-time parameter adjustment.

[0040] In a specific embodiment, the test signal frequency is set to 5Mhz, the reference clock is 200MHz, and the DAC sampling rate is 200Mhz; among them, as Figure 9 shown, when no interpolation is performed, obvious rising overshoot and falling overshoot can be seen, and a certain rising time of 8.4ns is also required; as Figure 10 shown, when the linear interpolation edge time is small (14.28ns), the slope is large, and there are still obvious waveform distortions and jitters in the linear interpolation; as Figure 11 shown, for non-linear sine interpolation, when the edge time is small (14.1ns), the distortion is not obvious, and there is no sine graph trend at the edge; as Figure 12 shown, for non-linear interpolation, when the edge time is large (40ns), the edge waveform of the non-linear interpolation is non-linear, and there is an obvious sine graph trend at the edge; as shown in 12, for non-linear interpolation, when the edge time is large (40ns), the edge waveform of the non-linear interpolation is non-linear, and there is an obvious sine graph trend at the edge; as Figure 13 shown, when the linear interpolation edge time is large (above 40ns), the overshoot phenomenon is not obvious; as Figure 14 shown, by setting the high level and low level to 0 and modulating the rising and falling edge times to obtain triangular waves, ramp waves, etc., the following experimental data are obtained: 1. In the case of traditional non-use of any interpolation algorithm, the overshoot phenomenon is serious. 2. When the edge time is below a certain threshold, non-linear sine interpolation is selected, and when it is above the threshold, linear interpolation is selected, and the overall waveform quality is higher. 3. By simply adjusting the parameters, various waveforms such as high-quality square waves, pulse waves, triangular waves, sawtooth waves, and ramp waves can be obtained.

[0041] In this application, by using the approximation method of mathematical calculation and combining the high-precision characteristics of DDS frequency control with the flexibility of edge interpolation, a low-jitter pulse wave with adjustable parameters such as edge time, pulse width, duty cycle, and symmetry is generated. This method adopts a conditional branch to select the interpolation method, integrating the advantages of linear interpolation and non-linear interpolation, and effectively reducing the edge jitter of the pulse signal.

[0042] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, refer to the partial description of the method embodiment.

[0043] This application also discloses a high-precision and low-jitter waveform generation device based on FPGA. This device is used to implement the above-mentioned high-precision and low-jitter waveform generation method based on FPGA. The device includes: A phase processing module, which is used to calculate according to the phase accumulation value obtained by preprocessing according to a preset mathematical model to determine the model output value, including: when the edge time is small, resulting in overshoot or jitter, using a sine 1 / 4 cycle waveform for non-linear interpolation; A waveform comparison module is configured to perform phase comparison based on the phase accumulation value, and in combination with the model output value, perform waveform selection to obtain an initial output waveform; and generate a sine wave according to the phase accumulation value through a preset CORDIC IP. A waveform selection module is configured to perform waveform selection based on the initial output waveform and the sine wave to determine a secondary output waveform. A waveform data conversion module is configured to perform digital-to-analog conversion based on the secondary output waveform and a preset reference clock signal, and output a final waveform.

[0044] Refer to Figure 15 , which shows a computer device of a high-precision and low-jitter waveform generation method based on FPGA according to the present invention, specifically including the following: The above computer device 12 is presented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0045] The bus 18 represents one or more of several bus 18 structures, including a memory bus 18 or a memory controller, a peripheral bus 18, a graphics acceleration port, a processor, or a local bus 18 using any bus 18 structure in a variety of bus 18 structures. For example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus 18, a Micro Channel Architecture (MAC) bus 18, an Enhanced ISA bus 18, a Video Electronics Standards Association (VESA) local bus 18, and a Peripheral Component Interconnect (PCI) bus 18.

[0046] The computer device 12 typically includes a variety of computer system readable media. These media can be any available media accessible by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0047] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be used to read and write non-removable, non-volatile magnetic media (commonly referred to as a "hard disk drive"). Although Figure 15Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical medium) can be provided. In these cases, each drive can be connected to the bus 18 through one or more data medium interfaces. The memory can include at least one program product having a set (such as at least one) of program modules 42, and these program modules 42 are configured to execute the functions of the various embodiments of the present invention.

[0048] The program / utility 40 having a set (at least one) of program modules 42 can be stored, for example, in the memory. Such program modules 42 include - but are not limited to - an operating system, one or more application programs, other program modules 42, and program data. The implementation of a network environment may be included in each or some combination of these examples. The program modules 42 generally execute the functions and / or methods in the embodiments described in the present invention.

[0049] The computer device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, a camera, etc.), and can also communicate with one or more devices that enable medical staff to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). This communication can be carried out through the input / output (I / O) interface 22. Moreover, the computer device 12 can also communicate with one or more networks (such as a local area network (LAN)), a wide area network (WAN), and / or a public network (such as the Internet) through the network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the computer device 12 through the bus 18. It should be understood that although Figure 15 not shown in the figure, other hardware and / or software modules can be used in combination with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units 16, external disk drive arrays, RAID systems, tape drives, and data backup storage systems 34, etc.

[0050] The processing unit 16 executes various functional applications and data processing by running the programs stored in the system memory 28, such as implementing a high-precision low-jitter waveform generation method based on an FPGA provided by the embodiments of the present invention.

[0051] That is, when the above processing unit 16 executes the above program, it realizes: calculating according to the phase accumulation value obtained by preprocessing according to a preset mathematical model to determine the model output value; performing phase comparison according to the phase accumulation value, and combining the model output value to perform waveform selection to obtain an initial output waveform; generating a sine wave through a preset CORDIC IP according to the phase accumulation value; performing waveform selection according to the initial output waveform and the sine wave to determine a secondary output waveform; performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal to output a final waveform.

[0052] In an embodiment of the present invention, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it realizes a high-precision and low-jitter waveform generation method based on FPGA provided by all embodiments of the present application: That is, when the program is executed by a processor, it realizes: calculating according to the phase accumulation value obtained by preprocessing according to a preset mathematical model to determine the model output value; performing phase comparison according to the phase accumulation value, and combining the model output value to perform waveform selection to obtain an initial output waveform; generating a sine wave through a preset CORDIC IP according to the phase accumulation value; performing waveform selection according to the initial output waveform and the sine wave to determine a secondary output waveform; performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal to output a final waveform.

[0053] One or more arbitrary combinations of computer-readable media can be adopted. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPOM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device.

[0054] A computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including - but not limited to - electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0055] The computer program code for performing the operations of the present invention can be written in one or more programming languages or combinations thereof. The above programming languages include object-oriented programming languages - such as Java, Smalltalk, C++, and also include conventional procedural programming languages - such as the "C" language or similar programming languages. The program code can be executed entirely on the healthcare provider's computer, partially on the healthcare provider's computer, executed as an independent software package, partially on the healthcare provider's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the healthcare provider's computer through any type of network - including a local area network (LAN) or a wide area network (WAN) - or, alternatively, can be connected to an external computer (e.g., by using an Internet service provider to connect through the Internet). Each embodiment in this specification is described in a progressive manner, with each embodiment highlighting the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0056] Although the preferred embodiments of the embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0057] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0058] The above has introduced in detail a high-precision and low-jitter waveform generation method based on FPGA provided by this application. Specific examples are used in this text to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A high-precision low-jitter waveform generation method based on FPGA, characterized in that: include: According to the phase accumulation value obtained by preprocessing, the model output value is determined by calculation according to the preset mathematical model, including: when the edge time is small and causes overexcitation or jitter, nonlinear interpolation is performed using a sine 1 / 4 cycle waveform; Performing phase comparison according to the phase accumulation value, and selecting a waveform in combination with the model output value to obtain an initial output waveform; and generating a sine wave through a preset CORDIC IP according to the phase accumulation value; According to the initial output waveform and the sine wave, waveform selection is performed to determine a secondary output waveform; According to the secondary output waveform and the preset reference clock signal, digital-to-analog conversion is performed to output the final waveform.

2. The method according to claim 1, characterized in that: The phase accumulation value obtained by preprocessing is calculated according to a preset mathematical model to determine the model output value, which also includes a preprocessing step: According to the preset reference clock signal, combined with the preset frequency control value ftw, accumulation is performed according to the preset rule to obtain an incrementing number; A phase overflow detection is performed using the incremented number to determine a phase accumulation value.

3. The method according to claim 1, characterized in that: The phase accumulation value obtained by preprocessing is calculated according to a preset mathematical model to determine the model output value, including: According to the phase accumulation value obtained by preprocessing, it is divided into four parts: rising edge, high level, falling edge, and low level; Interpolation is performed based on the edge conditions of the waveform. When the edge time is large and insufficient to produce a step overshoot, linear interpolation is used.

4. The method according to claim 3, characterized in that The interpolation is performed according to the edge conditions of the waveform. When the edge time is large and insufficient to generate a step overshoot, linear interpolation is used, including: The mathematical model transformed by interpolation is linearly interpolated, where the mathematical model is: In the formula, A is the peak value of the waveform, a is the rising edge value of the waveform, b is the falling edge value of the waveform, h is the high level value, T is the period of the generated signal, m is the bit width of the phase accumulator; x is the phase accumulator; n is the number of bits of data left shift when CORDIC inputs fixed-point radian data; the frequency of the generated signal is: fx=1 / T; when CORDIC inputs fixed-point radian data: CORDIC is the iteration number calculation model.

5. The method according to claim 1, characterized in that When the edge time is too short to cause overexcitation or jitter, a sine quarter cycle waveform is used for nonlinear interpolation, including: The mathematical model transformed by interpolation is used to perform nonlinear interpolation, where the mathematical model is: Since the rising edge is the first 1 / 4 period function image of y=sin(x), therefore: Similarly, we can get: In summary, we can get: In the formula, A is the peak value of the waveform, a is the rising edge value of the waveform, b is the falling edge value of the waveform, h is the high level value, T is the period of the generated signal, m is the bit width of the phase accumulator; x is the phase accumulator; n is the number of bits of data left shifted when the CORDIC inputs fixed-point radian data; the frequency of the generated signal is: f x =1 / T; When CORDIC inputs fixed-point radian data: CORDIC is an iteration number calculation model.

6. The method according to claim 1, characterized in that The phase comparison is performed according to the phase accumulation value, and the waveform is selected in combination with the model output value to obtain the initial output waveform; And according to the phase accumulation value, a sine wave is generated through the preset CORDIC IP, including: According to the phase accumulation value, a sine wave is obtained by using the CORDIC as the iteration number calculation model, where the CORDIC as the iteration number calculation model is: In the formula, K n is the constant gain, A is the peak value of the waveform, n is the number of bits of data left shifted when CORDIC inputs fixed-point radian data; x is the phase accumulator.

7. The method according to claim 1, characterized in that The method of accumulating according to a preset reference clock signal and a preset frequency control value ftw according to a preset rule to obtain an incremental number includes: According to the preset frequency control value ftw, ftw is accumulated every reference clock cycle to obtain an increment number, where the frequency calculation formula is: In the formula, m is the phase accumulator.

8. A high-precision low-jitter waveform generation device based on FPGA, characterized in that: include: The phase processing module is used to calculate the phase accumulation value obtained by preprocessing according to the preset mathematical model to determine the model output value, including: when the edge time is small and causes overexcitation or jitter, nonlinear interpolation is performed using a sine 1 / 4 cycle waveform; A waveform comparison module is used to perform phase comparison according to the phase accumulation value, and select a waveform in combination with the model output value to obtain an initial output waveform; and generate a sine wave through a preset CORDIC IP according to the phase accumulation value; A waveform selection module, used to select a waveform according to the initial output waveform and the sine wave, and determine a secondary output waveform; The waveform data conversion module is used to perform digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal, and output the final waveform.

9. An electronic device, characterized in that The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the FPGA-based high-precision low-jitter waveform generation method as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the FPGA-based high-precision low-jitter waveform generation method according to any one of claims 1 to 7 are implemented.

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