Address vector table fetch method and device based on finite-state machine
By introducing a combination of a finite state machine and a multiplexer into the processor, the problem that the finger fetching unit cannot directly obtain instructions is solved, and efficient finger fetching of the address vector table is realized, which improves the performance of the processor.
Patent Information
- Application Number
- CN202510286451.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-06-27
AI Technical Summary
In processor design, the finger fetching unit cannot directly obtain instructions from the instruction memory, resulting in obstacles in the finger fetching process.
The address vector table finger fetching method based on finite state machine is adopted, and the efficient finger fetching of the address vector table is achieved by setting up a finite state machine and a multiplexer. The finite state machine is used to manage the finger fetch state, while the multiplexer selects the instruction counter or address vector table based on the state of the state machine.
Through the combination of a finite state machine and multiplexer, efficient finger fetching of the address vector table is achieved, simplifying the finger fetching process and improving the performance of the processor.
Smart Images
Figure CN120216025A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technologies, and particularly to an address vector table instruction fetching method and apparatus based on a finite state machine. Background Art
[0002] RISC-V is an open-source instruction set architecture (ISA). Due to its modular, extensible, and free open-source characteristics, it has been widely used in the field of processor design. In processor design, the instruction fetch unit is a key component responsible for reading instructions from the instruction memory and sending them to subsequent processing units. Generally, the instruction fetch process of a processor is that the instruction counter accesses the instruction memory, obtains an instruction from the instruction memory, and sends the instruction counter and the instruction to subsequent functional units for further processing. However, in some specific cases, the instruction fetch unit cannot directly obtain instructions from the instruction memory.
[0003] Therefore, it is necessary to provide an address vector table instruction fetching method and apparatus based on a finite state machine to solve the above problems. Summary of the Invention
[0004] In view of the problems and deficiencies existing in the prior art, the present invention provides an address vector table instruction fetching method and apparatus based on a finite state machine, which realizes efficient instruction fetching of the address vector table by setting a finite state machine and a multiplexer.
[0005] The technical solution adopted by the present invention to solve the above technical problems is to provide an address vector table instruction fetching method based on a finite state machine, which is applied to the RISC-V instruction architecture and includes the following steps:
[0006] Set a finite state machine, where the finite state machine is used to read the address vector table;
[0007] Set a multiplexer, where the multiplexer includes a first data input port, a second data input port, a selection signal input port, and an output port; the first data input port obtains the next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains the state of the finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine and assigns it to the instruction counter through the output port;
[0008] When the finite state machine is in the first state, it indicates that the finite state machine is in the idle state, and the current instruction fetch unit is used to read an instruction from the instruction memory;
[0009] When the finite state machine is in the second state, it indicates that the finite state machine is sending a request to the instruction memory to read the address vector table.
[0010] When the finite state machine is in the third state, it indicates that the finite state machine has successfully sent a request to the instruction memory to read the address vector table and is waiting for the instruction memory to return the address vector table.
[0011] Preferably, when the finite state machine is in the first state, the following steps are further included:
[0012] When the instruction memory returns a ready signal, the finite state machine jumps from the first state to the third state;
[0013] When the instruction memory does not return a ready signal, the finite state machine jumps from the first state to the second state.
[0014] Preferably, when the finite state machine is in the second state, the following steps are further included:
[0015] When the instruction memory returns a ready signal, the finite state machine jumps from the second state to the third state;
[0016] When the instruction fetch unit is refreshed, the finite state machine jumps from the second state to the first state.
[0017] Preferably, when the finite state machine is in the third state, the following steps are further included:
[0018] When the instruction memory returns the address vector table, the finite state machine jumps from the third state to the first state.
[0019] Preferably, when the finite state machine is in the second state or the third state, the instruction fetch unit is reading the address vector table from local.
[0020] Preferably, when the finite state machine is in the first state, the multiplexer selects the next instruction counter to assign a value to the instruction counter, and the next instruction counter reads data from any one of multiple paths according to the processor implementation function and the processor state.
[0021] Preferably, when a key event is obtained, it triggers the instruction fetch unit to read the address vector table from the instruction memory.
[0022] Preferably, when the finite state machine is in the second state or the third state, it prevents the valid data returned by the instruction memory from entering the instruction queue.
[0023] Preferably, when the finite state machine is in the third state, the multiplexer selects the valid data returned from the instruction memory as the address vector table and sends it to the instruction counter for the next instruction fetch.
[0024] The present invention also provides an address vector table instruction fetching device based on a finite state machine, and the device includes:
[0025] A finite state machine for reading the address vector table;
[0026] A multiplexer for obtaining the address vector table as an input to the instruction counter. The multiplexer includes a first data input port, a second data input port, a selection signal input port, and an output port. The first data input port obtains the next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains the state of the finite state machine. The multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine and assigns it to the instruction counter through the output port;
[0027] A first state obtaining module for, when the finite state machine is in the first state, indicating that the finite state machine is in an idle state, and the current instruction fetching unit is used to read an instruction from the instruction memory;
[0028] A second state obtaining module for, when the finite state machine is in the second state, indicating that the finite state machine is sending a request to the instruction memory to read the address vector table;
[0029] A third state obtaining module for, when the finite state machine is in the third state, indicating that the finite state machine has successfully sent a request to the instruction memory to read the address vector table and is waiting for the instruction memory to return the address vector table.
[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0031] The method and device for fetching an address vector table based on a finite state machine provided by the present invention, the method includes: setting a finite state machine for reading the address vector table; setting a multiplexer, the multiplexer includes a first data input port, a second data input port, a selection signal input port and an output port; the first data input port obtains the next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains the state of the finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine, and assigns it to the instruction counter through the output port; when the finite state machine is in the first state, it indicates that the finite state machine is in the idle state, and the current instruction fetching unit is used to read an instruction from the instruction memory; when the finite state machine is in the second state, it indicates that the finite state machine is sending a request to read the address vector table to the instruction memory; when the finite state machine is in the third state, it indicates that the finite state machine has successfully sent a request to read the address vector table to the instruction memory and is waiting for the instruction memory to return the address vector table; by setting a finite state machine and a multiplexer between the instruction counter and the finite state machine, the fetching operation of the address vector table can be realized.
[0032] Further, through the jump of the finite state machine among the first state, the second state, and the third state, the reading of an address vector table is completed. The design of the finite state machine is simple and can efficiently complete the fetching operation of the address vector table. Description of the Drawings
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention, rather than all embodiments. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0034] Figure 1 It is a flowchart of the method for fetching an address vector table based on a finite state machine according to a preferred embodiment of the present invention.
[0035] Figure 2 It is a state transition diagram of the finite state machine in the method for fetching an address vector table based on a finite state machine according to a preferred embodiment of the present invention.
[0036] Figure 3 It is a schematic structural diagram of the finite state machine and the multiplexer in the method for fetching an address vector table based on a finite state machine according to a preferred embodiment of the present invention.
[0037] Figure 4Schematic diagram of the address vector table fetching device based on a finite state machine according to a preferred embodiment of the present invention. Detailed implementation manners
[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0039] The technical solutions of the present invention will be described in detail below with specific embodiments.
[0040] Based on the problems existing in the prior art, the embodiments of the present invention provide an address vector table fetching method and device based on a finite state machine, which implement an efficient fetching operation of the address vector table by setting a finite state machine and a multiplexer.
[0041] Now refer to Figures 1 - 3 , the embodiments of the present invention provide an address vector table fetching method based on a finite state machine, including the following steps:
[0042] Step S1: Set a finite state machine, which is used to read the address vector table;
[0043] Step S2: Set a multiplexer, which includes a first data input port, a second data input port, a selection signal input port, and an output port; the first data input port obtains the next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains the state of the finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine and assigns it to the instruction counter through the output port;
[0044] Step S3: When the finite state machine is in the first state, it indicates that the finite state machine is in the idle state, and the current fetching unit is used to read an instruction from the instruction memory;
[0045] Step S4: When the finite state machine is in the second state, it indicates that the finite state machine is sending a request to read the address vector table to the instruction memory;
[0046] Step S5: When the finite state machine is in the third state, it indicates that the finite state machine has successfully sent a request to read the address vector table to the instruction memory and is waiting for the instruction memory to return the address vector table.
[0047] Specifically, the first state of the finite state machine can be set to the IDLE state, the second state to the WAIT_RDY state, and the third state to the REQ_SENT state.
[0048] In a specific implementation, when the finite state machine 31 is in the first state, the following steps are further included:
[0049] When the instruction memory 33 returns a ready signal, the finite state machine 31 jumps from the first state to the third state, i.e., path ②; when the instruction memory 33 does not return a ready signal, the finite state machine 31 jumps from the first state to the second state, i.e., path ④.
[0050] In a specific implementation, when the finite state machine 31 is in the second state, the following steps are further included:
[0051] When the instruction memory 33 returns a ready signal, the finite state machine 31 jumps from the second state to the third state, i.e., path ⑤; when the fetch unit is refreshed, the finite state machine 31 jumps from the second state to the first state, i.e., path ③.
[0052] When the finite state machine 31 is in the third state, the following steps are further included:
[0053] When the instruction memory 33 returns the address vector table, the finite state machine 31 jumps from the third state to the first state.
[0054] In a specific implementation, when the finite state machine 31 is in the second state or the third state, the fetch unit reads the address vector table locally. When the finite state machine 31 is in the second state, the instruction counter 32 does not receive any assignment. When the finite state machine 31 is in the third state, the instruction counter 32 only accepts the valid instruction vector table returned by the instruction memory 33 as an assignment.
[0055] In a specific implementation, when the finite state machine 31 is in the first state, that is, when the fetch unit does not perform vector fetching, the multiplexer selects the next instruction counter to assign a value to the instruction counter, and the next instruction counter 35 reads data from any one of multiple paths according to the function implemented by the processor and the state of the processor.
[0056] Specifically, reading data from any one of multiple paths according to the processing implementation function and the processor state includes the following multiple situations: When the processor is reset, the next instruction counter 35 is the reset address. When an exception occurs, the next instruction counter 35 is the exception entry address. When the Commit instruction clears the pipeline, the next instruction counter 35 is provided by the Commit module. When the branch predictor predicts a branch instruction, the next instruction counter 35 selects the branch target address predicted by the branch predictor. When the branch execution unit corrects a branch prediction error, the next instruction counter 35 selects the branch target address calculated by the branch execution unit. When an exception program returns, the next instruction counter 35 selects the data of the Exception Program Counter (EPC). When sequentially executing 32-bit instructions, the next instruction counter 35 is the instruction counter 32 plus 4. When sequentially executing C extension instructions (compressed instructions are 16-bit instruction codes), the next instruction counter 35 is the instruction counter 32 plus 2.
[0057] In a specific implementation, when a key event is obtained, the fetch unit is triggered to read the address vector table from the instruction memory 33, and at this time, the finite state machine 31 starts to work.
[0058] Specifically, the key events include ZCMT extension instructions and fast interrupts. The ZCMT extension instructions are used to accelerate frequent events, and in order to improve the execution rate, fetching the address vector table will be triggered. When the processor receives a fast interrupt request and enters the fast interrupt entry, fetching the address vector table will be triggered.
[0059] In a specific implementation, when the finite state machine 31 is in the second state or the third state, the valid data returned by the instruction memory 33 is prevented from entering the instruction queue 34.
[0060] In a specific implementation, when the finite state machine 31 is in the third state, the multiplexer 36 selects the valid data returned from the instruction memory 33 as the address vector table and sends it to the instruction counter 32 for the next fetch. Since the data returned by the instruction memory 33 is a vector address, the instruction memory data and the instruction counter at this time are not transmitted to the instruction queue as valid instructions.
[0061] Specifically, the multiplexer 36 is a two - way selector that selects one of the next - instruction counter 35 and the address vector table entry as the assignment data for the instruction counter 32. Which path the multiplexer 36 selects as the assignment data for the instruction counter 32 is determined by the state of the finite - state machine 31. When the finite - state machine 31 is in the first state, the multiplexer 36 selects the next - instruction counter 35 as the assignment data for the instruction counter 32. When the state of the finite - state machine 31 is the third state and the instruction memory 33 returns valid data, the multiplexer 36 selects the data returned by the instruction memory 33 as the assignment data for the instruction counter 32. When the state of the finite - state machine 31 is the second state, the multiplexer 36 does not select the next - instruction counter 35 nor the data returned by the instruction memory 33, and at this time, the value of the instruction counter 32 is not updated.
[0062] An embodiment of the present invention also provides an address - vector - table instruction - fetching device based on a finite - state machine, as Figure 4 shown. The device includes:
[0063] A finite - state machine 43, which is used to read the address vector table.
[0064] A multiplexer 41, the multiplexer includes a first data input port, a second data input port, a selection - signal input port, and an output port; the first data input port obtains the next - instruction counter, the second data input port obtains the address vector table, and the selection - signal input port obtains the state of the finite - state machine; the multiplexer selects the next - instruction counter or the address vector table according to the state of the finite - state machine and assigns it to the instruction counter through the output port.
[0065] A first - state acquisition module 44, which is used to represent that the finite - state machine 43 is in an idle state when the finite - state machine 43 is in the first state, and the current instruction - fetching unit is used to read an instruction from the instruction memory;
[0066] A second - state acquisition module 45, which is used to represent that the finite - state machine 43 is sending a request to read the address vector table to the instruction memory when the finite - state machine 43 is in the second state;
[0067] A third - state acquisition module 46, which is used to represent that the finite - state machine 43 has successfully sent a request to read the address vector table to the instruction memory and is waiting for the instruction memory to return the address vector table when the finite - state machine 43 is in the third state.
[0068] In summary, the method and device for fetching an address vector table based on a finite state machine provided by the present invention include: setting a finite state machine for reading the address vector table; setting a multiplexer including a first data input port, a second data input port, a selection signal input port, and an output port; the first data input port obtains the next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains the state of the finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine and assigns it to the instruction counter through the output port; when the finite state machine is in the first state, it indicates that the finite state machine is in the idle state, and the current instruction fetching unit is used to read an instruction from the instruction memory; when the finite state machine is in the second state, it indicates that the finite state machine is sending a request to read the address vector table to the instruction memory; when the finite state machine is in the third state, it indicates that the finite state machine has successfully sent a request to read the address vector table to the instruction memory and is waiting for the instruction memory to return the address vector table; by setting a finite state machine and a multiplexer between the instruction counter and the finite state machine, the fetching operation of the address vector table can be realized.
[0069] Further, by the jump of the finite state machine among the first state, the second state, and the third state, a reading of the address vector table is completed. The design of this finite state machine is simple and can efficiently complete the fetching operation of the address vector table.
[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fetching an address vector table based on a finite state machine, applied to a RISC-V instruction architecture, characterized in that: The following steps are involved: Setting a finite state machine, wherein the finite state machine is used to read an address vector table; A multiplexer is set, the multiplexer includes a first data input port, a second data input port, a selection signal input port and an output port; the first data input port obtains a next instruction counter, the second data input port obtains an address vector table, and the selection signal input port obtains a state of a finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine, and assigns a value to the instruction counter through the output port; When the finite state machine is in the first state, it indicates that the finite state machine is in an idle state, and the current instruction fetch unit is used to read instructions from the instruction memory; When the finite state machine is in the second state, it indicates that the finite state machine is sending a request to the instruction memory to read the address vector table; When the finite state machine is in the third state, it indicates that the finite state machine has successfully sent a request to the instruction memory to read the address vector table, and is waiting for the instruction memory to return the address vector table.
2. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the first state, the following steps are also included: When the instruction memory returns a ready signal, the finite state machine jumps from the first state to the third state; When the instruction memory does not return a ready signal, the finite state machine jumps from the first state to the second state.
3. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the second state, the following steps are also included: When the instruction memory returns a ready signal, the finite state machine jumps from the second state to the third state; When the instruction fetch unit is refreshed, the finite state machine jumps from the second state to the first state.
4. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the third state, the following steps are also included: When the instruction memory returns the address vector table, the finite state machine jumps from the third state to the first state.
5. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the second state or the third state, the instruction fetch unit is reading the address vector table from a local.
6. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the first state, the multiplexer selects the next instruction counter to assign a value to the instruction counter, and the next instruction counter reads data from any one of the multiple paths according to the processor implementation function and the processor state.
7. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When a key event is obtained, the instruction fetch unit is triggered to read the address vector table from the instruction memory.
8. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the second state or the third state, valid data returned by the instruction memory is prevented from entering the instruction queue.
9. The address vector table instruction fetching method based on a finite state machine according to claim 1, characterized in that: When the finite state machine is in the third state, the multiplexer selects valid data returned from the instruction memory as an address vector table, and sends it to the instruction counter for the next instruction fetch.
10. An address vector table fetching device based on a finite state machine, applied to a RISC-V instruction architecture, characterized in that: The device comprises: A finite state machine for reading the address vector table; A multiplexer, which is used to obtain the address vector table as an input of an instruction counter, the multiplexer includes a first data input port, a second data input port, a selection signal input port and an output port; the first data input port obtains a next instruction counter, the second data input port obtains the address vector table, and the selection signal input port obtains a state of a finite state machine; the multiplexer selects the next instruction counter or the address vector table according to the state of the finite state machine, and assigns a value to the instruction counter through the output port; A first state acquisition module, which is used to indicate that when the finite state machine is in the first state, the finite state machine is in an idle state, and the current instruction fetch unit is used to read instructions from the instruction memory; A second state acquisition module, which is used to indicate that the finite state machine is sending a request to read the address vector table to the instruction memory when the finite state machine is in the second state; The third state acquisition module is used to indicate that when the finite state machine is in the third state, the finite state machine has successfully sent a request to read the address vector table to the instruction memory, and waits for the instruction memory to return the address vector table.