Groove manufacturing method, semiconductor device and manufacturing method thereof

Abstract

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for fabricating trenches, a semiconductor device, and a method for fabricating the same. Background Art

[0002] In semiconductor devices, it is often necessary to fabricate shallow trenches and deep trenches simultaneously. For example, in a backside illumination (BSI) image sensor, not only deep trenches are required to form isolation structures for isolating photodiodes, but also shallow trenches are needed to arrange metal wires to form capacitors. Currently, two photomasks are usually used to fabricate shallow trenches and deep trenches. One photomask is used to form multiple trenches with the same depth, and the other photomask is used to deepen the depth of some of the multiple trenches. However, this method uses a relatively large number of photomasks, resulting in a relatively high manufacturing cost of semiconductor devices. Summary of the Invention

[0003] The present invention discloses a method for fabricating trenches, a semiconductor device, and a method for fabricating the same, so as to solve the problem of relatively high manufacturing cost of semiconductor devices.

[0004] In a first aspect, the present invention discloses a method for fabricating trenches, including: providing a substrate, the substrate including a first trench region and a second trench region arranged at intervals; forming a first mask layer on the substrate, and using a preset photomask as a mask to etch the first mask layer so that the first mask layer only covers the substrate of the first trench region; forming a second mask layer on the substrate, and etching the second mask layer so that the second mask layer exposes the first mask layer and the substrate of the second trench region; using the first mask layer and the second mask layer as masks to etch the substrate of the second trench region to form a second trench with a first depth; etching the first mask layer so that the second mask layer exposes the substrate of the second trench region and the substrate of the first trench region; using the second mask layer as a mask to etch the substrate of the first trench region and the substrate of the second trench region to form a second trench with a second depth and a first trench with a third depth; the second depth is greater than the first depth and the third depth.

[0005] In some embodiments of the present invention, the etching of the first mask layer includes: anisotropic etching of the first mask layer; the etching of the second mask layer includes: anisotropic etching of the second mask layer.

[0006] In some embodiments of the present invention, the first mask layer includes a silicon oxide layer; the second mask layer includes a silicon nitride layer.

[0007] In some embodiments of the present invention, the width of the first trench is greater than or equal to the width of the second trench.

[0008] In some embodiments of the present invention, the substrate includes a plurality of first trenches and a plurality of second trenches; at least one of the following conditions is satisfied by the plurality of first trenches and the plurality of second trenches: the width of some of the first trenches among the plurality of first trenches is greater than or equal to the width of other first trenches; the width of some of the second trenches among the plurality of second trenches is greater than or equal to the width of other second trenches; the width of the some first trenches is greater than or equal to the width of the some second trenches; the width of the other first trenches is greater than or equal to the width of the other second trenches.

[0009] In some embodiments of the present invention, the shapes of the orthographic projections of the first trench and the second trench on the substrate are both strip-shaped, and the orthographic projections of the first trench and the second trench on the substrate are arranged in sequence along the length direction of the substrate.

[0010] In some embodiments of the present invention, the shape of the orthographic projection of the first trench on the substrate is grid-shaped, the shape of the orthographic projection of the second trench on the substrate is square, and the orthographic projection of the second trench on the substrate is located within the grid of the orthographic projection of the first trench on the substrate.

[0011] In a second aspect, the present invention discloses a method for manufacturing a semiconductor device, including: forming a first trench and a second trench by using the trench manufacturing method described in any one of the above; filling isolation media in the first trench and the second trench to form a first trench isolation structure for the first trench and a second trench isolation structure for the second trench.

[0012] In some embodiments of the present invention, the filling isolation media in the first trench and the second trench to form a first trench isolation structure for the first trench and a second trench isolation structure for the second trench includes: forming an isolation media layer on the substrate and filling the first trench and the second trench with the isolation media layer; performing surface planarization on the isolation media layer to expose the second mask layer; etching the isolation media layer between the second mask layers so that the surface of the isolation media layer is between the surface of the substrate and the surface of the second mask layer; etching the second mask layer to remove the second mask layer.

[0013] In a third aspect, the present invention discloses a semiconductor device manufactured by using the manufacturing method of the semiconductor device described above.

[0014] The present invention discloses a method for manufacturing a trench, a semiconductor device, and a method for manufacturing the same. A substrate is provided, which includes a first trench region and a second trench region arranged at intervals. A first mask layer is formed on the substrate, and using a preset photomask as a mask, the first mask layer is etched so that the first mask layer only covers the substrate of the first trench region. A second mask layer is formed on the substrate, and the second mask layer is etched so that the second mask layer exposes the first mask layer and the substrate of the second trench region. Using the first mask layer and the second mask layer as masks, the substrate of the second trench region is etched to form a second trench with a first depth. The first mask layer is etched so that the second mask layer exposes the substrate of the second trench region and the substrate of the first trench region. Using the second mask layer as a mask, the substrate of the first trench region and the substrate of the second trench region are etched to form a second trench with a second depth and a first trench with a third depth. The second depth is greater than the first depth and the third depth. Thus, a first trench, i.e., a shallow trench, and a second trench, i.e., a deep trench, can be manufactured using one photomask, and further, the manufacturing cost of the semiconductor device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the following will describe the drawings required to be used in the embodiments of the present invention or the background art.

[0016] Figures 1 to 4 It is a schematic cross-sectional structure diagram of a semiconductor device in each step of a current method for manufacturing a shallow trench and a deep trench.

[0017] Figure 5 It is a flowchart of a method for manufacturing a trench disclosed in an embodiment of the present invention.

[0018] Figures 6 to 14 It is a schematic cross-sectional structure diagram of a semiconductor device in each step of a method for manufacturing a trench disclosed in an embodiment of the present invention.

[0019] Figure 15 It is a schematic top view structure diagram of a semiconductor device including a first trench and a second trench disclosed in an embodiment of the present invention.

[0020] Figure 16 It is a schematic top view structure diagram of another semiconductor device including a first trench and a second trench disclosed in an embodiment of the present invention.

[0021] Figure 17 It is a schematic cross-sectional structure diagram of another semiconductor device including a first trench and a second trench disclosed in an embodiment of the present invention.

[0022] Figure 18 It is a flowchart of a method for manufacturing a semiconductor device disclosed in an embodiment of the present invention.

[0023] Figures 19 to 22 The present invention is a schematic diagram of the cross-sectional structure of a semiconductor device in various steps of forming a shallow trench isolation structure and a deep trench isolation structure in a method for manufacturing a semiconductor device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] As described in the background technology, in semiconductor devices, it is often necessary to simultaneously form shallow trenches and deep trenches. A current method for forming shallow trenches and deep trenches is as follows: Figure 1 As shown, a photomask is first used as a mask to form a first photoresist layer 100 of the substrate 10 exposing a plurality of trench regions on the substrate 10, and then, as shown in FIG. Figure 2 As shown, the first photoresist layer 100 is used as a mask to etch the substrate 10 in multiple groove areas to form multiple grooves 101 with the same depth. Then, as shown in FIG. Figure 3 As shown, another photomask is used as a mask to form a second photoresist layer 102 on the substrate 10 to expose a portion of the plurality of grooves 101. Then, as shown in FIG. Figure 4 As shown, using the second photoresist layer 102 as a mask, some of the grooves 101 in the plurality of grooves 101 are etched to deepen the depth of some of the grooves 101 so that these grooves 101 form deep grooves, and other grooves 101 except these grooves 101 form shallow grooves.

[0026] However, this method of making shallow grooves and deep grooves requires two photomasks, that is, the number of photomasks used is large, which leads to a high manufacturing cost of the semiconductor device. In addition, because the hollow pattern of the photomask corresponds to the groove pattern of the semiconductor device, when the groove pattern of the semiconductor device changes, two corresponding photomasks need to be remade, which also leads to a high manufacturing cost of the semiconductor device.

[0027] Based on this, the present invention discloses a groove manufacturing scheme, which uses a mask to make a mask layer to expose the second groove area, etches the substrate of the second groove area, and then etches the mask layer to expose the first groove area, and then etches the substrate of the first groove area and the substrate of the second groove area. While forming a first groove, i.e., a shallow groove, in the first groove area, a second groove, i.e., a deep groove, is formed in the second groove area, so as to reduce the manufacturing cost of the semiconductor device.

[0028] As an alternative implementation of the disclosure of the present invention, an embodiment of the present invention discloses a method for fabricating a trench, as Figure 5 shown, the method comprising: S101: Provide a substrate, the substrate including a first trench region and a second trench region disposed at intervals.

[0029] As Figure 6 shown, provide a substrate 10, the substrate 10 including a first trench region 103 and a second trench region 104 disposed at intervals. The first trench region 103 is used to form a first trench, and the second trench region 104 is used to form a second trench. The region between the first trench region 103 and the second trench region 104 is used to form an active region, and the active region is used to form semiconductor devices such as MOS transistors. Among them, the material of the substrate 10 can be any material suitable for forming semiconductor devices, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire or silicon, etc.

[0030] S102: Form a first mask layer on the substrate, and use a preset photomask as a mask to etch the first mask layer so that the first mask layer only covers the substrate in the first trench region.

[0031] As Figure 7 shown, form a first mask layer 11 on the substrate 10. Then, as Figure 8 shown, use a preset photomask as a mask to etch the first mask layer 11 so that the first mask layer 11 forms a first mask layer 11 of the substrate 10 that only covers the first trench region 103 as Figure 9 shown.

[0032] In some embodiments of the present invention, the first mask layer 11 is a hard mask, and the first mask layer 11 includes but is not limited to a silicon oxide layer. Of course, the present invention is not limited thereto. In other embodiments, the first mask layer 11 can also be a photoresist layer, etc., which will not be elaborated here. It should be noted that only positive photoresist is taken as an example in the drawings of the embodiments of the present invention, but it is not limited thereto. In other embodiments, it can also be negative photoresist.

[0033] It should be noted that when the first mask layer 11 is a hard mask, a photoresist layer can be first formed on the first mask layer 11, and then a preset photomask is used as a mask to expose and develop the photoresist layer to form a photoresist layer of the first mask layer 11 covering the first trench region 103. Then, using this photoresist layer as a mask, the first mask layer 11 is etched to form a first mask layer 11 of the substrate 10 that only covers the first trench region 103.

[0034] S103: Form a second mask layer on the substrate and etch the second mask layer to expose the first mask layer and the substrate of the second trench region.

[0035] As Figure 10 shown, form a second mask layer 12 on the substrate 10. The second mask layer 12 covers the first mask layer 11 and the substrate 10 exposed by the first mask layer 11. Then, as Figure 11 shown, etch the second mask layer 12 to expose the first mask layer 11 and the substrate 10 of the second trench region 104.

[0036] In some embodiments of the present invention, the second mask layer 12 is a hard mask, and the second mask layer 12 includes but is not limited to a silicon nitride layer. Among them, the material of the second mask layer 12 is different from that of the first mask layer 11. Of course, the present invention is not limited thereto. In other embodiments, the second mask layer 12 may also be a photoresist layer, etc., which will not be elaborated here.

[0037] In some embodiments of the present invention, the second mask layer 12 can be anisotropically etched. For example, a plasma etching process can be used to anisotropically etch the second mask layer 12, so that the etching rate of the second mask layer 12 in the longitudinal direction is greater than its etching rate in the transverse direction. While removing the second mask layer 12 on the top of the first mask layer 11 and the substrate 10 of the second trench region 104, the second mask layer 12 on the substrate 10 between the first trench region 103 and the second trench region 104 is retained.

[0038] S104: Using the first mask layer and the second mask layer as masks, etch the substrate of the second trench region to form a second trench with a first depth.

[0039] As Figure 12 shown, using the first mask layer 11 and the second mask layer 12 as masks, etch the substrate 10 of the second trench region 104 to form a second trench 105 with a first depth D1 in the second trench region 104. Among them, the substrate 10 of the second trench region 104 can be anisotropically etched to form the second trench 105 with the first depth D1.

[0040] S105: Etch the first mask layer to expose the substrate of the second trench region and the substrate of the first trench region with the second mask layer.

[0041] As Figure 13As shown in the figure, the first mask layer 11 exposed by the second mask layer 12 is etched to remove the first mask layer 11 exposed by the second mask layer 12, so that the second mask layer 12 exposes the substrate 10 of the second trench region 104 and the substrate 10 of the first trench region 103. Of course, the second mask layer 12 also covers the substrate 10 between the first trench region 103 and the second trench region 104. It should be noted that the distance between the first trench region 103 and the second trench region 104 is equal to the thickness of the second mask layer 12, and the thickness of the second mask layer 12 can be set according to actual requirements.

[0042] In some embodiments of the present invention, a wet etching process can be used to etch the first mask layer 11 exposed by the second mask layer 12. Since the material of the first mask layer 11 is different from that of the second mask layer 12, an etching solution that only etches the first mask layer 11 can be used to etch the first mask layer 11, or an etching solution with an etching rate of the first mask layer 11 much greater than that of the second mask layer 12 can be used to etch the first mask layer 11. Of course, the present invention is not limited thereto. In some other embodiments, a dry etching process can also be used to etch the first mask layer 11 exposed by the second mask layer 12.

[0043] S106: Using the second mask layer as a mask, etch the substrates of the first trench region and the second trench region to form a second trench with a second depth and a first trench with a third depth; the second depth is greater than the first depth and the third depth.

[0044] As Figure 14 shown in the figure, using the second mask layer 12 as a mask, etch the substrate 10 of the first trench region 103 and the substrate 10 of the second trench region 104 to form a second trench 105 with a second depth D2 in the second trench region 104 and a first trench 106 with a third depth D3 in the first trench region 103, where the second depth D2 is greater than the first depth D1 and the third depth D3. Among them, the second trench 105 is a deep trench, and the first trench 106 is a shallow trench.

[0045] In the trench manufacturing method disclosed in the embodiments of the present invention, only step S102 requires the use of a photomask, that is, in the embodiments of the present invention, a preset photomask can be used to form a first trench 106, that is, a shallow trench, in the first trench region 103 while forming a second trench 105, that is, a deep trench, in the second trench region 104, thereby reducing the number of photomasks used and further reducing the manufacturing cost of semiconductor devices.

[0046] In some embodiments of the present invention, the first trench 106 is used to form a shallow trench isolation structure, and the second trench 105 is used to form a deep trench isolation structure. For example, in a semiconductor device including low-voltage MOS transistors and high-voltage MOS transistors, the shallow trench isolation structure is used to isolate the low-voltage MOS transistors from each other or isolate the high-voltage MOS transistors from each other, and the deep trench isolation structure is used to isolate the low-voltage MOS transistors from the high-voltage MOS transistors to reduce the noise of the high-voltage MOS transistors on the low-voltage MOS transistors. Among them, the low-voltage MOS transistors include MOS transistors with an operating voltage of about 1V, and the high-voltage MOS transistors include MOS transistors with an operating voltage of about 32V.

[0047] On this basis, in some embodiments of the present invention, as Figure 15 shown, the shapes of the orthographic projections of the first trench 106 and the second trench 105 on the substrate 10 are both strip-shaped, and the orthographic projections of the first trench 106 and the second trench 105 on the substrate 10 are arranged in sequence along the length direction X of the substrate. Of course, the present invention is not limited to this. In other embodiments, the first trench 106 and the second trench 105 may also have other shapes and other arrangements, which will not be elaborated here.

[0048] Of course, the present invention is not limited to this. In other embodiments, the first trench 106 is also used to arrange metal wires, etc., and the second trench 105 is used to form a deep trench isolation structure. For example, in a semiconductor device including a back-illuminated image sensor, the metal wire is used to form a capacitor, and the deep trench isolation structure is used to isolate the photodiodes from each other.

[0049] On this basis, in some embodiments of the present invention, as Figure 16 shown, the shape of the orthographic projection of the first trench 106 on the substrate 10 is grid-shaped, the shape of the orthographic projection of the second trench 105 on the substrate 10 is square, and the orthographic projection of the second trench 105 on the substrate 10 is located within the grid of the orthographic projection of the first trench 106 on the substrate 10. Of course, the present invention is not limited to this. In other embodiments, the first trench 106 and the second trench 105 may also have other shapes and other arrangements, which will not be elaborated here.

[0050] In some embodiments of the present invention, as Figure 14 and Figure 15 shown, the width L1 of the first trench 106 is greater than or equal to the width L2 of the second trench 105. Of course, the present invention is not limited to this. In other embodiments, the width L1 of the first trench 106 may also be less than the width L2 of the second trench 105.

[0051] Based on this, in some embodiments of the present invention, the substrate 10 includes a plurality of first grooves 106 and a plurality of second grooves 105, and the plurality of first grooves 106 and the plurality of second grooves 105 satisfy at least one of the following conditions: the width L11 of some of the first grooves 106 in the plurality of first grooves 106 is greater than or equal to the width L12 of the other first grooves 106, the width L21 of some of the second grooves 105 in the plurality of second grooves 105 is greater than or equal to the width L22 of the other second grooves 105, the width L11 of some of the first grooves 106 is greater than or equal to the width L21 of some of the second grooves 105, and the width L12 of the other first grooves 106 is greater than or equal to the width L22 of the other second grooves 105.

[0052] As Figure 17 shown, the width L11 of some of the first grooves 106 in the plurality of first grooves 106 is greater than or equal to the width L12 of the other first grooves 106, the width L21 of some of the second grooves 105 in the plurality of second grooves 105 is greater than or equal to the width L22 of the other second grooves 105, the width L11 of some of the first grooves 106 is greater than or equal to the width L21 of some of the second grooves 105, and the width L12 of the other first grooves 106 is greater than or equal to the width L22 of the other second grooves 105.

[0053] Of course, the present invention is not limited to this. In some other embodiments, the plurality of first grooves 106 and the plurality of second grooves 105 may also satisfy at least one of the following conditions: the width L11 of some of the first grooves 106 in the plurality of first grooves 106 is less than the width L12 of the other first grooves 106, the width L21 of some of the second grooves 105 in the plurality of second grooves 105 is less than the width L22 of the other second grooves 105, the width L11 of some of the first grooves 106 is less than the width L21 of some of the second grooves 105, and the width L12 of the other first grooves 106 is less than the width L22 of the other second grooves 105.

[0054] It should be noted that under normal circumstances, the shallower the groove, the smaller its width, and the deeper the groove, the larger its width. However, the present invention is not limited to this. The width of the first groove 106 in the embodiments of the present invention is only limited by the width of the first mask layer 11 remaining after etching the first mask layer 11 with a preset photomask as a mask, and the width of the second groove 105 is only limited by the width of the substrate 10 in the second groove region 104 exposed by the second mask layer 12. That is to say, in the embodiments of the present invention, the widths of the first groove region 103 and the second groove region 104 can be set according to requirements, and then the widths of the first groove 106 and the second groove 105 can be set. Among them, the width of the first groove 106 is determined by the width of the first groove region 103, and the width of the second groove 105 is determined by the width of the second groove region 104.

[0055] As another alternative implementation of the disclosure of the present invention, embodiments of the present invention also disclose a method for manufacturing a semiconductor device. As Figure 18 shown, the manufacturing method includes: S201: Form a first trench and a second trench by using the trench manufacturing method disclosed in any of the above embodiments.

[0056] S202: Fill the first trench and the second trench with an isolation medium so that the first trench forms a first trench isolation structure and the second trench forms a second trench isolation structure.

[0057] In some embodiments of the present invention, as Figure 19 shown, an isolation medium layer 13 is formed on a substrate 10, and the isolation medium layer 13 fills the first trench 106 and the second trench 105. The isolation medium layer 13 includes but is not limited to silicon oxide or silicon nitride, etc. Then, as Figure 20 shown, surface planarization is performed on the isolation medium layer 13 to expose the second mask layer 12. Among them, chemical mechanical polishing process can be used to perform surface planarization on the isolation medium layer 13. Then, as Figure 21 shown, the isolation medium layer 13 between the second mask layers 12 is etched so that the surface of the isolation medium layer 13 is between the surface of the substrate 10 and the surface of the second mask layer 12. Among them, wet etching process or dry etching process can be used to etch the isolation medium layer 13 between the second mask layers 12. Then, as Figure 22 shown, the second mask layer 12 is etched to remove the second mask layer 12. Among them, wet etching process can be used to etch the second mask layer 12. Of course, the present invention is not limited thereto. In some other embodiments, the second mask layer 12 can also be removed during the process of performing surface planarization on the isolation medium layer 13, which will not be elaborated here.

[0058] As another alternative implementation of the disclosure of the present invention, embodiments of the present invention also disclose a semiconductor device, and the semiconductor device is manufactured by using the manufacturing method of the semiconductor device disclosed in any of the above embodiments. Among them, the semiconductor device can be a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor, or can be a semiconductor device including a back-illuminated image sensor, etc.

[0059] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should all be considered as the scope recorded in this specification.

[0060] The above embodiments merely represent several implementation manners of this specification. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all fall within the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be subject to the appended claims.

Claims

1. A method for manufacturing a groove, characterized in that, Comprising: Providing a substrate, the substrate including a first trench region and a second trench region arranged at intervals; Forming a first mask layer on the substrate, and using a preset photomask as a mask to etch the first mask layer so that the first mask layer only covers the substrate of the first trench region; Forming a second mask layer on the substrate, and etching the second mask layer so that the second mask layer exposes the substrate of the first mask layer and the second trench region; Using the first mask layer and the second mask layer as masks to etch the substrate of the second trench region to form a second trench with a first depth; Etching the first mask layer so that the second mask layer exposes the substrate of the second trench region and the substrate of the first trench region; Using the second mask layer as a mask to etch the substrate of the first trench region and the substrate of the second trench region to form a second trench with a second depth and a first trench with a third depth; The second depth is greater than the first depth and the third depth.

2. The method for manufacturing a trench according to claim 1, wherein The etching of the first mask layer includes: anisotropic etching of the first mask layer; The etching of the second mask layer includes: anisotropic etching of the second mask layer.

3. The manufacturing method of the trench according to claim 1 or 2, characterized in that The first mask layer includes a silicon oxide layer; the second mask layer includes a silicon nitride layer.

4. The method for manufacturing a trench according to claim 1, characterized in that, The width of the first trench is greater than or equal to the width of the second trench.

5. The method for manufacturing the groove according to claim 1, wherein The substrate includes a plurality of first trenches and a plurality of second trenches; at least one of the following conditions is satisfied by the plurality of first trenches and the plurality of second trenches: the width of some of the first trenches among the plurality of first trenches is greater than or equal to the width of other first trenches; The width of some of the second trenches among the plurality of second trenches is greater than or equal to the width of other second trenches; the width of the some first trenches is greater than or equal to the width of the some second trenches; The width of the other first trenches is greater than or equal to the width of the other second trenches.

6. The method for manufacturing the groove according to claim 1, characterized in that, The shapes of the positive projections of the first trench and the second trench on the substrate are both strip-shaped, and the positive projections of the first trench and the second trench on the substrate are arranged in sequence along the length direction of the substrate.

7. The manufacturing method of the groove according to claim 1, characterized in that The shape of the positive projection of the first trench on the substrate is grid-shaped, the shape of the positive projection of the second trench on the substrate is square, and the positive projection of the second trench on the substrate is located within the grid of the positive projection of the first trench on the substrate.

8. A method for manufacturing a semiconductor device, characterized in that Comprising: Forming a first trench and a second trench by using the trench manufacturing method according to any one of claims 1 to 7; Filling isolation media in the first trench and the second trench so that the first trench forms a first trench isolation structure and the second trench forms a second trench isolation structure.

9. The method for manufacturing a semiconductor device according to claim 8, wherein, The filling of isolation media in the first trench and the second trench so that the first trench forms a first trench isolation structure and the second trench forms a second trench isolation structure includes: Forming an isolation media layer on the substrate and filling the isolation media layer in the first trench and the second trench; Perform surface planarization on the isolation dielectric layer to expose the second mask layer on the isolation dielectric layer; Etch the isolation dielectric layer between the second mask layers so that the surface of the isolation dielectric layer is between the surface of the substrate and the surface of the second mask layer; Etch the second mask layer to remove the second mask layer.

10. A semiconductor device, characterized in that, It is fabricated by using the manufacturing method of the semiconductor device according to claim 8 or 9.

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