Level shift circuit and high-voltage half-bridge driving chip

Abstract

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

Description

Technical Field

[0001] This application relates to the technical field of lidar, and particularly to a level shift circuit and a high-voltage half-bridge drive chip. Background Art

[0002] Currently, lidar usually uses a high-voltage half-bridge drive chip to charge and discharge a load, thereby completing light emission and reset. The high-voltage half-bridge drive chip generally includes a logic circuit, a high-side control circuit, a low-side control circuit, a high-side switch, and a low-side switch, etc. Among them, when the high-side switch is turned on, energy is charged to the load; when the low-side switch is turned on, the load discharges.

[0003] However, during actual use, the high-voltage half-bridge drive chip will generate a large dV / dt, resulting in common-mode noise in the high-voltage level shift circuit inside the high-side control circuit. The common-mode noise will interfere with the transmission of normal signals, resulting in a duty cycle loss of the normal signals. In severe cases, signal locking may even occur, leading to abnormal charging and discharging of the load, thus affecting the normal use of the lidar.

[0004] In related technologies, a filtering module is usually added to the high-voltage level shift circuit. The filtering module is generally composed of a capacitor and a resistor. When the common-mode noise is small, it can be filtered by the filtering module. However, when the power switch device operates at a higher frequency and higher voltage, the generated common-mode noise is greater. At this time, a larger resistor or capacitor needs to be increased to filter the common-mode noise. In this way, more delays will be introduced, resulting in a reduction in the signal transmission speed. Summary of the Invention

[0005] The embodiments of this application provide a level shift circuit and a high-voltage half-bridge drive chip. The level shift circuit can filter common-mode noise to ensure the stability of the output signal, and does not require setting large resistors or capacitors, reducing delays and improving the signal transmission speed.

[0006] In a first aspect, an embodiment of the present application provides a level shift circuit, including a first high-voltage switching transistor, a second high-voltage switching transistor, a cross-coupling module, and a conversion module; the first high-voltage switching transistor, the control terminal is used to access a set signal, the first terminal is grounded, and the second terminal is used to access a power supply voltage; the second high-voltage switching transistor, the control terminal is used to access a reset signal, the first terminal is grounded, and the second terminal is used to access a power supply voltage; the cross-coupling module, the cross-coupling module includes a first current mirror and a second current mirror, the first terminal of the first current mirror is used to access a first current when the first high-voltage switching transistor is turned on, the second terminal of the first current mirror is grounded, the first terminal of the second current mirror is used to access a second current when the second high-voltage switching transistor is turned on, the second terminal of the second current mirror is grounded, wherein the first current is greater than or equal to N times the second current, and N is a positive integer; the conversion module, the first terminal is connected to the first terminal of the first current mirror through a first node, the second terminal is connected to the first terminal of the second current mirror through a second node, the third terminal is respectively connected to the third terminal of the first current mirror and the second node, the fourth terminal is respectively connected to the third terminal of the second current mirror and the first node, and the fifth terminal is used to output an output signal.

[0007] In the level shift circuit provided by the embodiment of the present application, by making the first current greater than N times the second current, that is, the first current is much greater than the second current, the potential of the first node corresponding to the first current is always higher than the potential of the second node corresponding to the second current. Even if there is common-mode noise, the common-mode noise can be filtered by the difference between the first current and the second current. In this way, without introducing a large capacitor and a large bias current, a high common-mode transient noise suppression ability is achieved. Moreover, since the cross-coupling module formed by the first current mirror and the second current mirror is a positive feedback structure, that is, the potential of the second node can be further pulled down, and then the pull-down of the first node is weakened, so the first node will quickly rise to achieve low transmission delay and accelerate the response speed.

[0008] In some possible implementation manners, the first current mirror includes a first N-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor, wherein the drain of the first N-type metal-oxide-semiconductor transistor is used to access the first current, the drain of the second N-type metal-oxide-semiconductor transistor is used to access a third current, and the width-to-length ratio of the second N-type metal-oxide-semiconductor transistor is greater than the width-to-length ratio of the first N-type metal-oxide-semiconductor transistor; the second current mirror includes a third N-type metal-oxide-semiconductor transistor and a fourth N-type metal-oxide-semiconductor transistor, the drain of the third N-type metal-oxide-semiconductor transistor is used to access the second current, the drain of the fourth N-type metal-oxide-semiconductor transistor is used to access a fourth current, and the width-to-length ratio of the fourth N-type metal-oxide-semiconductor transistor is greater than the width-to-length ratio of the third N-type metal-oxide-semiconductor transistor; wherein the first current is greater than or equal to the fourth current.

[0009] Since the first current mirror and the second current mirror form a positive feedback structure, after the condition that the first current is N times the second current is satisfied, because the aspect ratio of the second NMOS transistor is greater than that of the first NMOS transistor MN1, the third current is greater than the first current. At this time, the third current is very high, that is, the third current is much greater than the second current. At this time, the level of the second node is pulled down by the third current, making the fourth current smaller. Then, the pulling down of the first node is weakened, and the first node will quickly rise to achieve low transmission delay and accelerate the response speed.

[0010] In some possible implementation manners, the conversion module includes a fifth N-type metal-oxide-semiconductor transistor, a sixth N-type metal-oxide-semiconductor transistor, a seventh N-type metal-oxide-semiconductor transistor, and an eighth N-type metal-oxide-semiconductor transistor; for the fifth N-type metal-oxide-semiconductor transistor, the source is respectively connected to the drain of the second N-type metal-oxide-semiconductor transistor and the drain of the third N-type metal-oxide-semiconductor transistor, and the gate is shorted to the drain; for the sixth N-type metal-oxide-semiconductor transistor, the source is respectively connected to the drain of the fourth N-type metal-oxide-semiconductor transistor and the drain of the first N-type metal-oxide-semiconductor transistor, and the gate is shorted to the drain; for the seventh N-type metal-oxide-semiconductor transistor, the source is connected to the drain of the fifth N-type metal-oxide-semiconductor transistor, and the gate is connected to the first node; for the eighth N-type metal-oxide-semiconductor transistor, the source is connected to the drain of the sixth N-type metal-oxide-semiconductor transistor, and the gate is connected to the second node.

[0011] In some possible implementation manners, the level shift circuit further includes: a first resistor and a second resistor; for the first resistor, one end is used to connect to the power supply voltage, and the other end is connected to the first node and the gate of the seventh N-type metal-oxide-semiconductor transistor; for the second resistor, one end is used to connect to the power supply voltage, and the other end is connected to the second node and the gate of the eighth N-type metal-oxide-semiconductor transistor.

[0012] In some possible implementation manners, the level shift circuit further includes: a positive feedback module, the first end is connected to the drain of the seventh N-type metal-oxide-semiconductor transistor through a third node, the second end is connected to the drain of the eighth N-type metal-oxide-semiconductor through a fourth node, and the third end is used to connect to the power supply voltage.

[0013] In some possible implementations, the positive feedback module includes a first P-type metal-oxide-semiconductor (PMOS) transistor and a second N-type metal-oxide-semiconductor (NMOS) transistor; for the first PMOS transistor, the gate is connected to the fourth node, the source is used to connect to the power supply voltage, and the drain is connected to the drain of the seventh NMOS transistor; for the second PMOS transistor, the gate is connected to the third node, the source is used to connect to the power supply voltage, and the drain is connected to the drain of the eighth NMOS transistor.

[0014] In some possible implementations, the level shift circuit further includes: a shaping module, with the first end connected to the fourth node, the second end used to connect to the power supply voltage, the third end grounded, and the fourth end used to output an output signal.

[0015] In some possible implementations, the shaping module includes a first inverter and a second inverter; for the first inverter, the first end is connected to the fourth node, the second end is used to connect to the power supply voltage, and the third end is grounded; for the second inverter, the first end is connected to the fourth end of the first inverter, the second end is used to connect to the power supply voltage, the third end is grounded, and the fourth end is used to output an output signal.

[0016] In some possible implementations, the level shift circuit further includes: a third current mirror and a first voltage regulator diode; for the third current mirror, the first end is connected to the second end of the first high-voltage switch transistor through the fifth node, the second end is used to connect to the power supply voltage, and the third end is connected to the first node; for the first voltage regulator diode, one end is connected to the fifth node and the other end is used to connect to the power supply voltage.

[0017] In a second aspect, an embodiment of the present application provides a high-voltage half-bridge drive chip, including: a logic circuit, a high-side control circuit, a low-side control circuit, a high-side switch, and a low-side switch; for the logic circuit, the first input terminal is used to connect to a high-side control signal, and the second input terminal is used to connect to a low-side control signal; the high-side control circuit includes a pulse generation module and a level shift circuit according to any optional manner of the first aspect; the input terminal of the pulse generation module is connected to the first output terminal of the logic circuit and is used to generate a set signal and a reset signal; the first input terminal of the level shift circuit is used to connect to the set signal, the second input terminal of the level shift circuit is used to connect to the reset signal, and the level shift circuit is used to output an output signal according to the set signal and the reset signal; the low-side control circuit has an input terminal connected to the second output terminal of the logic circuit; for the high-side switch, the controlled terminal is connected to the output terminal of the high-side control circuit, the first end is used to connect to a DC voltage, and the second end is connected to the load; for the low-side switch, the controlled terminal is connected to the output terminal of the low-side control circuit, the first end is grounded, and the second end is connected to the load.

[0018] Based on the high-side control circuit provided by the embodiments of the present application, the common-mode noise can be filtered by making the first current greater than the second current, ensuring the reliability of the output signal. When the first current is N times the second current, since the cross-coupling module formed by the first current mirror and the second current mirror is a positive feedback structure, the potential of the second node can be further pulled down, and then the pulling down of the first node is weakened, so the first node will quickly rise to achieve low transmission delay and accelerate the response speed, that is, the signal transmission speed is improved. Since this high-side control circuit is only provided with a first resistor and a second resistor and does not have a filter capacitor, etc., the static power consumption is small. The positive feedback module can replace the latch in the related technology, simplifying the circuit structure, making the circuit structure simple and the manufacturing cost low. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 is a schematic diagram of the frame structure of a high-voltage half-bridge drive chip;

[0021] Figure 2 is a schematic diagram of the circuit structure of a high-voltage level-shifting circuit;

[0022] Figure 3 is a waveform diagram of an input signal, a set signal, and a reset signal;

[0023] Figure 4 is a schematic diagram of the circuit structure of a high-voltage level-shifting circuit;

[0024] Figure 5 is a schematic diagram of the circuit structure of another high-voltage level-shifting circuit;

[0025] Figure 6 is a schematic diagram of the circuit structure of a level-shifting circuit according to an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of the circuit structure of another level-shifting circuit according to an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of the circuit structure of another level-shifting circuit according to an embodiment of the present application;

[0028] Figure 9 is a schematic diagram of the circuit structure of yet another level-shifting circuit according to an embodiment of the present application;

[0029] Figure 10 It is a schematic circuit diagram of another level shift circuit according to an embodiment of the present application;

[0030] Figure 11 It is a schematic circuit diagram of another level shift circuit according to an embodiment of the present application;

[0031] Figure 12 It is a schematic circuit diagram of another level shift circuit according to an embodiment of the present application;

[0032] Figure 13 It is a schematic circuit diagram of another level shift circuit according to an embodiment of the present application;

[0033] Figure 14 It is a schematic framework diagram of a high - voltage half - bridge drive chip provided by an embodiment of the present application.

[0034] Reference numerals:

[0035] 1. High - voltage half - bridge drive chip; 11. Logic unit; 12. Pulse generation circuit; 13. High - voltage level shift circuit; 131. First two - stage inverter module; 132. Second two - stage inverter module; 133. First filter module; 134. Second filter module; 135. First mirror unit; 136. Second mirror unit; 137. First - stage interlock loop; 138. Second - stage interlock loop; 139. Third mirror unit; 1310. Fourth mirror unit; 14. First drive circuit; 15. Delay matching unit; 16. Second drive circuit; 2. Load; 3. Level shift circuit; 31. Cross - coupling module; 311. First current mirror; 312. Second current mirror; 32. Conversion module; 33. Third current mirror; 34. Fourth current mirror; 35. Positive feedback module; 36. Shaping module; 361. First inverter; 362. Second inverter;

[0036] Db, bootstrap diode; Cb, bootstrap capacitor; Q1, high-side switch; Q2, low-side switch; RS, latch; HO, high-side interface; LO, low-side interface; HIN, high-side control signal; LIN, low-side control signal; VDD, first power supply voltage; VSS, first ground voltage; VDDH, second power supply voltage; VSSH, second ground voltage; VDC, DC voltage; Set, set signal; Reset, reset signal; VIN, input signal; LD1, first high-voltage switch transistor; LD2, second high-voltage switch transistor; C, capacitor; CP1, first parasitic capacitor; CP2, second parasitic capacitor; R, resistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; ST1, first Schmitt trigger; ST2, second Schmitt trigger; DZ, diode; Cp1, first parasitic capacitor; Cp2, second parasitic capacitor; A, first node; B, second node; C, third node; D, fourth node; E, fifth node; F, sixth node; OUT1, first signal; OUT2, second signal; OUT, output signal; MOS1, first switching transistor; MOS2, second switching transistor; MOS3, third switching transistor; MOS4, fourth switching transistor; MOS5, fifth switching transistor; MOS6, sixth switching transistor; INV1, third inverter; INV2, fourth inverter; BiasN, first bias current; BiasP, second bias current; Dz1, first voltage regulator diode; Dz2, second voltage regulator diode; I1, first current; I2, second current; I3, third current; I4, fourth current; MN1, first NMOS transistor; MN2, second NMOS transistor; MN3, third NMOS transistor; MN4, fourth NMOS transistor; MN5, fifth NMOS transistor; MN6, sixth NMOS transistor; MN7, seventh NMOS transistor; MN8, eighth NMOS transistor; MP1, first PMOS transistor; MP2, second PMOS transistor; MP3, third PMOS transistor; MP4, fourth PMOS transistor. Detailed implementation manners

[0037] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe in detail the embodiments of the present application with reference to the accompanying drawings.

[0038] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended implementation manners.

[0039] In the description of the present application, terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. In addition, in the description of the present application, unless otherwise specified, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] Before introducing the embodiments of the present application, the following explains the professional terms that may be involved in the embodiments of the present application.

[0042] LiDAR: A radar system that detects the position, speed and other characteristic quantities of a target by emitting laser beams. Its working principle is to emit a detection signal (laser beam) to the target object, and then compare the received echo signal reflected from the target object with the detection signal (or local oscillator signal). After appropriate processing, relevant information about the target object relative to the LiDAR can be obtained, such as parameters like distance, azimuth, altitude, speed, attitude, and even shape.

[0043] Half-bridge circuit: Its working principle is based on field-effect transistors with switching control functions such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The on-time of the MOSFET is controlled by a Pulse Width Modulation (PWM) signal, so that the MOSFET works in a high-level or low-level mode within each cycle.

[0044] As a new type of wide-bandgap semiconductor material, gallium nitride (GaN) material has a higher critical breakdown voltage, a higher electron mobility, and a higher maximum operating temperature, and can replace traditional silicon (Si) materials and be widely used in the preparation of high-voltage and high-frequency power switching devices.

[0045] For example, in LiDAR, a half-bridge circuit is usually used to charge and discharge a load (i.e., a laser), thereby completing the emission and reset of the laser. As Figure 1As shown, the high-voltage half-bridge driver chip 1 (High Voltage Half-Bridge Driver) usually consists of a logic unit 11 (LogicUnits), a pulse generation circuit 12 (PulseGenerateCircuit), a high-voltage level shift circuit 13 (HighVoltageLevelShift), a latch RS, a first driver circuit 14 (Driver), a delay matching unit 15 (DelayMatchingUnit), and a second driver circuit 16. The high-voltage half-bridge driver chip 1 is also connected to a driver circuit, which is composed of a bootstrap diode Db, a bootstrap capacitor Cb, a high-side switch Q1, and a low-side switch Q2. The high-voltage half-bridge driver chip 1 usually also has a first interface, a second interface, a first voltage interface, a ground interface, a high-side interface HO, a low-side interface LO, a second voltage interface, and a third voltage interface. Among them, the first interface is used to access the high-side control signal HIN, the second interface is used to access the low-side control signal LIN, the first voltage interface is used to access the first power supply voltage VDD, the ground interface is used to access the first ground voltage VSS, the second voltage interface is used to access the second power supply voltage VDDH, and the third voltage interface is used to access the second ground voltage VSSH.

[0046] The first output terminal of the logic unit 11 is connected to the input terminal of the pulse generation circuit 12. The first output terminal and the second output terminal of the pulse generation circuit 12 are connected to the first input terminal and the second input terminal of the latch RS. The output terminal of the latch RS is connected to the input terminal of the first driver circuit 14. The output terminal of the first driver circuit 14, the high-side interface HO, is connected to the controlled terminal of the high-side switch Q1. One end of the high-side switch Q1 is connected to the DC voltage VDC, and the other end of the high-side switch Q1 is connected to the load 2. The second output terminal of the logic unit 11 is connected to the input terminal of the delay matching unit 15. The output terminal of the delay matching unit 15 is connected to the input terminal of the second driver circuit 16. The output terminal of the second driver circuit 16 is connected to the controlled terminal of the low-side switch Q2 through the low-side interface LO. One end of the low-side switch Q2 is connected to the other end of the high-side switch Q1 through a common node and is connected to the load 2. The other end of the low-side switch Q2 is connected to the first ground voltage VSS. One end of the power supply voltage interface is also connected to the positive electrode of the bootstrap diode Db. The negative electrode of the bootstrap diode Db is connected to the second voltage interface 1e and the first plate of the bootstrap capacitor Cb. The second plate of the bootstrap capacitor Cb is connected to the third voltage interface 1f and the load 2.

[0047] The first input terminal of the logic unit 11 is connected to the first interface to access the high-side control signal HIN, and the second input terminal of the logic unit 11 is connected to the second interface to access the low-side control signal LIN. After being processed by the logic unit 11, the high-side control signal HIN and the low-side control signal LIN are respectively output. The high-side signal passes through the pulse generation circuit 12 and the delay matching unit 15. After passing through the pulse generation circuit 12, the high-side control signal HIN generates two narrow pulse signals, which then undergo voltage domain conversion through the high-voltage level shift circuit 13, converting the voltage domain of the signal from the first power supply voltage VSS - the first ground voltage VDD to the second power supply voltage VSSH - the second ground voltage VDDH. Then, the two narrow pulses are restored to square wave signals by the latch RS, and after power amplification by the first drive circuit 14, they are output through the high-side interface HO to the controlled terminal of the high-side switch Q1 to control the on / off of the high-side switch Q1. The low-side control signal LIN is output to the second drive circuit 16 after passing through the delay matching unit 15. After power amplification by the second drive circuit 16, it is output through the low-side interface LO to the controlled terminal of the low-side switch Q2 to control the on / off of the low-side switch Q2. Among them, the high-side switch Q1 and the low-side switch Q2 are usually made of GaN material.

[0048] Exemplarily, when charging the load 2, the high-side control signal HIN is at a high level, the high-side switch Q1 is turned on, the low-side control signal LIN is at a low level, and the low-side switch Q2 is turned off. The DC voltage VDC charges the load 2 (charges); when the load 2 discharges, the high-side control signal HIN is at a low level, the high-side switch Q1 is turned off, the low-side control signal LIN is at a high level, and the low-side switch Q2 is turned on. The load 2 discharges through the low-side switch Q2.

[0049] When the high-voltage half-bridge drive chip 1 is working, the low-side control signal LIN controls the low-side switch Q2 to turn on first, and the high-side control signal HIN controls the high-side switch Q1 to turn off. The first power supply voltage VDD charges the bootstrap capacitor Cb through the bootstrap diode Db, and the charging current is as shown by the dotted line in Figure 1 so that the voltage across the bootstrap capacitor Cb is the first power supply voltage VDD. Then, the low-side switch Q2 is controlled to turn off, and the high-side switch Q1 is controlled to turn on. At this time, the voltage of the third power supply interface is quickly raised to the DC voltage VDC, that is, the voltage of the second ground voltage VSSH is quickly raised to the DC voltage VDC, and the current direction is as shown in Figure 1As shown by the solid line in the figure, since the voltage difference across the bootstrap capacitor Cb cannot change suddenly, the voltage of the second power supply voltage VDDH will be quickly boosted to the sum of the DC voltage VDC and the first power supply voltage VDD. When the DC voltage VDC is very high, reaching several hundred volts, and the switching speed of the GaN power switch device is very fast, the second ground voltage VSSH will rise to several hundred volts in a short time. Thus, a large dV / dt will be generated, causing the high-voltage level shift circuit 13 inside the high-voltage half-bridge drive chip 1 to generate common-mode noise, which affects the transmission of normal signals. That is, the common-mode noise will interfere with the transmission of normal signals, resulting in the loss of the duty cycle of the normal signals, and even the problem of signal locking, leading to abnormal charging and discharging of the load, thereby affecting the normal use of the lidar. Therefore, before the high-voltage half-bridge drive chip 1 works, it is usually necessary to measure the ability of the high-voltage level shift circuit 13 to withstand transient noise, that is, the common-mode transient immunity (CMTI) ability, to measure the reliability of the use of the high-voltage level shift circuit 13.

[0050] In some examples, several solutions are described.

[0051] First, resistors and capacitors are used to suppress common-mode noise. As Figure 2 shown, the high-voltage level shift circuit 13 in the related art may include a first high-voltage switch tube LD1, a second high-voltage switch tube LD2, a first parasitic capacitor CP1, a second parasitic capacitor CP2, a third resistor R3, a fourth resistor R4, a first two-stage inverter module 131, a second two-stage inverter module 132, a first filter module 133, a second filter module 134, a first Schmidt trigger ST1, and a second Schmidt trigger ST2. The controlled end of the first high-voltage switch tube LD1 is used to connect to the set signal Set, the controlled end of the second high-voltage switch tube LD2 is used to connect to the reset signal Reset, one end of the first high-voltage switch tube LD1 and one end of the second high-voltage switch tube LD2 are grounded, the other end of the first high-voltage switch tube LD1 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the second power supply voltage VDDH, the other end of the second high-voltage switch tube LD2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the second power supply voltage VDDH. The other end of the first high-voltage switch tube LD1 is connected to one end of the first two-stage inverter module 131 through the fifth node E, the other end of the second high-voltage switch tube LD2 is connected to one end of the second two-stage inverter module 132 through the sixth node F, and a diode DZ can be connected in parallel with the third resistor R3 and the fourth resistor R4 respectively.

[0052] Among them, as Figure 3As shown, the set signal Set and the reset signal Reset are obtained by the previous-stage narrow pulse generation circuit collecting the rising edge and falling edge of the input signal VIN. The set signal Set and the reset signal Reset control the alternating conduction of the first high-voltage switch LD1 and the second high-voltage switch LD2. When the set signal Set comes, the first high-voltage switch LD1 is turned on, pulling down the potential of the fifth node E. At this time, the sixth node F remains at a high level. After being shaped by the first two-stage inverter module 131, the first signal OUT1 is output through the first Schmitt trigger ST1. The working principle of the reset signal Reset is the same as that of the set signal Set, and finally the second signal OUT2 is output through the second Schmitt trigger ST2. When the second ground voltage VSSH and the second power supply voltage VDDH in the high-voltage half-bridge driving chip 1 rapidly rise to generate a large dV / dt, a common-mode noise current is generated on the first parasitic capacitor Cp1 and the second parasitic capacitor Cp2 at the fifth node E and the sixth node F. This current flows through the third resistor R3 and the fourth resistor R4 to generate a common-mode noise voltage. At this time, the fifth node E and the sixth node F are pulled down simultaneously. When the common-mode noise signal is small, it can be eliminated by the first filtering module 133 and the second filtering module 134 composed of a metal-oxide-semiconductor (MOS) transistor, a capacitor C, and a resistor R.

[0053] However, when the first high-voltage switch LD1 and the second high-voltage switch LD2 work at higher frequencies and higher voltages, the common-mode noise generated by the high-voltage half-bridge driving chip 1 is greater. At this time, it is necessary to increase the resistor R or the capacitor C in the first filtering module 133 and the second filtering module 134 to eliminate the larger common-mode noise. However, this will introduce more delays, thereby reducing the transmission speed of the normal signal. Here, it is worth noting that since the high-side switch Q1 and the low-side switch Q2 are made of GaN material, due to the special properties of the GaN material, the power switch devices made of GaN material generally need to work in scenarios with high voltage and high switching speed, resulting in the driving chip for driving this power switch device must also have the characteristics of high voltage resistance and low delay, that is, the high-voltage half-bridge driving chip 1 needs to have the characteristics of high voltage resistance and low delay. However, when filtering the larger common-mode noise through the first filtering module 133 and the second filtering module 134 composed of the capacitor C and the resistor R, more delays are introduced. In this way, if you want to have a higher CMTI ability, more delays will be introduced. If you want to have a lower transmission delay to improve the signal transmission speed, you cannot have a higher CMTI ability, and it is impossible to achieve the compatibility of a higher CMTI ability and a low transmission delay.

[0054] Second, by canceling the currents with each other to suppress the common-mode noise. Such asFigure 4 As shown, the high-voltage level-shifting circuit 13 may include a first high-voltage switching transistor LD1, a second high-voltage switching transistor LD2, a third resistor R3, a fourth resistor R4, a plurality of resistors R, a first switching transistor MOS1, a second switching transistor MOS2, a third switching transistor MOS3, a fourth switching transistor MOS4, a fifth switching transistor MOS5, a sixth switching transistor MOS6, a first mirror unit 135, and a second mirror unit 136. The other end of the first high-voltage switching transistor LD1 is connected to the first switching transistor MOS1 among the plurality of switching transistors MOS through a fifth node E, and the other end of the second high-voltage switching transistor LD2 is connected to the second switching transistor MOS2 among the plurality of switching transistors MOS through a sixth node F. The third resistor R3 and the fourth resistor R4 may be respectively connected in parallel with a diode DZ.

[0055] In this example, when common-mode noise is generated, the first switching transistor MOS1, the second switching transistor MOS2, the third switching transistor MOS3, and the fourth switching transistor MOS4 among the plurality of switching transistors MOS first convert the voltage signal into a current signal, that is, the voltage signals at the fifth node E and the sixth node F are converted into current signals at this time. After the current in the first switching transistor MOS1 is replicated by the first mirror unit 135 and compared with the current in the second switching transistor MOS2, since the currents in the first switching transistor MOS1 and the second switching transistor MOS2 are equal, the output of the high-voltage level-shifting circuit 13 remains unchanged. Similarly, the currents in the third switching transistor MOS3 and the fourth switching transistor MOS4 are also equal. Exemplarily, when a normal differential-mode signal comes, the set signal Set pulls down the fifth node E, and currents are generated in the first switching transistor MOS1 and the third switching transistor MOS3, causing the gate of the fifth switching transistor MOS5 to be pulled low, so the fifth switching transistor MOS5 remains off. At this time, the gate of the sixth switching transistor MOS6 is pulled high, the sixth switching transistor MOS6 is turned on, the first signal OUT1 changes from a high level to a low level, and the second signal OUT2 remains at a high level. At this time, the signal is transmitted normally. The working process of the reset signal Reset is the same as the working principle of the set signal Set.

[0056] In this way, the currents of the same magnitude generated by the common-mode signals cancel each other out to suppress the common-mode noise, and at this time, the CMTI ability is relatively good. However, since there may be certain deviations in each component when it leaves the factory, that is, there may also be device mismatch problems in the same component. For example, when the resistance value of the third resistor R3 is slightly smaller than that of the fourth resistor R4, it will cause a certain amount of differential-mode noise in the high-voltage level-shifting circuit 13. At this time, a filtering structure composed of a resistor R and a capacitor C is still needed to filter out the differential-mode noise. Therefore, additional delay will still be generated, resulting in that although the high-voltage level-shifting circuit 13 has relatively good CMTI ability, it is difficult to meet the requirements of high-speed applications for the high-side switch Q1 and the low-side switch Q2 prepared from GaN materials.

[0057] The third method is to suppress the common-mode noise by adopting a double-loop interlocking structure and the bias current generated in the MOS. As Figure 5 shown, the high-voltage level shift circuit 13 may include a first high-voltage switch LD1, a second high-voltage switch LD2, a first-stage interlocking loop 137, a second-stage interlocking loop 138, a third mirror unit 139, a fourth mirror unit 1310, a third inverter INV1, a fourth inverter INV2, and multiple switch transistors MOS.

[0058] In this example, when the high-voltage level shift circuit 13 operates, first, the power-on reset circuit gives the first-stage interlocking loop 137 an initial state. At this time, the second-stage interlocking loop 138 is used to strengthen this state. The initial state refers to the levels of the first signal OUT1 and the second signal OUT2. Exemplarily, when the first signal OUT is power-on reset, its initial state is low level. At this time, the first bias current BiasN of the seventh switch transistor MOS7 connected to the first signal OUT will strengthen the pull-down of the MOS in the third mirror unit. Therefore, at this time, the input signal VIN must make the current generated in the eighth switch transistor MOS8 connected to the first high-voltage switch LD1 be the sum of the current in the ninth switch transistor MOS9 connected to the second high-voltage switch LD2 and the current in the seventh switch transistor MOS7, then the output state will flip. Therefore, without introducing a filter structure composed of a resistor R and a capacitor C, it has good elimination ability for both common-mode noise and differential-mode noise.

[0059] In this way, the CMTI ability can be achieved through the double-loop interlocking structure and the seventh switch transistor MOS7, the eighth switch transistor MOS8, and the ninth switch transistor MOS9, and no additional filter structure needs to be added. However, although this solution has good elimination ability for both common-mode and differential-mode noise without introducing a filter structure, the ability of the high-voltage level shift circuit 13 to resist differential-mode noise is limited by the first bias current BiasN and the second bias current BiasNP. That is, when manufacturing the high-voltage level shift circuit 13, the first bias current BiasN and the second bias current BiasNP are preset, that is, fixed bias currents. In this way, based on the fixed bias currents, it can only act on fixed differential-mode noise. When the differential-mode noise has a certain change and is set larger, the magnitudes of the bias currents of each switch transistor MOS cannot be flexibly adjusted, resulting in low adjustment flexibility. That is, the ability of the high-voltage level shift circuit 13 to resist differential-mode noise is limited by the fixed bias currents (i.e., the first bias current BiasN and the second bias current BiasNP). And the control loop of this circuit is complex, and an additional static bias circuit needs to be set to provide the first bias current BiasN and the second bias current BiasNP for the switch transistors MOS. In this way, the manufacturing cost is high, and the power consumption is high.

[0060] To this end, the embodiments of the present application provide a level shift circuit and a high-voltage half-bridge drive chip. The level shift circuit can filter out common-mode noise to ensure the stability of the output signal, and does not require setting large resistors or capacitors, reducing delay and improving the signal transmission speed.

[0061] The following will provide an exemplary introduction to the level shift circuit and the high-voltage half-bridge drive chip provided by the present application in conjunction with the accompanying drawings.

[0062] As Figure 6 shown, the high-side control circuit 3 provided by the embodiments of the present application may include a first high-voltage switch LD1, a second high-voltage switch LD2, a cross-coupling module 31, and a conversion module 32. Among them, the controlled end of the first high-voltage switch LD1 is used to access the set signal Set, the first end of the first high-voltage switch LD1 is grounded, the second end of the first high-voltage switch LD1 is used to access the power supply voltage, the controlled end of the second high-voltage switch LD2 is used to access the reset signal Reset, the first end of the second high-voltage switch LD2 is grounded, and the second end of the second high-voltage switch LD2 is used to access the power supply voltage. At this time, the power supply voltage refers to the second power supply voltage VDDH. Since the first high-voltage switch LD1 and the second high-voltage switch LD2 are high-voltage tubes, their first ends and second ends can withstand the high voltage of the second power supply voltage VDDH, that is, the drain-source voltage of the first high-voltage switch LD1 and the second high-voltage switch LD2 can withstand the high voltage of the second power supply voltage VDDH, so as to ensure the reliability of the function of the high-side control circuit 3 by controlling the on-off of the first high-voltage switch LD1 and the second high-voltage switch LD2. At the same time, the first high-voltage switch LD1 and the second high-voltage switch LD2 can convert the narrow pulse voltage signal into a narrow pulse current signal.

[0063] As Figure 6 shown, the cross-coupling module 31 includes a first current mirror 311 and a second current mirror 312. The first end of the first current mirror 311 is used to access the first current I1 when the first high-voltage switch LD1 is turned on, the second end of the first current mirror 311 is grounded, the first end of the second current mirror 312 is used to access the second current I2 when the second high-voltage switch LD2 is turned on, and the second end of the second current mirror 312 is grounded. The first end of the conversion module 32 is connected to the first end of the first current mirror 311 through the first node A, the second end of the conversion module 32 is connected to the first end of the second current mirror 312 through the second node B, the third end of the conversion module 32 is respectively connected to the third end of the first current mirror 311 and the second node B, the fourth end of the conversion module 32 is respectively connected to the third end of the second current mirror 312 and the first node A, and the fifth end of the conversion module 32 is used to output the output signal OUT.

[0064] In this example, during operation, after power-on, a reset phase will be performed first. During the reset phase, the reset signal Reset is triggered. The reset signal Reset is at a high level, the set signal Set is at a low level, the first high-voltage switch LD1 is turned off, and the second high-voltage switch LD2 is turned on, generating a second current I2. At this time, the second node B is connected to the second current I2, and the potential of the second node B becomes higher, making the potential of the second node B higher than that of the first node A. Then, the output signal OUT output by the conversion module 32 is at a low level. When the reset phase ends, under the positive feedback of the cross-coupling module 31, the voltage of the second node B will continue to remain at a high potential. At this time, due to the pull-down of the fourth current I4, the first node A maintains a low potential close to the second ground voltage VSSH, and the output signal OUT output by the conversion module 32 still remains at a low level.

[0065] As Figure 7 shown, the first current mirror 31 in the cross-coupling module 31 may include a first N-type metal-oxide-semiconductor (NMOS) transistor MN1 and a second NMOS transistor MN2, and the second current mirror 32 may include a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The drain of the first NMOS transistor MN1 is used to connect to the first current I1, the drain of the second NMOS transistor MN2 is used to connect to the third current I3, the drain of the third NMOS transistor MN3 is used to connect to the second current I2, and the drain of the fourth NMOS transistor MN4 is used to connect to the fourth current I4. Thus, when the reset phase ends, under the positive feedback of the cross-coupling module 31, the voltage of the second node B will continue to remain at a high potential of the gate-source voltage VGS of the second NMOS transistor MN2.

[0066] In one example, as Figure 8As shown, the high-side control circuit 3 of the embodiment of the present application may include a first resistor R1 and a second resistor R2. One end of the first resistor R1 is used to connect to the second power supply voltage VDDH, and the other end of the first resistor R1 is connected to the first node A and the first end of the conversion module 32. One end of the second resistor R2 is used to connect to the second power supply voltage VDDH, and the other end of the second power supply voltage VDDH is connected to the second node B and the second end of the conversion module 32. In this example, the resistance values of the first resistor R1 and the second resistor R2 are the same. However, after the reset stage, the voltage of the second node B remains at a high potential of a gate-source voltage VGS at this time. Assuming that the voltage of the second node B is 0.7V (volt), then the current of the second node B (i.e., the second current I2) is (VDDH - 0.7) / R2, and the current of the first node A (i.e., the first current I1) is VDDH / R1 at this time. Then the current of the second node B is less than the current of the first node A, that is, the first current I1 is greater than the second current I2. Then it can be indicated that the fourth current I4 can be determined by the second power supply voltage VDDH and the first resistor R1, and the second current I2 can be determined by the resistor R2 and the gate-source voltage of the second NMOS transistor MN2. For example, by adjusting the resistance values of the first resistor R1 and the second resistor R2, the magnitudes of the fourth current I4 and the second current I2 can be correspondingly changed.

[0067] When a normal differential-mode signal comes, the set signal Set is at a high level, the reset signal Reset is at a low level, the second high-voltage switch LD2 is turned off, and the first high-voltage switch LD1 is turned on to generate a first current I1. At this time, the first current I1 is connected to the first node A, and the potential of the first node A becomes higher. And the first current I1 is greater than the second current I2, that is, the second current I2 is smaller. At this time, the potential of the second node B is pulled down by the third current I3, so that the potential of the first node A is higher than the potential of the second node B. Then the output signal OUT output by the conversion module 32 is at a high level, and the output signal OUT is normal at this time. The working process of the reset signal Reset is similar to the working process of the above set signal Set.

[0068] In summary, during the reset stage and when a normal differential-mode signal comes, the output signal OUT output by the high-side control circuit 3 is in a normal state.

[0069] In one example, as Figure 9As shown, the level shift circuit 3 further includes a third current mirror 33 and a fourth current mirror 34. The first end of the third current mirror 33 is connected to the second end of the first high-voltage switch LD1 through the fifth node E. The second end of the third current mirror 33 is used to access the second power supply voltage VDDH. The third end of the third current mirror 33 is connected to the first node A. When the first high-voltage switch LD1 is turned on, the current flowing through the third current mirror 33 is copied as the first current I1. The first end of the fourth current mirror 34 is connected to the second end of the second high-voltage switch LD2 through the sixth node F. The second end of the fourth current mirror 34 is used to access the second power supply voltage VDDH. The third end of the fourth current mirror 34 is connected to the second node B. When the second high-voltage switch LD2 is turned on, the current flowing through the fourth current mirror 34 is copied as the second current I2. By setting the mirror ratios of the third current mirror 33 and the fourth current mirror 34, the values of the first current I1 and the second current I2 can be correspondingly changed.

[0070] In one example, as Figure 9 shown, the third current mirror 33 may include a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected and are connected to the drain of the third PMOS transistor MP3. The drain of the third PMOS transistor MP3 is connected to the second end (the drain as shown in the figure) of the first high-voltage switch LD1 through the fifth node E. The drain of the fourth PMOS transistor MP4 is connected to the first node A. The sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the second power supply voltage VDDH. When the first high-voltage switch LD1 is turned on, the fourth PMOS transistor MP4 mirrors the current flowing through the third PMOS transistor MP3 to obtain the first current I1.

[0071] The fourth current mirror 34 may include a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6. The connection structure and the copying principle of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are similar to the copying principle of the above-mentioned third current mirror 33.

[0072] To avoid the problem that the voltage difference between the two points of the fifth node E and the sixth node F and the second power supply voltage VDDH is too large, causing breakdown of the subsequent circuit, as Figure 10As shown, the level shift circuit 3 may further include a first voltage stabilizing diode Dz1 and a second voltage stabilizing diode Dz2. The first voltage stabilizing diode Dz1 is connected in parallel with the third PMOS transistor MP3, and the positive electrode of the first voltage stabilizing diode Dz1 is connected to the fifth node E. The second voltage stabilizing diode Dz2 is connected in parallel with the fifth PMOS transistor MP5, and the positive electrode of the second voltage stabilizing diode Dz2 is connected to the sixth node F. Since the voltage across the first voltage stabilizing diode Dz1 and the second voltage stabilizing diode Dz2 remains at the rated value after reaching the rated value, and the voltage across them will not increase even if the current is increased. In this way, it is possible to avoid the problem that the voltage difference between the fifth node E and the sixth node F and the second power supply voltage VDDH is too large, causing breakdown of the subsequent circuit, so as to ensure the reliability of the level shift circuit 3.

[0073] When the second ground voltage VSSH and the second power supply voltage VDDH in the high-voltage half-bridge driving chip 1 rise rapidly and generate a large dV / dt, the high-side control circuit 3 will generate common-mode noise. At this time, the potentials of the fifth node E and the sixth node F are both low levels relative to the second power supply voltage VDDH, and the generated first current I1 is equal to the second current I2. In this way, the level shift circuit 3 is maintained in the power-on reset state, that is, the potential of the first node A continues to be lower than the potential of the second node B, resulting in the output signal OUT always being low level, so the output signal OUT is abnormally affected by the common-mode noise.

[0074] Therefore, in order to make the potential of the first node A still higher than the potential of the second node B after the high-side control circuit 3 generates common-mode noise, so that the output signal OUT is at a high level, the first current I1 needs to be greater than or equal to N times the second current I2, where N is a positive integer, that is Figure 10 taking as an example, the aspect ratio of the second NMOS transistor MN2 needs to be greater than the aspect ratio of the first NMOS transistor MN1. For example, the aspect ratio of the second NMOS transistor MN2 can be N times the aspect ratio of the first NMOS transistor MN1. The aspect ratio of the fourth NMOS transistor MN4 needs to be greater than the aspect ratio of the third NMOS transistor MN3. For example, the aspect ratio of the fourth NMOS transistor MN4 can be N times the aspect ratio of the third NMOS transistor MN3, so that the first current I1 needs to be greater than the fourth current I4, that is, the first current I1 needs to be greater than or equal to N times the second current I2. In this way, even if there is common-mode noise, since the first current I1 is greater than or equal to N times the second current I2, therefore, the potential of the first node A is higher than the potential of the second node B, so that the output signal OUT output by the conversion module 32 is at a high level, that is, the output signal OUT is normal at this time.

[0075] When the first current I1 is slightly greater than the second current I2 due to process mismatch, if there is a differential-mode signal, at this time, it is also necessary to make the first current I1 greater than N times the second current I2. For this, the aspect ratio of the second NMOS transistor MN2 can be set to N times the aspect ratio of the first NMOS transistor MN1, and the aspect ratio of the fourth NMOS transistor MN4 can be set to N times the aspect ratio of the third NMOS transistor MN3 as described above. In this way, when there is a differential-mode signal, the first current I1 is greater than or equal to N times the second current I2. Therefore, the differential-mode noise caused by mismatch needs to be greater than (N - 1) * the second current I2. (N - 1) * the second current I2 is the difference between the first current I1 and the second current I2. The currents corresponding to the first current I1 and the second current I2 are different. For this reason, the differential-mode noise caused by mismatch needs to be greater than (N - 1) * the minimum current Imin, where the minimum current Imin is the smaller value of the first current I1 and the second current I2.

[0076] Taking the first current I1 being greater than or equal to N times the second current I2 as an example, at this time, the potential of the first node A is higher than the potential of the second node B. The first current I1 generates a voltage across the first NMOS transistor MN1. At this time, it is necessary for the first NMOS transistor MN1 to be in the saturation region. From the saturation-region current-voltage formula (1), it can be known that:

[0077]

[0078] where, μ n is the electron mobility of the NMOS transistor, C ox is the gate oxide capacitance per unit area, W N1 and L N1 are the channel width and length of the first NMOS transistor MN1 respectively, V GSN1 is the gate-source voltage of MN1, and V THN is the threshold voltage of the first NMOS transistor MN1.

[0079] Based on the above formula (1), formula (2) can be obtained:

[0080]

[0081] where, I1 is the current value of the first current.

[0082] In one example, such as Figure 11As shown in the figure, the conversion module 32 may include a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The source of the fifth NMOS transistor MN5 is respectively connected to the drain of the second NMOS transistor MOS2 and the drain of the third NMOS transistor MOS3, and the gate of the fifth NMOS transistor MN5 is short-circuited to the drain of the fifth NMOS transistor MN5. The source of the sixth NMOS transistor MN6 is respectively connected to the drain of the fourth NMOS transistor MN4 and the drain of the first NMOS transistor MN1, and the gate of the sixth NMOS transistor MN6 is short-circuited to the drain of the sixth NMOS transistor MN6. The source of the seventh NMOS transistor MN7 is connected to the drain of the fifth NMOS transistor MN5, the gate of the seventh NMOS transistor MN7 is connected to the first node A, the source of the eighth NMOS transistor MN8 is connected to the drain of the sixth NMOS transistor MN6, the gate of the eighth NMOS transistor MN8 is connected to the second node B, the drain of the seventh NMOS transistor MN7 is connected to the second power supply voltage VDDH through a resistor R, and the drain of the eighth NMOS transistor MN8 is connected to the second power supply voltage VDDH through a resistor R.

[0083] In this example, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8 can convert the voltage signals of the first node A and the second node B into current signals.

[0084] At this time, the voltage generated by the first current I1 in the first NMOS transistor MN1 also needs to meet the turn-on condition of the seventh NMOS transistor MN7. From the above formula (2), it can be known that it is necessary to ensure that the gate-source voltage V of MN1 GSN1 is higher than the threshold voltage V of the first NMOS transistor MN1 THN and the gate-source voltage V of the fifth MN5 GSN5 to turn on the seventh NMOS transistor MN7.

[0085] In this example, the conversion module 32 outputs two voltage signals. In order to enable the conversion module 32 in the present application to directly output an output signal OUT, in one example, such as Figure 12As shown, the high-side control circuit 3 may further include a positive feedback module 35. The first end of the positive feedback module 35 is connected to the drain of the seventh NMOS transistor MN7 through the third node C. The second end of the positive feedback module 35 is connected to the drain of the eighth NMOS transistor MN8 through the fourth node D. The third end of the positive feedback module 35 is used to access the second power supply voltage VDDH. Through the positive feedback module 35, the response speed of the high-side control circuit 3 can be improved, and the narrow pulse signal can be restored to a square wave signal and output. That is, the positive feedback module 35 is the latch RS in the related art. Thus, the embodiment of the present application also integrates the function of the latch RS and can directly output an output signal OUT, and the output signal OUT is a square wave signal.

[0086] Exemplarily, as Figure 12 shown, the positive feedback module 23 may include a first PMOS transistor MP1 and a second PMOS transistor MP2. The gate of the first PMOS transistor MP1 is connected to the fourth node D. The source of the first PMOS transistor MP1 is used to access the second power supply voltage VDDH. The drain of the first PMOS transistor MP1 is connected to the drain of the seventh NMOS transistor MN7 and the third node C. The gate of the second PMOS transistor MP2 is connected to the third node C. The source of the second PMOS transistor MP2 is used to access the second power supply voltage VDDH. The drain of the second PMOS transistor MP2 is connected to the drain of the eighth NMOS transistor MN8.

[0087] When the set signal Set is at a high level, the potential of the fifth node E drops, the potential of the first node A rises and is higher than the potential of the second node B. Then the seventh NMOS transistor MN7 is turned on and the eighth NMOS transistor MN8 is turned off. The potential of the third node C becomes low and the potential of the fourth node D becomes high. At this time, the output signal OUT is at a high level.

[0088] In this example, if the seventh NMOS transistor MN7 is to be turned on, the third node C and the fourth node D are flipped and satisfy formula (3):

[0089] VDDH-VC=|V THP | (3)

[0090] where, I1 is the current value of the first current. VC is the voltage of the third node C, and V THP is the threshold voltage of the first PMOS transistor MP1.

[0091] At this time, the first PMOS transistor MP1 is in the linear region and the seventh NMOS transistor MN7 is in the saturation region. Since the currents flowing through the first PMOS transistor MP1 and the seventh NMOS transistor MN7 are equal, formula (4) can be obtained:

[0092]

[0093] Among them, V dsatP1 is the electron mobility of the first PMOS transistor MP1, and V dsatP1 = VDDH - VSSH - |V THP |, W N7 and L N7 are the channel width and length of the seventh NMOS transistor MN7 respectively, W P1 and L P1 are the channel width and length of the first PMOS transistor MP1 respectively, μ p is the electron mobility of the PMOS transistor, V GSN5 is the gate-source voltage of the fifth NMOS transistor MN5.

[0094] The formula (5) can be obtained:

[0095]

[0096] By adjusting the value of N and the dimensions (i.e., width-to-length ratios) of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, and the eighth NMOS transistor MN8, the ability of the high-side control circuit 3 to withstand dV / dt can be changed. Under the conditions of a fixed multiple relationship and device dimensions, the process adaptation is fixed. The larger dV / dt is, the larger the differential-mode noise generated in this adaptation is. At this time, the first current I1 will be much larger than the second current I2, so (N - 1)*Imin will be larger, and the filtering effect will be better, and the suppression of the differential-mode noise by the high-side control circuit 3 will be stronger. At the same time, there is no need to worry that the first current I1 will affect the normal signal transmission after being too large, because the amplitude order of the normal signal is much larger than that of the common-mode or differential-mode noise signal in this example. By making the first current I1 greater than N times the second current I2, that is, the first current I1 is greater than the second current I2, the potential of the first node A corresponding to the first current I1 is higher than the potential of the second node B corresponding to the second current I2. Even if there is common-mode noise, it can be filtered out by (N - 1)*Imin. Since the potential of the first node A is higher than the potential of the second node B, the output signal OUT always remains at a high level, that is, there is no duty cycle loss in the output signal OUT. Without introducing a large capacitor and a large bias current, the high CMTI ability is achieved.

[0097] While achieving high CMTI capabilities, low transmission delay can also be achieved to accelerate the response speed, that is, the signal transmission speed is increased. Specifically, since the conversion module 32 has a positive feedback structure, when the first current I1 is N times the second current I2, because the aspect ratio of the second NMOS transistor MN2 is N times that of the first NMOS transistor MN1, the third current I3 is equal to N times the first current I1, that is, the third current I3 is greater than the second current I2. At this time, the level of the second node B is pulled down by the third current I3, making the fourth current I4 smaller and weakening the pull-down of the first node C. The first node C will quickly rise to achieve low transmission delay and increase the signal transmission speed.

[0098] In summary, the high-side control circuit 3 provided by the embodiments of the present application can filter out common-mode noise by making the first current I1 greater than the second current I2 to generate (N - 1)*I2, ensuring the reliability of the output signal OUT. When the first current I1 is N times the second current I2, since the cross-coupling module 31 formed by the first current mirror 311 and the second current mirror 312 has a positive feedback structure, the potential of the second node B can be further pulled down, and the pull-down of the first node C is weakened, so the first node C will quickly rise to achieve low transmission delay, accelerate the response speed, and increase the signal transmission speed. At the same time, since the high-side control circuit 3 is only provided with the first resistor R1 and the second resistor R2 and does not have a filter capacitor, etc., the static power consumption is small. The positive feedback module 23 can replace the latch RS in the related art, simplifying the circuit structure, making the circuit structure simple and the manufacturing cost low.

[0099] In one example, as Figure 13 shown, the level shift circuit 3 may further include a shaping module 36. The first end of the shaping module 36 is connected to the fourth node D, the second end of the shaping module 36 is used to access the second power supply voltage VDDH, the third end of the shaping module 36 is grounded, and the fourth end of the shaping module 36 is used to output the output signal OUT.

[0100] Exemplarily, as Figure 13 shown, the shaping module 36 may include a first inverter 361 and a second inverter 362. The first end of the first inverter 361 is connected to the fourth node D, the second end of the first inverter 361 is used to access the second power supply voltage VDDH, the third end of the first inverter 361 is grounded, the first end of the second inverter 362 is connected to the fourth end of the first inverter 361, the second end of the second inverter 362 is used to access the second power supply voltage VDDH, the third end of the second inverter 362 is grounded, and the fourth end of the second inverter 362 is used to output the output signal OUT.

[0101] Optionally, the first inverter 361 and the second inverter 362 can both be composed of one PMOS and one NMOS, or can have other structures.

[0102] Based on the above level shift circuit 3, an embodiment of the present application further provides a high-voltage half-bridge driving chip, as Figure 14 shown. The high-voltage half-bridge driving chip can include a logic circuit 4, a high-side control circuit 5, a low-side control circuit 6, a high-side switch Q1, and a low-side switch Q2. Among them, the first input terminal of the logic circuit 4 is used to access a high-side control signal HIN, the second input terminal of the logic circuit 4 is used to access a low-side control signal LIN, and the high-side control circuit 5 includes a pulse generation module 51 and the level shift circuit 3 described in any of the above optional manners. The input terminal of the pulse generation module 51 is connected to the first output terminal of the logic circuit 4 and is used to generate a set signal Set and a reset signal Reset. The first input terminal of the level shift circuit 3 is used to access the set signal Set, the second input terminal of the level shift circuit 3 is used to access the reset signal Reset, and the level shift circuit 3 can output an output signal OUT according to the set signal Set and the reset signal Reset. The input terminal of the low-side control circuit 6 is connected to the second output terminal of the logic circuit 4. The controlled terminal of the high-side switch Q1 is connected to the output terminal of the high-side control circuit 5. The first terminal of the high-side switch Q1 is used to access a DC voltage VDC, the second terminal of the high-side switch Q1 is connected to the load 2, the controlled terminal of the low-side switch Q2 is connected to the output terminal of the low-side control circuit 6, the first terminal of the low-side switch Q2 is grounded, and the second terminal of the low-side switch Q2 is connected to the load 2.

[0103] Among them, the principles and different implementation functions of the logic circuit 4, the pulse generation module 51, the low-side control circuit 6, the high-side switch Q1, and the low-side switch Q2 are the same as those of the logic unit 11, the pulse generation circuit 12, the delay matching unit 15, etc. in the high-voltage half-bridge driving chip 1 in the above related technology, and can also include other structures in the above high-voltage half-bridge driving chip 1 (for example, a bootstrap diode Db, a bootstrap capacitor Cb, etc.). Specifically, reference can be made to the above high-voltage half-bridge driving chip 1.

[0104] An embodiment of the present application further provides a lidar, including the half-bridge driving circuit 3 in the above embodiment.

[0105] An embodiment of the present application further provides a movable device. The movable device includes the lidar in the above embodiment and a movable device body, and the lidar is mounted on the device body. The beneficial effects that the movable device can achieve include the beneficial effects that the above lidar can achieve, and details thereof will not be described herein again.

[0106] As can be understood by those skilled in the art from the description of the above embodiments, for the convenience and brevity of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be allocated to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0107] In the embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

Claims

1. A level shift circuit, characterized in that, The level shift circuit includes: A first high-voltage switch transistor, the control terminal of which is used to receive a set signal, the first terminal of which is grounded, and the second terminal of which is used to receive a power supply voltage; A second high-voltage switch transistor, the control terminal of which is used to receive a reset signal, the first terminal of which is grounded, and the second terminal of which is used to receive the power supply voltage; A cross-coupling module, the cross-coupling module includes a first current mirror and a second current mirror. The first terminal of the first current mirror is used to receive a first current when the first high-voltage switch transistor is turned on, the second terminal of the first current mirror is grounded, the first terminal of the second current mirror is used to receive a second current when the second high-voltage switch transistor is turned on, and the second terminal of the second current mirror is grounded. Wherein, the first current is greater than or equal to N times the second current, and N is a positive integer; and, A conversion module, the first terminal of which is connected to the first terminal of the first current mirror through a first node, the second terminal of which is connected to the first terminal of the second current mirror through a second node, the third terminal of which is respectively connected to the third terminal of the first current mirror and the second node, the fourth terminal of which is respectively connected to the third terminal of the second current mirror and the first node, and the fifth terminal of which is used to output an output signal.

2. The level shift circuit according to claim 1, characterized in that The first current mirror includes a first N-type metal-oxide-semiconductor transistor and a second N-type metal-oxide-semiconductor transistor. Wherein, the drain of the first N-type metal-oxide-semiconductor transistor is used to receive the first current, the drain of the second N-type metal-oxide-semiconductor transistor is used to receive a third current, and the width-to-length ratio of the second N-type metal-oxide-semiconductor transistor is greater than the width-to-length ratio of the first N-type metal-oxide-semiconductor transistor; The second current mirror includes a third N-type metal-oxide-semiconductor transistor and a fourth N-type metal-oxide-semiconductor transistor. The drain of the third N-type metal-oxide-semiconductor transistor is used to receive the second current, the drain of the fourth N-type metal-oxide-semiconductor transistor is used to receive a fourth current, and the width-to-length ratio of the fourth N-type metal-oxide-semiconductor transistor is greater than the width-to-length ratio of the third N-type metal-oxide-semiconductor transistor; Wherein, the first current is greater than or equal to the fourth current.

3. The level shift circuit according to claim 2, wherein The conversion module includes: A fifth N-type metal-oxide-semiconductor transistor, the source of which is respectively connected to the drain of the second N-type metal-oxide-semiconductor transistor and the drain of the third N-type metal-oxide-semiconductor transistor, and the gate of which is short-circuited to the drain; A sixth N-type metal-oxide-semiconductor transistor, the source of which is respectively connected to the drain of the fourth N-type metal-oxide-semiconductor transistor and the drain of the first N-type metal-oxide-semiconductor transistor, and the gate of which is short-circuited to the drain; A seventh N-type metal-oxide-semiconductor transistor, the source of which is connected to the drain of the fifth N-type metal-oxide-semiconductor transistor, and the gate of which is connected to the first node; and, An eighth N-type metal-oxide-semiconductor transistor, the source of which is connected to the drain of the sixth N-type metal-oxide-semiconductor transistor, and the gate of which is connected to the second node.

4. The level shift circuit according to claim 3, wherein The level shift circuit further includes: A first resistor, one end of which is used to connect to the power supply voltage, and the other end is connected to the first node and the gate of the seventh N-type metal-oxide-semiconductor transistor; and, A second resistor, one end of which is used to connect to the power supply voltage, and the other end is connected to the second node and the gate of the eighth N-type metal-oxide-semiconductor transistor.

5. The level shift circuit according to claim 3, characterized in that, The level shift circuit further includes: A positive feedback module, the first end of which is connected to the drain of the seventh N-type metal-oxide-semiconductor transistor through a third node, the second end of which is connected to the drain of the eighth N-type metal-oxide-semiconductor transistor through a fourth node, and the third end of which is used to connect to the power supply voltage.

6. The level shift circuit according to claim 5, wherein The positive feedback module includes: A first P-type metal-oxide-semiconductor transistor, the gate of which is connected to the fourth node, the source of which is used to connect to the power supply voltage, and the drain of which is connected to the drain of the seventh N-type metal-oxide-semiconductor transistor; and, A second P-type metal-oxide-semiconductor transistor, the gate of which is connected to the third node, the source of which is used to connect to the power supply voltage, and the drain of which is connected to the drain of the eighth N-type metal-oxide-semiconductor transistor.

7. The level shift circuit according to claim 5, wherein The level shift circuit further includes: A shaping module, the first end of which is connected to the fourth node, the second end of which is used to connect to the power supply voltage, the third end of which is grounded, and the fourth end of which is used to output the output signal.

8. The level shift circuit according to claim 7, wherein The shaping module includes: A first inverter, the first end of which is connected to the fourth node, the second end of which is used to connect to the power supply voltage, and the third end of which is grounded; and, A second inverter, the first end of which is connected to the fourth end of the first inverter, the second end of which is used to connect to the power supply voltage, the third end of which is grounded, and the fourth end of which is used to output the output signal.

9. The level shift circuit according to any one of claims 1-8, characterized in that The level shift circuit further includes: A third current mirror, the first end of which is connected to the second end of the first high-voltage switch transistor through a fifth node, the second end of which is used to connect to the power supply voltage, and the third end of which is connected to the first node; and, A first voltage regulator diode, one end of which is connected to the fifth node, and the other end of which is used to connect to the power supply voltage.

10. A high-voltage half-bridge drive chip, characterized in that, Comprising: A logic circuit, the first input terminal of which is used to connect to a high-side control signal, and the second input terminal of which is used to connect to a low-side control signal; A high-side control circuit, including a pulse generation module and the level shift circuit according to any one of claims 1-9; the input terminal of the pulse generation module is connected to the first output terminal of the logic circuit, and is used to generate a set signal and a reset signal; the first input terminal of the level shift circuit is used to connect to the set signal, the second input terminal of the level shift circuit is used to connect to the reset signal, and the level shift circuit is used to output the output signal according to the set signal and the reset signal; A low-side control circuit, the input terminal of which is connected to the second output terminal of the logic circuit; A high-side switch, the controlled terminal of which is connected to the output terminal of the high-side control circuit, the first end of which is used to connect to a DC voltage, and the second end of which is connected to a load; and, A low-side switch, the controlled terminal of which is connected to the output terminal of the low-side control circuit, the first end of which is grounded, and the second end of which is connected to the load.

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