Frequency control system, method and device, electronic equipment and storage medium

Abstract

The invention discloses a frequency control system, method and device, electronic equipment and a storage medium, and relates to the technical field of computers.According to the frequency control method and device, a repetition period rule is counted and analyzed based on a first system management interruption time point, and a second system management interruption triggering opportunity is set, so that unnecessary interruption is reduced, and the efficiency is improved. And the negative influence of frequent interruption on the performance of the processor is reduced. After the second system management interrupt is triggered, the number of instructions executed by the processor between two times of system management interruptions is obtained, the occupancy rate is calculated, and processor frequency adjustment is carried out in combination with frequency control schemes corresponding to different occupancy rate intervals, so that processor frequency adjustment better meets actual load requirements. The problem of performance reduction caused by frequent interruption is avoided, and the frequency is flexibly adjusted according to the actual workload, so that the technical problem of processor performance reduction caused by frequent system management interruption in the prior art can be solved, and the technical effect of system energy conservation is achieved while the processor performance is ensured.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a control system, method, device, electronic device, and storage medium for frequency. Background Art

[0002] To achieve system energy saving, the operating frequency of the central processing unit (CPU) is adjusted to reduce power consumption, so that the energy-saving effect of the computer system reaches the best.

[0003] Currently, the adjustment of the CPU operating frequency is to calculate the occupancy rate of the CPU operating frequency after a system management interrupt (SMI interrupt), and adjust the CPU operating frequency according to the occupancy rate of the CPU operating frequency. However, frequent SMI interrupts will cause a reduction in CPU performance. Summary of the Invention

[0004] This application provides a control system, method, device, electronic device, and storage medium for frequency, so as to at least solve the problem in the related art that frequent SMI interrupts will cause a reduction in CPU performance.

[0005] This application provides a control system for frequency, including a basic input / output system, a baseboard management controller, and a shared memory; the shared memory is respectively connected to the basic input / output system and the baseboard management controller; The baseboard management controller is configured to determine a first repetition period and the time points of generating system management interrupts in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each of the first system management interrupts, and send the time points of generating system management interrupts in the first repetition period to the shared memory; The shared memory is configured to, in response to a first acquisition instruction from the basic input / output system, send the time points of generating system management interrupts in the first repetition period to the basic input / output system; The basic input / output system is configured to perform frequency control on the processor according to the time points of generating system management interrupts in the first repetition period.

[0006] This application provides a frequency control method, including: Determining a first repetition period and the time points of generating system management interrupts in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each of the first system management interrupts; wherein, the time points of the first system management interrupts and the number of processor instructions between each of the first system management interrupts are obtained in the basic input / output system; Execute frequency control of the processor according to the time point when a system management interrupt occurs in the first repetition period.

[0007] This application also provides a frequency control device, including: A determination unit, configured to determine a first repetition period and the time point when a system management interrupt occurs in the first repetition period based on the time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt; Wherein, the time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt are obtained in the basic input / output system; A control unit, configured to execute frequency control of the processor according to the time point when a system management interrupt occurs in the first repetition period.

[0008] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above frequency control methods when executing the computer program.

[0009] This application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, when the computer program is executed by a processor, the steps of any of the above frequency control methods are implemented.

[0010] This application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any of the above frequency control methods are implemented.

[0011] Through this application, since the repetition period rule is statistically analyzed based on the first system management interrupt time point, and the trigger timing of the second system management interrupt is set, the number of unnecessary interrupts is reduced, and the negative impact of frequent interrupts on the processor performance is reduced. After the second system management interrupt is triggered, the number of instructions executed by the processor between the two system management interrupts is obtained, and the occupancy rate is calculated based on this. Combined with the frequency control scheme corresponding to different occupancy rate intervals, the processor frequency is adjusted, making the processor frequency adjustment more in line with the actual load requirements. This method not only avoids the problem of performance degradation caused by frequent interrupts, but also can flexibly adjust the frequency according to the actual workload. Therefore, the technical problem of frequent system management interrupts reducing the processor performance in the prior art can be solved, and the technical effect of achieving system energy saving while ensuring the processor performance can be achieved. Description of the Drawings

[0012] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 Schematic diagram of a frequency control system provided by this application; Figure 2 Schematic diagram of another frequency control system provided by this application; Figure 3 Flowchart of a frequency control method provided by an embodiment of this disclosure; Figure 4 Time series diagram of an instruction density provided by an embodiment of this application; Figure 5 Another time series diagram of an instruction density provided by an embodiment of this application; Figure 6 Schematic diagram of a repetition period provided by an embodiment of this application; Figure 7 Schematic diagram for confirming the time point of a system management interrupt provided by an embodiment of this application; Figure 8 Schematic diagram of the structure of a frequency control device provided by an embodiment of this disclosure; Figure 9 Schematic diagram of the structure of another frequency control device provided by an embodiment of this disclosure. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0015] It should be noted that in the description of this application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific implementation manners.

[0017] An embodiment of this application provides a frequency control system. Please refer to Figure 1 , Figure 1Schematic diagram of a frequency control system provided by an embodiment of the present application. The system includes a Basic Input / Output System 101, a Baseboard Management Controller 102, and a shared memory 103; The shared memory is respectively connected to the Basic Input / Output System and the Baseboard Management Controller; The Baseboard Management Controller is configured to determine a first repetition period and a time point at which a system management interrupt is generated in the first repetition period based on a time point of a first system management interrupt and the number of instructions of the processor between each first system management interrupt, and send the time point at which the system management interrupt is generated in the first repetition period to the shared memory; The shared memory, in response to a first acquisition instruction of the Basic Input / Output System, sends the time point at which the system management interrupt is generated in the first repetition period to the Basic Input / Output System; The Basic Input / Output System is configured to perform frequency control on the processor according to the time point at which the system management interrupt is generated in the first repetition period.

[0018] The frequency control system is a key component in modern computer architectures, and its design goal is to optimize energy efficiency while ensuring system performance. This frequency control system can significantly improve the energy efficiency ratio of the system by intelligently adjusting the processor frequency, and is especially suitable for power-sensitive scenarios such as high-performance computing, data centers, and embedded systems. The system adopts a dynamic frequency adjustment mechanism based on system management interrupts. In some embodiments, the Basic Input / Output System is the Basic Input / Output System (BIOS, Basic Input / Output System). Through the collaborative work of the BIOS and the Baseboard Management Controller (BMC), fine-grained control of the processor frequency is achieved.

[0019] Please refer to Figure 2 , Figure 2 Schematic diagram of another frequency control system provided by the present application; in the frequency control system, the BIOS captures the trigger time point of the System Management Interrupt (SMI) in real time through a high-precision timer, and counts the number of instructions executed by the processor between adjacent SMIs. These data are regarded as important indicators of system load changes and can reflect the working intensity of the processor in different time periods.

[0020] The BMC is a dedicated management unit independent of the main processor, usually based on the ARM or x86 architecture, with independent power supply and network connections. The main functions of the BMC are to monitor the system hardware status, manage system logs, perform remote management and other tasks. In the frequency control system, the BMC undertakes the core functions of data analysis and decision-making. It obtains the SMI time points and the number of instructions collected by the BIOS from the shared memory, applies pattern recognition algorithms to analyze the system operation rules, and identifies recurring workload patterns (i.e., repetition periods).

[0021] In some embodiments, the system further includes: The basic input / output system, after obtaining the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts, sends the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts to the shared memory; The shared memory, in response to the second acquisition instruction of the baseboard management controller, sends the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts to the baseboard management controller.

[0022] The shared memory (Shared Memory Region) is a key component for efficient data exchange between the BIOS and the BMC, usually implemented through a dedicated area in the system memory. In some embodiments, the shared memory adopts a double-buffer design, including an SMI monitoring data buffer and an optimized SMI time point buffer, which are respectively used to store the raw data collected by the BIOS and the optimized results generated by the BMC. To ensure data consistency, the shared memory implements a synchronization mechanism based on atomic operations, allowing the BIOS and the BMC to read and write data safely in different threads. This design avoids the overhead of traditional I / O communication and significantly improves the system response speed.

[0023] When the system is working, the BIOS first enters the data collection stage. Based on a high-precision timer, it records the accurate time stamps each time an SMI trigger is detected, and obtains the number of instructions executed between adjacent SMIs through the processor performance counter. These data are organized into a time series and written into the SMI monitoring data buffer of the shared memory in real time. To ensure data integrity, the BIOS adopts a circular buffer structure, and automatically overwrites the earliest data when the buffer is full.

[0024] The BMC periodically reads the SMI monitoring data from the shared memory and enters the data analysis phase. It first preprocesses the raw data, including time series alignment, outlier filtering, and data smoothing. Subsequently, the BMC applies a pattern recognition algorithm based on the Hidden Markov Model (HMM) to analyze the distribution patterns of the SMI intervals and the number of instructions, and identify the repeating cycles of the system operation. These cycles may correspond to specific application behaviors, such as database queries, video encoding, or scientific computing, etc.

[0025] After identifying the repeating cycles, the BMC enters the optimization decision phase. It dynamically adjusts the SMI trigger frequency according to the instruction execution density. For high-load regions with intensive instructions, the algorithm increases the SMI frequency to check the system status more frequently and adjust the frequency; for low-load regions with sparse instructions, it reduces the SMI frequency to reduce the interrupt overhead. This adaptive adjustment strategy can accurately match the actual load changes of the system and avoid the unnecessary overhead brought by the traditional evenly spaced SMI.

[0026] The optimized SMI time points are written into the optimized SMI time point buffer in the shared memory. After each data collection is completed, the BIOS checks whether there are new optimization results in this buffer. Once an update is found, the BIOS immediately enters the frequency control phase and adjusts the processor frequency according to the new SMI time points. This process involves modifying the clock control register of the processor and adjusting the multiplication factor or the bus frequency to achieve dynamic adjustment of the processor performance.

[0027] The core of the non-uniform system management interrupt method lies in its adaptive adjustment strategy. The algorithm first calculates the distribution of the instruction execution rate in the historical data, and then uses K-means clustering to divide the system load into different regions. For each region, the algorithm applies different SMI interval strategies respectively: This hierarchical strategy not only ensures the system's response ability to peak loads but also minimizes the interrupt overhead during low loads.

[0028] The implementation of the frequency control system involves multiple key technologies. In terms of data collection, the BIOS needs to accurately synchronize the hardware timer and the processor performance counter to ensure the accuracy of the timestamps and instruction counts. In terms of algorithm implementation, the pattern recognition and optimization algorithms running on the BMC require efficient computing resources, and usually adopt multi-thread parallel processing technology to improve the analysis speed.

[0029] In some embodiments, in order to confirm whether there is valid first repeating cycle SMI time point data in the shared memory, the BIOS continuously polls a specific status flag bit in the shared memory. This flag bit is set by the Baseboard Management Controller (BMC) after completing data calculation and writing. To ensure the accuracy and consistency of data reading, the BIOS uses atomic operations to access this flag bit to avoid competition problems in a multi-threaded environment.

[0030] After detecting that the flag bit is set, the BIOS reads the data in the shared memory. The data in the shared memory is stored in a specific structure, which contains key information such as an array of time points, a data version number, a checksum, etc.

[0031] In some embodiments, determining the first repetition period and the time points at which system management interrupts are generated in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts includes: Drawing an autocorrelation function graph of instruction density versus time based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts; In the periodic load analysis process of the BMC, quantitative analysis of the periodicity of the service load is achieved by constructing an autocorrelation function (ACF) graph of the time series. The specific implementation process is as follows: First, the BMC will obtain the time point sequence of the first system management interrupt (SMI) and the corresponding instruction number sequence are converted into an instruction density sequence , where , representing the processor load intensity per unit time. Subsequently, the system performs a normalization process on this time series, calculates its mean μ and standard deviation σ, and obtains the normalized sequence .

[0032] The drawing of the autocorrelation function graph is based on the calculation of the lag correlation of the normalized sequence: for each lag value k (k = 1, 2,..., m, where m is the maximum lag period), calculate the autocorrelation coefficient , where Z is the mean of the normalized sequence and n is the total number of samples. This coefficient reflects the degree of linear correlation of the time series at a lag of k units, and its value range is [-1, 1]. The BMC plots the corresponding to each lag value k as a two-dimensional coordinate graph, with the horizontal axis being the lag time and the vertical axis being the correlation coefficient, forming an autocorrelation function graph.

[0033] When analyzing the features in the graph, the system focuses on detecting the positions of significant positive correlation peaks: if at a lag of a time If there is a local maximum value greater than 0.7 (configurable threshold), it is determined that there is a repeating pattern with a period of a in the service load. For example, in an e-commerce promotion system, the ACF graph may have a peak at a lag of 24 hours, corresponding to the daily traffic peak cycle. To improve the detection robustness, the system uses a sliding window smoothing algorithm to denoise the ACF curve and verifies the significance of periodicity through statistical tests (such as the Ljung-Box test) to avoid misjudgment caused by random fluctuations. This mechanism converts the implicit period of the service load into a visual feature through mathematical modeling, providing a quantitative basis for dynamically adjusting the SMI interruption period.

[0034] Determine a first repeating period in the autocorrelation function graph, and determine the time point for generating a system management interruption based on the non-uniform system management interruption method within the first repeating period; wherein, the density of the system management interruption is positively correlated with the change amplitude of the instruction density.

[0035] After the BMC determines the periodic characteristics of the service load through the ACF graph (such as a significant positive correlation peak at a lag of a time), first divide the complete cycle into several sub-intervals with different instruction density change rates. In specific implementation, the system performs sliding window differential calculation on the historical instruction density curve, and defines the region where the absolute value of the curve slope exceeds the threshold as the "high density change region", and the rest as the "stable region".

[0036] In the interruption scheduling strategy, the BMC adopts an adaptive density control algorithm: for the high density change region (such as the load fluctuation exceeding the reference value by ±15%), shorten the SMI trigger interval to the minimum value of T (such as two seconds) to form a dense monitoring window; while in the stable region (fluctuation less than ±5%), extend the interval to the maximum value of T (such as 5 seconds) to reduce system overhead and ensure that the interruption density is strictly positively correlated with the severity of load change. For example, after identifying the ticket purchase peak mode, the system will automatically start dense monitoring 30 minutes before 8 am every day.

[0037] In some embodiments, the performing frequency control on the processor according to the time point for generating a system management interruption in the first repeating period includes: Set a second system management interruption based on the time point for the system management interruption in the first repeating period; The basic input / output system, after determining to trigger the second system management interruption, obtains the number of instructions executed by the processor between two second system management interruptions; The BIOS converts the time point into an actual hardware scheduling instruction, and this process involves multi-level timing control and hardware interaction.

[0038] The BIOS first converts the relative time point provided by the BMC (the offset relative to the start of the cycle) into the system absolute time, which requires an accurate calculation of the time elapsed since the system was started. Since the Time Stamp Counter (TSC) counter may pause when the system is in sleep or deep C state, the BIOS needs to maintain an accumulated sleep time correction value and subtract this correction value from the current TSC value to obtain the accurate running time. For the periodic load pattern, the BIOS constructs a circular buffer in memory and pre-computes the SMI trigger points for multiple future cycles to reduce the real-time calculation overhead.

[0039] Calculate the occupancy rate of the processor based on the number of instructions executed by the processor between the two second system management interrupts; The actual occupancy rate is obtained from the formula "occupancy rate = actual number of instructions / (theoretical throughput × time)". In some embodiments, the occupancy rate data is not only used for current decision-making, but also can be used to predict the load change trend through historical data in the future to further optimize the frequency adjustment strategy.

[0040] Determine the occupancy rate interval into which the occupancy rate falls, and different occupancy rate intervals correspond to different frequency control schemes; In some embodiments, by constructing a mapping system of a three-segment occupancy rate interval and a frequency control scheme, precise regulation of the processor performance and power consumption is achieved. The occupancy rate is divided into three intervals with clear engineering significance: occupancy rate < 90% indicates that the system resource utilization rate is not optimal, and the processor frequency level is reduced; 90% ≤ occupancy rate ≤ 95% is the optimal energy efficiency area of the system, and the current frequency level remains unchanged; occupancy rate > 95% is determined as the overload state, and the processor frequency level is increased.

[0041] Reduce unnecessary frequency adjustments through trend extrapolation in the low load area, adopt relaxation control in the stable area to reduce monitoring energy consumption, and enable an emergency response mechanism in the overload area to ensure system reliability.

[0042] Determine the frequency control scheme for frequency control of the processor according to the occupancy rate interval, and perform frequency control of the processor.

[0043] After completing the determination of the occupancy rate interval, perform frequency control of the processor according to the frequency control scheme corresponding to the corresponding occupancy rate interval.

[0044] Figure 3 It is a schematic flowchart of a frequency control method provided by an embodiment of the present disclosure.

[0045] As Figure 3 shown, it includes: Step 201: Determine the first repetition period and the time points at which system management interrupts occur in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts; Among them, the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts are obtained in the basic input / output system; In the BIOS initialization stage, configure the hardware timer to capture SMI events. In some embodiments, a timestamp counter or a high-precision event timer can be used to achieve nanosecond-level time accuracy. Specifically, the types of timers are not limited in the embodiments of the present application.

[0046] When an SMI is triggered, the interrupt handler of the BIOS will respond immediately. First, it saves the current processor context, including the states of general registers, segment registers, and flag registers. This process needs to be completed in an extremely short time to ensure the accuracy of the captured time points. Subsequently, the handler reads the value of the high-precision timer, converts it into a system timestamp, and stores it in a temporary buffer together with the SMI event type and related parameters. To ensure the accuracy of time measurement, the BIOS uses a time synchronization algorithm to regularly calibrate with the system real-time clock (RTC) to compensate for possible timer drift.

[0047] The instruction count depends on the processor's performance monitoring unit. Modern processors such as the Intel Core series and the AMD Ryzen series are equipped with performance monitoring units that can accurately count various microarchitecture events, including the number of executed instructions. The BIOS configures the performance monitoring unit by writing to specific model-specific registers, selects appropriate event counters, and enables instruction retirement event counting. During each SMI interval, the performance monitoring unit continuously accumulates the number of executed instructions. When the next SMI is triggered, the BIOS reads the counter value and resets the counter.

[0048] To handle the multi-core processor environment, the BIOS needs to traverse all logical processors in the system and configure independent performance counters for each core. In the hyper-threading technology, each physical core contains multiple logical processors, and the BIOS needs to distinguish the instruction counts of different threads. This is usually achieved by setting a thread affinity mask and combining specific MSR registers.

[0049] The BIOS organizes the processed data into a specific data structure, which includes an array of timestamps, an array of instruction count values, and metadata (such as sampling frequency, processor model, etc.). This data structure is written to a specified area of the shared memory, usually using a double-buffering technique to achieve read-write separation. To ensure data consistency, the BIOS sets an atomic flag bit to notify the BMC of the availability of new data.

[0050] Step 202, perform frequency control on the processor according to the time point when the system management interrupt is generated in the first repetition period.

[0051] For the detailed implementation process of step 102, please refer to the description in the above application embodiment, and this application embodiment will not elaborate again one by one.

[0052] In some embodiments, the determining of the first repetition period and the time point when the system management interrupt is generated in the first repetition period based on the time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt further includes: Draw an autocorrelation function graph of instruction density and time according to the time point of the first system management interrupt and the number of instructions of the processor between each first system management interrupt; Determine the first repetition period in the autocorrelation function graph, and determine the time point when the system management interrupt is generated based on the non-uniform system management interrupt method in the first repetition period; wherein, the density of the system management interrupt is positively correlated with the change range of the instruction density.

[0053] For the detailed implementation process, please refer to the description in the above application embodiment, and this application embodiment will not elaborate again one by one.

[0054] In some embodiments, the setting of the second system management interrupt based on the time point of the system management interrupt in the first repetition period and performing frequency control on the processor includes: Set the second system management interrupt based on the time point of the system management interrupt in the first repetition period; After determining that the second system management interrupt is triggered, obtain the number of instructions executed by the processor between two second system management interrupts; Calculate the occupancy rate of the processor based on the number of instructions executed by the processor; Determine the occupancy rate interval that the occupancy rate falls into, and different occupancy rate intervals correspond to different frequency control schemes; Determine the frequency control scheme for performing frequency control on the processor according to the occupancy rate interval, and perform frequency control on the processor.

[0055] For the detailed implementation process, please refer to the description in the above application embodiment, and this application embodiment will not elaborate again one by one.

[0056] In some embodiments, the determining of the frequency control scheme for performing frequency control on the processor according to the occupancy rate interval and performing frequency control on the processor includes: When the occupancy rate falls within the first occupancy rate range, determine that the frequency control scheme is to reduce the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate range; When the occupancy rate falls within the second occupancy rate range, determine that the frequency control scheme is to keep the operating frequency of the processor unchanged; When the occupancy rate falls within the third occupancy rate range, determine that the frequency control scheme is to increase the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate range.

[0057] When the real-time monitored processor occupancy rate falls into the first range lower than the target range, the system triggers a progressive frequency reduction strategy. By gradually lowering the operating frequency and continuously collecting occupancy rate data, a control loop of "adjust - feedback - readjust" is formed until the occupancy rate enters the target range; if the occupancy rate is already in the target range (the second range), then start the frequency locking mechanism to keep the current operating frequency unchanged, and at the same time use a dynamic sampling interval to optimize the monitoring efficiency and reduce the system interruption overhead while ensuring the load perception accuracy; and when the occupancy rate breaks through to the third range higher than the target range, perform a stepped frequency increase operation. By gradually increasing the frequency in stages and verifying the occupancy rate change in real time, a regulation path of "quick response - gradual convergence" is constructed until the occupancy rate returns to the target range.

[0058] This control strategy avoids frequent oscillations at the interval boundaries by introducing a hysteresis comparator mechanism, and smooths the occupancy rate data of multiple consecutive sampling periods through a sliding window to ensure the stability and accuracy of frequency adjustment. This three-stage adjustment logic forms a complete control link from load perception, policy decision-making to execution feedback through the collaborative work of the hardware performance monitoring unit and the firmware control engine. It can not only reduce power consumption by deep frequency reduction in low-load scenarios, but also quickly improve performance in high-load scenarios to cope with sudden demands, and finally achieve the efficient and stable operation of the processor within the target load range.

[0059] In some embodiments, the first repetition period includes a system management interrupt sparse area and a system management interrupt dense area; after determining the occupancy rate range in which the occupancy rate falls and different occupancy rate ranges corresponding to different frequency control schemes, the method further includes: When the number of times that the occupancy rate of the processor corresponding to the system management interrupt sparse area falls within the first occupancy rate range or the third occupancy rate range exceeds a preset threshold, obtain the second system management interrupt time point and the number of instructions of the processor between each of the second system management interrupt time points; Determine a second repetition period based on the second system management interruption time point and the number of instructions of the processor between each of the second system management interruption time points, and set a system management interruption based on the non-uniform system management interruption method within the second repetition period.

[0060] When the BMC receives a cycle calculation instruction (carrying abnormal interval statistical data) sent by the shared memory, it sets the second system management interruption to be triggered at a fixed interval through the PIT, and continuously collects instruction count and timestamp data for N complete cycles (such as set to 10 or 20). In some embodiments, to ensure data quality, the Kalman filter algorithm can be used to fuse the HPET timestamp and PMU instruction counter data to eliminate clock drift errors.

[0061] Please refer to Figure 4 , Figure 4 which is a time series diagram of instruction density provided by an embodiment of the present application. As Figure 4 shown, it can be intuitively seen that there is a repetition period of instruction density every a time period. By overlapping the two period curves, it can be found that the curve coincidence degree is very high; taking the average value of each point on the curve, as Figure 5 shown, Figure 5 which is a time series diagram of instruction density provided by an embodiment of the present application; as Figure 5 shown, at a certain time point c, curve 1 corresponds to instruction density 1, and curve 2 corresponds to instruction density 2. Then the instruction density corresponding to the merged curve at time c is (instruction density 1 + instruction density 2) ÷ 2 = instruction density 3.

[0062] Calculate the instruction density of each point and plot it into a new curve diagram, which is the repetition period curve diagram, as Figure 6 shown, Figure 6 which is a repetition period schematic diagram provided by an embodiment of the present application.

[0063] Please refer to Figure 7 , Figure 7 which is a schematic diagram for confirming the time point of system management interruption provided by an embodiment of the present application. As Figure 7 shown, when the BMC predicts that the instruction density is in a stable period, a sparse SMI setting is adopted. At this time, since there is no need to widely adjust the processor frequency, when it is predicted that the instruction density needs to change, it enters the SMI intensive area, and SMI is densely generated to calculate the processor occupancy rate and accurately adjust the frequency.

[0064] In the cycle analysis stage, the BMC uses multi-resolution wavelet transform to decompose the time series into different frequency components, and identifies the dominant cycle component through spectral analysis.

[0065] Based on the newly determined second repetition period, the BMC implements a non-uniform SMI scheduling strategy: by performing a sliding window regression analysis on the historical instruction density curve, predicting the extreme points of the load change rate, setting a dense SMI monitoring window before and after the extreme points, and using sparse monitoring in other regions. This dynamic adjustment reduces the number of SMI triggers while maintaining the same monitoring accuracy of the system.

[0066] The BMC sends the optimized second repetition period parameters (including the period length, the SMI time point array, and the confidence score) to the BIOS through shared memory.

[0067] In some embodiments, before determining the first repetition period and the time points at which system management interrupts are generated in the first repetition period based on the time points of the first system management interrupts and the number of instructions executed by the processor between each pair of the first system management interrupts, the method further includes: Setting the first system management interrupt based on a fixed time interval; After determining that the first system management interrupt is triggered, obtaining the time point of the first system management interrupt and the number of instructions executed by the processor between the two first system management interrupts.

[0068] Set a reference interrupt period, such as 2 seconds or 3 seconds, and generate an SMI signal at each time boundary. When the BIOS captures an SMI trigger, read the interrupt trigger moment of the timestamp counter, and this timestamp will be used as the reference point for subsequent cycle calculations; at the same time, read the current value of the instruction counter, and the difference in the count values between two SMI interrupts is the total number of instructions executed by the processor within this cycle.

[0069] In some embodiments, the determining the first repetition period in the autocorrelation function graph further includes: When it is determined that there is no repetition period in the autocorrelation function graph, determining the time points at which system management interrupts are generated at a fixed time interval.

[0070] In the fixed interval mode, the BMC implements a dual redundant guarantee mechanism: on the one hand, the deviation between the actual SMI trigger time and the theoretical time is monitored in real time through a timestamp comparator. If the deviation exceeds ±5 μs continuously for 3 times, the hardware clock calibration process is triggered; on the other hand, a sliding window counter is maintained to count the total number of instructions executed within every 100 intervals. If the fluctuation coefficient exceeds 15%, the cycle re-detection algorithm is automatically triggered. This design enables the system to maintain a stable monitoring efficiency in the absence of an obvious periodic load scenario and also has self-adaptability to potential periodic characteristics. It should be noted that this description method is only an exemplary illustration and not a specific limitation on specific values, and the embodiments of the present application do not limit this.

[0071] In some embodiments, the density of generating a system management interrupt determined based on the non-uniform system management interrupt method is less than the density of generating a system management interrupt determined at fixed time intervals.

[0072] Embodiments of the present application also provide a frequency control device. Figure 8 As shown in the structural schematic diagram of a frequency control device provided by an embodiment of the present disclosure, Figure 8 the device is applied to the basic input / output system and includes: A first determination unit 31, configured to determine a first repetition period and the time points of generating system management interrupts in the first repetition period based on the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts; wherein, the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts are obtained in the basic input / output system; A control unit 32, configured to perform frequency control on the processor according to the time points of generating system management interrupts in the first repetition period.

[0073] Further, in a possible implementation manner of an embodiment of the present disclosure, the first determination unit 31 is further configured to: Draw an autocorrelation function graph of instruction density and time according to the time points of the first system management interrupts and the number of instructions of the processor between each of the first system management interrupts; Determine the first repetition period in the autocorrelation function graph, and determine the time points of generating system management interrupts in the first repetition period based on the non-uniform system management interrupt method; wherein, the density of the system management interrupt is positively correlated with the change amplitude of the instruction density.

[0074] Further, in a possible implementation manner of an embodiment of the present disclosure, the control unit 32 is further configured to: Set a second system management interrupt based on the time points of the system management interrupts in the first repetition period; After determining that the second system management interrupt is triggered, obtain the number of instructions executed by the processor between two second system management interrupts; Calculate the occupancy rate of the processor based on the number of instructions executed by the processor; Determine the occupancy rate interval that the occupancy rate falls into, and different occupancy rate intervals correspond to different frequency control schemes; Determine the frequency control scheme for performing frequency control on the processor according to the occupancy rate interval, and perform frequency control on the processor.

[0075] Further, in a possible implementation manner of an embodiment of the present disclosure, the control unit 32 is further configured to: When the occupancy rate falls within the first occupancy rate range, determine the frequency control scheme to reduce the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate range; When the occupancy rate falls within the second occupancy rate range, determine the frequency control scheme to keep the operating frequency of the processor unchanged; When the occupancy rate falls within the third occupancy rate range, determine the frequency control scheme to increase the operating frequency of the processor until the occupancy rate of the processor after adjusting the operating frequency falls within the second occupancy rate range.

[0076] Further, in a possible implementation manner of the embodiment of the present disclosure, the first repetition period includes a system management interrupt sparse area and a system management interrupt dense area. As Figure 9 shown, the apparatus further includes: A generating unit 33, configured to, after the control unit 32 determines the occupancy rate range where the occupancy rate falls, and different occupancy rate ranges correspond to different frequency control schemes, when the number of times that the occupancy rate of the processor corresponding to the system management interrupt sparse area falls within the first occupancy rate range or the third occupancy rate range exceeds a preset threshold, obtain the second system management interrupt time point and the number of instructions of the processor between each second system management interrupt time point; A second determining unit 34, configured to determine the second repetition period according to the second system management interrupt time point and the number of instructions of the processor between each second system management interrupt time point, and set the system management interrupt in the second repetition period based on the non-uniform system management interrupt method.

[0077] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 9 shown, the apparatus further includes: A setting unit 35, configured to set the first system management interrupt based on a fixed time interval before the first determining unit 31 determines the first repetition period and the time points for generating the system management interrupt in the first repetition period based on the time points of the first system management interrupt and the number of instructions of the processor between each first system management interrupt; An obtaining unit 36, configured to obtain the time point of the first system management interrupt and the number of instructions executed by the processor between two first system management interrupts after determining that the first system management interrupt is triggered.

[0078] Further, in a possible implementation manner of the embodiment of the present disclosure, the first determining unit 31 is further configured to: When it is determined that there is no repetition period in the autocorrelation function graph, determine the time points for generating the system management interrupt in a fixed time interval manner.

[0079] For the description of the features in the corresponding embodiments of the frequency control device, reference can be made to the relevant description in the corresponding embodiments of the frequency control method, which will not be elaborated here one by one.

[0080] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above-described embodiments of the frequency control method.

[0081] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the frequency control method when running.

[0082] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disc, etc., various media that can store computer programs.

[0083] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the frequency control method.

[0084] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the frequency control method.

[0085] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0086] The above has introduced in detail a frequency control system, method, device, electronic device, and storage medium provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A control system for a frequency, characterized in that, It includes a Basic Input / Output System (BIOS), a Baseboard Management Controller (BMC), and a shared memory; the shared memory is respectively connected to the BIOS and the BMC; The BMC is configured to determine a first repetition period and the time points at which system management interrupts are generated in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts, and send the time points at which system management interrupts are generated in the first repetition period to the shared memory; The shared memory, in response to a first acquisition instruction from the BIOS, sends the time points at which system management interrupts are generated in the first repetition period to the BIOS; The BIOS is configured to perform frequency control of the processor according to the time points at which system management interrupts are generated in the first repetition period.

2. The control system of the frequency according to claim 1, characterized in that The system further includes: After obtaining the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts, the BIOS sends the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts to the shared memory; The shared memory, in response to a second acquisition instruction from the BMC, sends the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts to the BMC.

3. The control system of the frequency according to claim 1, wherein The determining of the first repetition period and the time points at which system management interrupts are generated in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts includes: Drawing an autocorrelation function graph of instruction density versus time based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts; Determining the first repetition period in the autocorrelation function graph, and determining the time points at which system management interrupts are generated in the first repetition period based on a non-uniform system management interrupt method; wherein, the density of the system management interrupts is positively correlated with the change amplitude of the instruction density.

4. The control system of the frequency according to claim 1, characterized in that, The performing of the frequency control of the processor according to the time points at which system management interrupts are generated in the first repetition period includes: Setting a second system management interrupt based on the time points of the system management interrupts in the first repetition period; After determining that the second system management interrupt is triggered, the BIOS obtains the number of processor instructions executed between two occurrences of the second system management interrupt; Calculating the occupancy rate of the processor based on the number of processor instructions executed between two occurrences of the second system management interrupt; Determining the occupancy rate interval into which the occupancy rate falls, with different occupancy rate intervals corresponding to different frequency control schemes; Determining a frequency control scheme for performing frequency control of the processor according to the occupancy rate interval, and performing frequency control of the processor.

5. A method for controlling a frequency, characterized in that, It includes: Determining a first repetition period and the time points at which system management interrupts are generated in the first repetition period based on the time points of the first system management interrupts and the number of processor instructions between each pair of the first system management interrupts; Among them, the time point of the first system management interruption and the number of instructions of the processor between each first system management interruption are obtained in the basic input / output system; Perform frequency control on the processor according to the time point of generating the system management interruption in the first repetition period.

6. The control method of the frequency according to claim 5, wherein The determining of the first repetition period and the time point of generating the system management interruption in the first repetition period based on the time point of the first system management interruption and the number of instructions of the processor between each first system management interruption further includes: Draw an autocorrelation function graph of instruction density and time according to the time point of the first system management interruption and the number of instructions of the processor between each first system management interruption; Determine the first repetition period in the autocorrelation function graph, and determine the time point of generating the system management interruption based on the non-uniform system management interruption method in the first repetition period; wherein, the density of the system management interruption is positively correlated with the change amplitude of the instruction density.

7. The method according to claim 5, wherein The setting of the second system management interruption based on the time point of the system management interruption in the first repetition period and performing frequency control on the processor includes: Set the second system management interruption based on the time point of the system management interruption in the first repetition period; After determining that the second system management interruption is triggered, obtain the number of instructions executed by the processor between two second system management interruptions; Calculate the occupancy rate of the processor based on the number of instructions executed by the processor; Determine the occupancy rate interval that the occupancy rate falls into, and different occupancy rate intervals correspond to different frequency control schemes; Determine the frequency control scheme for performing frequency control on the processor according to the occupancy rate interval, and perform frequency control on the processor.

8. The method according to claim 7, wherein The determining of the frequency control scheme for performing frequency control on the processor according to the occupancy rate interval and performing frequency control on the processor includes: When the occupancy rate falls into the first occupancy rate interval, determine that the frequency control scheme is to reduce the working frequency of the processor until the occupancy rate of the processor after adjusting the working frequency falls into the second occupancy rate interval; When the occupancy rate falls into the second occupancy rate interval, determine that the frequency control scheme is to keep the working frequency of the processor unchanged; When the occupancy rate falls into the third occupancy rate interval, determine that the frequency control scheme is to increase the working frequency of the processor until the occupancy rate of the processor after adjusting the working frequency falls into the second occupancy rate interval.

9. The method according to claim 7, wherein The first repetition period includes a system management interruption sparse area and a system management interruption dense area; after determining the occupancy rate interval that the occupancy rate falls into and different occupancy rate intervals corresponding to different frequency control schemes, the method further includes: When the number of times that the occupancy rate of the processor corresponding to the system management interruption sparse area falls into the first occupancy rate interval or the third occupancy rate interval exceeds a preset threshold, obtain the second system management interruption time point and the number of instructions of the processor between each second system management interruption time point; Determine a second repetition period according to the second system management interruption time point and the number of instructions of the processor between each of the second system management interruption time points, and set system management interruptions based on a non-uniform system management interruption method within the second repetition period.

10. The method according to claim 5, wherein Before determining a first repetition period and the time points at which system management interruptions occur within the first repetition period based on the time points of the first system management interruptions and the number of instructions of the processor between each of the first system management interruptions, the method further includes: Setting the first system management interruption based on a fixed time interval; After determining that the first system management interruption is triggered, obtaining the time point of the first system management interruption and the number of instructions executed by the processor between two consecutive first system management interruptions.

11. The method according to claim 6, characterized in that, The determining of the first repetition period in the autocorrelation function graph further includes: When it is determined that there is no repetition period in the autocorrelation function graph, determining the time points at which system management interruptions are generated in a fixed time interval manner.

12. A control device for a frequency, characterized in that, Including: A determining unit configured to determine a first repetition period and the time points at which system management interruptions occur within the first repetition period based on the time points of the first system management interruptions and the number of instructions of the processor between each of the first system management interruptions; Wherein, the time points of the first system management interruptions and the number of instructions of the processor between each of the first system management interruptions are obtained in the basic input / output system; A control unit configured to perform frequency control of the processor according to the time points at which system management interruptions occur within the first repetition period.

13. An electronic device, characterized in that, Including: A memory configured to store a computer program; A processor configured to implement the steps of the frequency control method as described in any one of claims 5 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by the processor, implements the steps of the frequency control method as described in any one of claims 5 to 11.

15. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the frequency control method as described in any one of claims 5 to 11.

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