Microprocessor system based on core particles, architecture method, chip and electronic equipment

Abstract

The invention discloses a microprocessor system based on core particles, an architecture method, a chip and electronic equipment. The microprocessor system is based on a core particle architecture, and the microprocessor system comprises a plurality of computing chips with computing functions; the data wafer is coupled with the plurality of computing wafers, and is provided with an external interface unit, a memory read-write unit and a plurality of co-processing units for data acceleration processing; and a plurality of memory units arranged close to the data wafer. According to the microprocessor system provided by the invention, the co-processing unit is arranged on the data wafer, so that the space on the data wafer is effectively utilized, the computing power unloading is realized, and the high performance of the microprocessor system is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a microprocessor (CPU) system, an architecture method, a chip and an electronic device based on Chiplet. Background Art

[0002] As the difficulty of improving the process in the semiconductor industry is increasing, Moore's Law is gradually failing. If one wants to obtain a chip with better performance and higher integration, a more advanced packaging process must be adopted, and Chiplet has become the current main technical direction. Chiplet technology enables the corresponding chip solutions to have the following characteristics for industry manufacturers:

[0003] 1. Reduce implementation costs. In the chip manufacturing process, the larger the area of a single die, the greater the manufacturing difficulty. And due to the problem of manufacturing defects (random probability distribution), the larger the single die area, the higher the probability of defects on the single die, which means a sharp drop in the yield rate. Therefore, adopting Chiplet technology can obtain an appropriate die area, thereby achieving optimal cost control.

[0004] 2. A reasonable Chiplet solution allows different wafers with different processes to be used for analog IP and digital IP. For example, various high-speed IO PHY / Serdes modules can be placed on the IO die, and high-frequency digital logic can be placed on the calculate die, which can effectively reduce the backend implementation difficulty introduced when they were originally placed together.

[0005] 3. On this basis, it can also accelerate the time to market of chip products. Generally, analog IP has the characteristics of slow maturity and is not sensitive to the process. On a relatively backward process, through good design, the performance obtained can be no less than that of the latest process. Digital logic is just the opposite, and advanced processes have great advantages in operating frequency, power consumption, and area. Through Chiplet technology, the analog part of the system on chip (SoC) can be laid out on a relatively mature process, while the digital logic part can adopt the latest process, thus avoiding the long waiting time for the analog IP to mature in the new process.

[0006] 4. Through Chiplet technology, better performance can also be achieved. As mentioned above, after the main computing logic adopts the most advanced process, the highest energy efficiency of the computing part can be exerted, and at the same time, there is no obvious loss in the performance of high-speed IO / analog IP. Such a system is optimal in overall performance.

[0007] However, the current Chiplet-based CPU solutions are as follows:

[0008] 1) As Figure 1 shown, Solution 1 adopts the combination of Compute Die and Compute IO. Although this solution uses Chiplet technology and overcomes the yield problem. However, Figure 1 the DDRC in

[0009] is still configured on the Compute Die and does not achieve a complete separation of digital and analog. Figure 2 2) As

[0010] shown, Solution 2 adopts the Chiplet expansion solution. Although this solution reduces the area of a single Die, it also does not achieve a complete separation of analog and digital, so that analog and digital cannot adopt different processes and cannot achieve the best performance and cost. Figure 3 3) As shown, Solution 3 uses IO Die and multiple Compute Dies. Although this solution overcomes the problem of incomplete separation of digital and analog in Solution 1 and Solution 2, the area of the IO Die in this solution is mainly determined by the size of each IO, and the placement position of the IO is around the Die, which will inevitably result in a lot of unused blank space on the IO Die, thus causing waste of space. In addition, for high-performance computing chips in the data center, there are many processing tasks that need to be offloaded from the host to reduce the burden on the CPU. However, in Solution 3, the task offloading is actually achieved through another C Die (such as DPU), and this cost will be relatively high. There is no layout of a coprocessor for computing power offloading in the IO Die of Solution 3. Summary of the Invention

[0011] The object of the present invention aims to solve at least one of the above technical problems to a certain extent.

[0012] To achieve the above object, the present invention proposes a microprocessor system. The microprocessor system is based on a Chiplet architecture, and the microprocessor system includes: a plurality of computing wafers having computing functions; a data wafer coupled to the plurality of computing wafers, the data wafer being arranged with an external interface unit, a memory read / write unit, and a plurality of coprocessor units for data acceleration processing; and a plurality of memory units arranged close to the data wafer.

[0013] The coprocessor unit is located at a position close to the memory read / write unit.

[0014] The data wafer is cut into a plurality of pieces, and the cut plurality of data wafers are interconnected.

[0015] The multiple data chips after slicing are configured to adopt mesh interconnection or ring interconnection.

[0016] The multiple computing chips are configured to be arranged on the data chips in a stacked manner.

[0017] The multiple data chips are configured to be arranged in a stacked manner with respect to each other.

[0018] To achieve the above object, on the other hand, the present invention proposes an architecture method for a microprocessor system based on a Chiplet architecture. The architecture method includes: arranging multiple computing chips with computing functions; arranging data chips coupled to the multiple computing chips, and arranging an external interface unit, a memory read / write unit, and multiple coprocessor units for data acceleration processing on the data chips; arranging multiple memory units close to the data chips.

[0019] The architecture method further includes: arranging the coprocessor units at positions close to the memory read / write unit.

[0020] The architecture method further includes: slicing the data chips into multiple ones, and interconnecting the multiple sliced data chips.

[0021] The multiple sliced data chips adopt mesh interconnection or ring interconnection.

[0022] The architecture method further includes: arranging the multiple computing chips on the data chips in a stacked manner.

[0023] Arrange the multiple sliced data chips in a stacked manner with respect to each other.

[0024] To achieve the above object, on yet another aspect, the present invention provides a processor chip, which includes the aforementioned microprocessor system.

[0025] To achieve the above object, on yet another aspect of the embodiments of the present invention, there is provided an electronic device configured with the aforementioned processor chip.

[0026] The additional aspects and advantages of the present invention will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0028] Figure 1 is a schematic block diagram of a Chiplet-based CPU system in the prior art;

[0029] Figure 2It is a schematic block diagram of another Chiplet-based CPU system in the prior art;

[0030] Figure 3 It is another schematic block diagram of a Chiplet-based CPU system in the prior art;

[0031] Figure 4 It is a schematic block diagram of a microprocessor system based on Chiplet;

[0032] Figure 5 It is another schematic block diagram of a microprocessor system based on Chiplet;

[0033] Figure 6 It is yet another schematic block diagram of a microprocessor system based on Chiplet;

[0034] Figure 7 It is another schematic block diagram of a microprocessor system based on Chiplet;

[0035] Figure 8 It is a schematic flow diagram of an architecture method of a microprocessor; and

[0036] Figure 9 It is a schematic diagram of an electronic device. Detailed implementation manners

[0037] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present invention and should not be construed as a limitation to the present invention.

[0038] Chiplet, also known as a core chip or a small chip, is a packaging technology that disassembles a complex chip into a group of small chip units (Dies) with separate functions and encapsulates the module chips and the underlying basic chips through interconnection.

[0039] As mentioned above, although the current prior art has proposed systems based on Chiplet packaging, the existing system architectures have problems such as the inability to effectively separate analog and digital and the inability to completely offload the CPU computing power.

[0040] Therefore, the present invention proposes a microprocessor system, an architecture method, a chip, and an electronic device based on Chiplets to overcome the above-mentioned existing technical problems.

[0041] Figure 4 It is a schematic block diagram of a microprocessor system, as Figure 4 shown. The microprocessor system is based on the Chiplet architecture, and the microprocessor system includes:

[0042] A plurality of computing chips 10 with computing functions; a data chip 20 coupled to the plurality of computing chips 10, the data chip 20 being provided with an external interface unit 30, a memory read / write unit 40, and a plurality of coprocessor units 60 for data acceleration processing; and a plurality of memory units 50 arranged close to the data chip 20.

[0043] For example, as Figure 4 shown, Figure 4 the CPU system includes a data chip 20, which can be regarded as a management and data center for the plurality of computing chips 10. The data chip can be coupled to the plurality of computing chips 10 through the external interface unit 30. Each unit on the data chip can be connected through a bus to achieve the transmission of signal data. In the embodiment of the present invention, the data chip 20 is provided with a coprocessor unit 60, which supports programmability and can be used to support data acceleration processing for different applications. For example, network acceleration, storage acceleration, data encryption operations, etc. Since the coprocessor unit 60 is arranged on the data chip 20, the coprocessor unit 60 can assist in processing different computing requests, offload computing power, and reduce the data access path.

[0044] Taking data encryption operations as an example, since the prior art does not arrange a coprocessor unit dedicated to data acceleration processing on the D die, the prior art needs to use the core (C-core) of the C Chip for data acceleration processing. The specific process is as follows: The data to be processed is accessed from the memory (DDR) through the bus, and after the C-core finishes processing, the processed data is stored back into the DDR via the bus. The specific process is as follows:

[0045] ddr -> ddrc -> ddie - bus -> sio -> cdie - bus -> c-core -> cdie - bus -> sio -> ddie - bus -> ddrc -> ddr.

[0046] For the present invention, since the coprocessor unit is arranged on the D Die of the present invention, the coprocessor unit can assist in data encryption processing. Taking the coprocessor unit as the acceleration processor ACC as an example, the data access process of the present invention is as follows:

[0047] ddr -> ddrc -> ddie - bus -> ACC -> ddic - bus -> ddrc -> ddr.

[0048] As can be seen from the above process, the ACC accesses data from the DDR through the DDRC via the D die bus. After the data is processed, the processed data is then written back to the DDR through the DDRC via the D die bus. Obviously, compared with the existing access process described above, the access path in the embodiments of the present invention is greatly shortened.

[0049] As Figure 4 shown, the data wafer 20 of the present invention is provided with a memory read / write unit 40, which can read and write data to / from the memory unit 50. Compared with the prior art, arranging the memory read / write unit on the data wafer effectively separates the analog IP and the digital IP completely.

[0050] In a preferred manner, the coprocessor unit is located close to the memory read / write unit.

[0051] For example, as Figure 4 shown, the memory read / write units 40 are respectively arranged on the upper side of the data wafer 20. Therefore, Figure 4 the two coprocessor units 60 (ACC) in

[0052] are close to the memory read / write unit 40 located on the upper side of the data wafer 20, shortening the distance between the coprocessor unit 60 and the memory read / write unit 40, with a relatively short relative distance, thereby further reducing the data access path and realizing in-memory processing of data.

[0053] For example, considering that more and more functions are loaded onto the data wafer, the area of the data wafer will also become larger and larger accordingly. To improve the product yield, the present invention can further divide the data wafer into multiple ones, and the external interface unit, the memory read unit, and the coprocessor unit arranged in the data wafer are also arranged on the divided data wafers. As Figure 5 shown, Figure 5 the D Die in

[0054] is divided into two. Two ACCs, two SLCs, and one DDRC are arranged on each of the two divided D Dies. Similarly, for multiple C Dies that are coupled, after the D Die is divided, the C Dies are correspondingly coupled to the divided D Dies.

[0055] In a preferred manner, the multiple divided data wafers are configured to use grid interconnection or ring interconnection.

[0056] For example, ring interconnection, also known as Ring interconnect, is to connect the multiple D Dies after segmentation end to end to form a ring structure. Using this interconnection method can facilitate the effective interaction between each D Die without a central control transfer, and can reduce latency, which is beneficial to the expansion of D Die interconnection, thereby improving the overall performance of the CPU system. Grid interconnection, also known as Mesh interconnect, is to arrange multiple D Dies in a regular grid, and each D Die is connected to the adjacent D Dies in the same row and the same column. This interconnection method can increase the network dimension of multiple D Dies, improve the communication transmission bandwidth between them, reduce network latency, and at the same time is also beneficial to the increase of D Dies in the case of more D Die segmentation, thus supporting more cores.

[0057] In addition, the above two interconnection methods are only preferred, and the embodiments of the present invention are not limited to the above two interconnection methods. Those skilled in the art can adopt an interconnection method suitable for expansion according to actual needs, and no more limitations are made in this regard.

[0058] In a preferred manner, the multiple computing wafers are configured to be arranged on the data wafers in a stacked manner.

[0059] For example, in combination with Figure 5 as shown, Figure 5 the multiple C Dies in Figure 6 are distributed in a plane. However, as more functions are loaded in the CPU system and the number of configured C Dies increases, it will inevitably lead to a larger area of the multiple C Dies in the plane distribution, which will undoubtedly result in an overly large overall package size of the CPU system. Therefore, as Figure 6 shown, the present invention adopts 3D packaging technology (also known as 3D stacking technology) to stack multiple C Dies on the corresponding coupled D Dies. It should be noted that the stacking of multiple C Dies only changes their arrangement relationship with the D Dies. After stacking, the multiple C Dies are still coupled to the corresponding D Dies to achieve data communication transmission. In this way, this 3D stacking method can effectively utilize the space in the vertical direction and reduce the planar expansion area. At the same time, it can also reduce the communication path between the C Dies and the D Dies, and thus can provide a larger communication bandwidth.

[0060] In a preferred manner, the multiple data wafers are configured to be arranged in a stacked manner with each other.

[0061] Figure 7 Actually, it is a further stacking schematic diagram based on Figure 6 , as Figure 7As shown in the figure, in order to further reduce the overall area, the present invention can also stack multiple D Dies. That is to say, on the basis of stacking multiple C Dies, multiple D Dies can also be further stacked on each other to more optimize the overall package size of the CPU system.

[0062] In addition, the present invention also takes into account the heat dissipation problem caused by the stacking method. Therefore, the CPU system of the present invention can also be configured with appropriate heat dissipation channels and structures according to actual needs to ensure the stable operation of the overall CPU system.

[0063] In summary, the microprocessor system based on Chiplet provided by the present invention has the following advantages:

[0064] 1) It can separate analog IP and digital IP.

[0065] 2) A coprocessor unit is arranged on the D die, effectively realizing computing power offloading and better performance of the CPU system.

[0066] 3) The coprocessor unit is arranged close to the memory, further optimizing the access path and process, and the operation and processing speed of the CPU system is faster.

[0067] 4) Multiple Dies are arranged in a stacked manner, the package size of the CPU system is smaller, and the overall structure is more compact and reasonable.

[0068] 5) It can achieve the best performance, power consumption, and area (PPA).

[0069] Based on the same technical concept, the present invention also provides an architecture method. This architecture method applies the architecture of the CPU system, and this CPU system is based on the Chiplet architecture, as Figure 8 shown. The architecture method includes:

[0070] Step S810, arranging multiple computing chips with computing functions.

[0071] For example, based on the Chiplet packaging technology of the present invention, different functions are implemented on different chips (Dies).

[0072] Step S820, arranging data chips coupled to the multiple computing chips, and arranging an external interface unit, a memory read / write unit, and multiple coprocessor units for data acceleration processing on the data chips.

[0073] For example, for the purpose of facilitating the effective management and control of each C Die, the present invention configures a D Die (D Chip) coupled to a plurality of C Dies. Among them, an external interface unit, such as an IO, is arranged on the D Die, which is used for the interconnection between the D Die and the plurality of C Dies, and a memory read / write unit, such as a DDR controller (DDRC), is arranged for controlling data reading from or writing to the DDR memory. In the present invention, a plurality of coprocessor units are arranged in the space part of the D Die other than the external interface unit and the memory read / write unit, which can effectively utilize the space of the D Die. At the same time, the coprocessor units can assist in processing different computing requests, offload computing power, and reduce the data access path.

[0074] Step S830, arrange a plurality of memory units close to the data die.

[0075] For example, a plurality of memory units are arranged close to the data die, specifically close to the memory read / write unit, which facilitates the memory read / write unit to read and write data to and from the memory units.

[0076] Therefore, the architecture method provided by the present invention endows a single die with computing functions and data functions based on the Chiplet packaging technology, and a coprocessor unit is configured on the data die. On the one hand, the space on the data die can be effectively utilized, and on the other hand, computing power offloading can be achieved, improving the performance of the CPU system architecture. On the one hand, the memory reading unit is configured on the data die to effectively and thoroughly separate the analog IP and the digital IP.

[0077] In a preferred manner, the architecture method further includes: the coprocessor unit is arranged at a position close to the memory read / write unit.

[0078] In the present invention, the coprocessor is arranged at a position close to the memory read / write, further improving the overall processing ability and realizing near-memory processing of data, which can further improve the performance of the CPU system.

[0079] In a preferred manner, the architecture method further includes: the data die is divided into a plurality of parts, and the divided plurality of data dies are interconnected.

[0080] For example, as more complex business functions are configured on the D die, the single Die area of the D die will also become larger and larger. In order to effectively reduce the single Die area and enable the performance expansion of the CPU system, the present invention can further divide the D die according to the configuration of the D die. After the division, multiple D dies are interconnected. The area of each Die after such division is reduced compared to that before the division, thereby also avoiding defect problems caused by excessive area. For example, there are 4 ACCs arranged on the original D die, and the D die is interconnected with 8 C dies. If the D die is divided into 2, then each of the divided D dies is respectively arranged with 2 ACCs, and each D die is respectively connected to 4 C dies.

[0081] In the present invention, by further dividing the D die, the single Die area of the D die can be effectively reduced, and more services can be unloaded onto the D die, thereby facilitating the overall performance expansion of the CPU system.

[0082] In a preferred manner, the multiple data wafers after the division are interconnected by a grid or a ring.

[0083] In a preferred manner, the multiple computing wafers are configured to be arranged on the data wafers in a stacked manner.

[0084] For example, as mentioned above, the present invention is based on the Chiplet architecture. As more functions are loaded, the number of C dies in the entire CPU system is also increasing. The expansion of multiple C dies on the same plane will inevitably cause the overall package size of the CPU system to be too large. Therefore, the embodiment of the present invention adopts a 3D packaging method, specifically stacking multiple C dies on their corresponding coupled D dies. For example, multiple C dies can be vertically coupled to the D die to form a compact 3D structure.

[0085] In a preferred manner, the multiple data wafers after the division are arranged in a stacked manner with each other.

[0086] For example, multiple D dies can be vertically stacked with each other.

[0087] In the present invention, by architecting multiple Dies in a stacked manner, not only can the package area size be reduced compared to traditional planar packaging, making the package structure more compact and improving the space utilization rate, but also the interconnection path between Die parts can be reduced, improving the signal transmission speed and reliability between Dies, reducing signal delay and improving integrity, thereby overall improving the overall performance of the CPU system of the architecture and promoting the data transmission and processing speed.

[0088] For more details and advantages of the architecture method, reference can be made to the above introduction of the chiplet-based microprocessor, which will not be elaborated here.

[0089] Correspondingly, the present invention further provides a processor chip, which is the microprocessor system obtained based on the above-mentioned chiplet architecture.

[0090] Correspondingly, the present invention further provides an electronic device, which is configured with the above-mentioned processor chip.

[0091] As Figure 9 shown, it shows a schematic structural diagram of an electronic device 900 suitable for implementing the embodiments of the present invention. The electronic device in the embodiments of the present invention may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Tablet Computers), PMPs (Portable Multimedia Players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 9 The shown electronic device is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0092] As Figure 9 shown, the electronic device 900 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to the programs stored in the read-only memory (ROM) 902 or the programs loaded from the storage device 908 into the random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the electronic device 900 are also stored. The processing device 901, the ROM 602, and the RAM 903 are connected to each other through a bus 904. The input / output (I / O) interface 905 is also connected to the bus 904.

[0093] Generally, the following devices may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 908 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909. The communication device 909 can allow the electronic device 900 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 9 the shown electronic device 900 has various devices, it should be understood that it is not required to implement or include all the shown devices. More or fewer devices may be alternatively implemented or included.

[0094] The above description is only a preferred embodiment of the present invention and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present invention.

[0095] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present invention. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0096] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A microprocessor system, characterized in that, The microprocessor system is based on a chiplet architecture, and the microprocessor system includes: A plurality of computing dies with computing functions; A data die coupled to the plurality of computing dies, the data die being arranged with an external interface unit, a memory read / write unit, and a plurality of coprocessor units for data acceleration processing; A plurality of memory units arranged close to the data die.

2. The CPU system according to claim 1, characterized in that, The coprocessor units are located at positions close to the memory read / write unit.

3. The CPU system according to claim 1, wherein The data die is sliced into a plurality of pieces, and the sliced plurality of data dies are interconnected.

4. The CPU system according to claim 3, characterized in that, The sliced plurality of data dies are configured to use mesh interconnection or ring interconnection.

5. The CPU system according to claim 1, characterized in that, The plurality of computing dies are configured to be arranged on the data die in a stacked manner.

6. The CPU system according to claim 1, wherein The plurality of data dies are configured to be arranged in a stacked manner with respect to each other.

7. An architecture method, characterized in that, For a microprocessor system, the microprocessor system is based on a chiplet architecture, and the architecture method includes: Arranging a plurality of computing dies with computing functions; Arranging a data die coupled to the plurality of computing dies, and arranging an external interface unit, a memory read / write unit, and a plurality of coprocessor units for data acceleration processing on the data die; Arranging a plurality of memory units close to the data die.

8. The architecture method according to claim 7, wherein The architecture method further includes: The coprocessor units are arranged at positions close to the memory read / write unit.

9. The architecture method according to claim 7, wherein The architecture method further includes: The data die is sliced into a plurality of pieces, and the sliced plurality of data dies are interconnected.

10. The architecture method according to claim 9, wherein, The sliced plurality of data dies use mesh interconnection or ring interconnection.

11. The architecture method according to claim 7, characterized in that, The architecture method further includes: The plurality of computing dies are arranged on the data die in a stacked manner.

12. The architecture method according to claim 9, wherein The sliced plurality of data dies are arranged in a stacked manner with respect to each other.

13. A processor chip, characterized in that, The processor chip includes the microprocessor system based on the chiplet architecture as claimed in claims 1-6.

14. An electronic device, characterized in that, The electronic device is configured with the processor chip as claimed in claim 13 above.

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