Preparation method of DFB semiconductor laser

Abstract

The invention relates to a preparation method of a DFB (Distributed Feedback) semiconductor laser, which belongs to the technical field of semiconductor lasers and comprises the following steps of: 1, forming an epitaxial structure on a substrate; 2, forming a ridge waveguide structure; 3, forming a protective film layer on the upper part of the ridge waveguide structure and windowing; 4, spin-coating negative photoresist on the upper part of the ridge waveguide structure and exposing to form a first protective layer; step 5, forming a second protection layer; step 6, forming a first window; step 7, continuously windowing the first protection layer below the first window, and forming a second window; 8, performing magnetron sputtering gold plating by adopting a magnetron sputtering process, and at least forming a metal layer on the inner surface of the second window; step 9, removing the photoresist and the redundant metal layer, and only reserving the metal layers at the upper end of the ridge part and the upper ends of the protective film layers at the two sides of the ridge part to obtain a suspended electrode structure; the preparation method is simple in manufacturing and lower in cost, can effectively reduce parasitic capacitance, and is beneficial to realizing high-bandwidth and high-speed transmission of chips.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and particularly relates to a method for manufacturing a DFB semiconductor laser. Background Art

[0002] The advent of the 5G era means that high-speed optical modules have become the main components in the construction of communication and data centers. Currently, there are bottlenecks in the chip bandwidth and transmission rate of high-speed optical modules. For high-speed modulated semiconductor lasers, their bandwidth is affected by different factors, including the relaxation oscillation frequency and parasitic capacitance of the chip, etc. Among them, the magnitude of the parasitic capacitance usually directly affects the operating bandwidth of the laser. The parasitic capacitance restricts the injection current from entering the active region, affects the carrier recombination, and the influence of the parasitic capacitance on the bandwidth is more obvious at high frequencies. Therefore, for high-speed lasers, the parasitic capacitance should be minimized in chip design to reduce the impact of the parasitic capacitance on the modulation bandwidth.

[0003] The ridge waveguide laser is a common semiconductor laser. A ridge waveguide structure is constructed inside the ridge waveguide laser, and the ridge waveguide structure is used to confine the optical field and carriers, so that the laser propagation and oscillation modes in the resonant cavity are determined by waveguide theory. The ridge waveguide laser usually has advantages such as low threshold current, high output power, good beam quality, and single-mode output, and is widely used in the communication field.

[0004] The parasitic capacitance of existing ridge waveguide lasers usually includes: PN junction capacitance and metal electrode plate capacitance, etc. Among them, the PN junction capacitance is related to the design of the quantum well structure and material selection; the metal electrode plate capacitance can be adjusted by the electrode area, wire diameter, etc.; there are various forms of the ridge waveguide structure in existing ridge waveguide lasers. For example, in some ridge waveguide structures, the ridge part is relatively wide (usually greater than or much greater than 3 μm). When making electrodes on the ridge part, the electrodes are all located within the upper surface of the ridge part and no parasitic capacitance will be formed. Another example is that in some ridge waveguide structures, the ridge part is constructed as an inverted trapezoid structure. For example, a high-speed semiconductor laser chip with an inverted trapezoid structure disclosed in Chinese Patent CN109412020A has a relatively wide upper surface of the ridge part. When making electrodes on the ridge part, the electrodes are all located within the upper surface of the ridge part and it is not easy to form parasitic capacitance either; however, in some commonly used ridge waveguide structures, the width of the ridge part is very narrow, usually not exceeding 3 μm. When preparing ridge waveguide lasers using existing processes, electrodes will be formed on both sides of the ridge part, as shown in the attached Figure 1 - attached Figure 3As shown (A and B in the figure), it is a schematic structural diagram of a common existing ridge waveguide laser. The ridge waveguide structure in this kind of ridge waveguide laser can obtain good bandwidth in the case of low speed or low frequency. However, when the transmission rate or frequency increases, the working bandwidth of the laser will be significantly reduced, resulting in that this kind of ridge waveguide structure is not suitable for high-speed lasers. Because in this kind of ridge waveguide structure, the electrodes on both sides of the ridge (A and B in the figure) will form electrode capacitance at high speed, thus generating parasitic capacitance. The parasitic capacitance will limit the injection current into the active region and affect the carrier recombination. The influence of parasitic capacitance on the modulation bandwidth is very obvious at high frequencies. Therefore, this kind of ridge waveguide laser with a very narrow ridge is only suitable for low-speed lasers and not suitable for high-speed laser design. It is necessary to further optimize the ridge waveguide structure in the narrow-ridge ridge waveguide laser in order to further improve the laser bandwidth and achieve high-bandwidth and high-rate transmission of high-speed semiconductor lasers. To solve this technical problem, a feasible solution is to use a lithography machine with higher precision. When making the electrodes, the metal is only plated on the upper surface of the ridge and will not form electrodes on the side of the ridge. Although it can effectively reduce the metallization area of the electrodes and avoid generating parasitic capacitance, this method has many limiting conditions and the cost is very high (especially the cost of the lithography machine that can meet this preparation process is very high), which is not conducive to mass production. Therefore, how to eliminate the parasitic capacitance in the narrow-ridge ridge waveguide laser with lower cost, more versatility, and more convenient mass production, and prepare a narrow-ridge ridge waveguide laser suitable for high speed, is urgently to be solved. Summary of the Invention

[0005] In the first aspect of the present invention, to solve the above technical problems, a preparation method of a DFB semiconductor laser is provided, which can not only prepare a narrow-ridge ridge waveguide laser with lower cost, more versatility, and more convenient mass production, but also can form a floating electrode structure in the ridge waveguide structure, effectively eliminate the electrode capacitance, improve the chip bandwidth performance, and is beneficial to realizing high-bandwidth and high-rate transmission of the chip. The main idea is as follows:

[0006] A preparation method of a DFB semiconductor laser includes the following steps:

[0007] Step 1: Form an epitaxial structure on a substrate, and the outermost layer of the epitaxial structure is a contact layer;

[0008] Step 2: Form a ridge waveguide structure on the epitaxial structure. The ridge waveguide structure includes a ridge and trenches on both sides of the ridge, and the width of the ridge is 1-3 μm;

[0009] Step 3: Form a protective film layer on the upper part of the ridge waveguide structure, and open a window on the protective film layer to remove at least part of the protective film layer directly above the ridge to expose the contact layer at the upper end of the ridge, and the protective film layer remains in a state of covering at least both sides of the ridge;

[0010] Step 4: Spin-coat a negative photoresist on the upper part of the ridge waveguide structure and expose it to form a first protective layer;

[0011] Step 5: Spin-coat a positive photoresist on the first protective layer and expose it to form a second protective layer;

[0012] Step 6: Open a window in the second protective layer above the ridge waveguide structure and form a first window. The width of the first window is greater than or equal to the sum of the thickness of the ridge and the thickness of the protective film layers on both sides of the ridge;

[0013] Step 7: Continue to open a window in the first protective layer below the first window and form a second window to expose the contact layer exposed in Step 3. Above the protective film layer on the side of the ridge, the bottom of the second window is not lower than the upper surface of the contact layer;

[0014] Step 8: Use a magnetron sputtering process to magnetron sputter gold on the upper surface of the second protective layer and the inner surface of the second window to form a metal layer;

[0015] Step 9: Remove the photoresist and the excess metal layer, and only retain the metal layer at the upper end of the ridge and the upper ends of the protective film layers on both sides of the ridge to obtain a suspended electrode structure. The preparation method provided by this solution can not only form a suspended electrode structure in a narrow-ridge ridge waveguide structure, minimize the electrode metallization area to the greatest extent, and effectively eliminate the electrode capacitance, thereby further improving the laser bandwidth and achieving high-bandwidth and high-speed transmission of high-speed semiconductor lasers; moreover, this preparation method can be realized with existing equipment, making this preparation method more general, lower in cost (especially without the need to configure a higher-precision lithography machine), more conducive to mass production, and thus more meeting the market demand; in addition, this preparation method also adopts a double-exposure process using positive and negative photoresists to effectively prevent the metal electrode from exposing downward from both sides of the ridge during the preparation process, thereby more effectively eliminating the parasitic capacitance, improving the chip bandwidth performance, and being conducive to achieving high-bandwidth and high-speed transmission of the chip.

[0016] Further, it further includes Step 10: Open a window in the flat metal electrode area on one side of the ridge waveguide structure through a yellow light process to form a third window; and then form a flat metal electrode structure in the third window through a magnetron sputtering process;

[0017] Step 11: Grind and polish the back surface of the substrate and form an N-side metal layer through a magnetron sputtering process;

[0018] Step 12: Dissociate the Bar strip and form reflection film layers on the AR end face and the HR end face respectively.

[0019] Preferably, the epitaxial structure includes a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer, a P-type cladding layer, and a contact layer grown in sequence on the substrate.

[0020] Preferably, in step 2, the width of the ridge in the ridge waveguide structure is 1.5 μm, or 2 μm, or 2.5 μm.

[0021] Preferably, in step 2, the ridge waveguide structure is formed by using a RIE dry etching process or a wet etching process.

[0022] Preferably, in step 3, the thickness of the protective film layer is 0.3 - 1.5 μm. This is beneficial for achieving a better protection effect.

[0023] Preferably, in step 3, the protective film layer is a silicon oxide protective film layer.

[0024] Preferably, in step 3, the protective film layer is formed by using a plasma enhanced chemical vapor deposition process.

[0025] Preferably, in step 3, by opening a window in the protective film layer, the entire contact layer at the upper end of the ridge is exposed. This is beneficial for increasing the area of the metal layer on the contact layer, achieving a better conductive effect; and is beneficial for improving the stability of the suspended electrode structure.

[0026] Preferably, in step 3, after opening the window, the upper surfaces of the protective film layers on both sides of the ridge are flush with the upper surface of the ridge.

[0027] In the second aspect of the present invention, to solve the problem of reducing the preparation difficulty and making it easier to form the suspended electrode structure. Further, in step 3, along the direction close to the ridge, the upper surface of the protective film layer on the side of the ridge gradually slopes upward, and the top of the protective film layer is flush with the upper surface of the ridge. This is more beneficial for forming the suspended electrode structure subsequently, can reduce the difficulty of the subsequent gold plating process, and avoid plating metal layers on both sides of the ridge, thereby effectively avoiding the formation of parasitic capacitance on both sides of the ridge.

[0028] Preferably, the upper surface of the protective film layer is configured as a curved surface or an inclined surface. This is easier to achieve by etching, beneficial for reducing the preparation difficulty and being easier to form.

[0029] In the third aspect of the present invention, to solve the problem of more precisely controlling the morphology of the suspended electrode structure and avoiding the occurrence of electrode capacitance. Further, in step 6, a window is opened on the second protective layer by using a RIE dry etching process; in step 7, a window is opened on the first protective layer by using a RIE dry etching process. In this solution, a double exposure process is formed by using a positive and negative photoresist dry etching method, so as to more effectively control the morphology of the suspended electrode structure during the preparation process, effectively prevent the metal electrode from exposing downward from both sides of the ridge, thereby more reliably forming the suspended electrode structure, effectively eliminating the electrode capacitance, improving the chip bandwidth performance, and being beneficial for achieving high bandwidth and high speed transmission of the chip.

[0030] Further, during the process of fabricating the second window in step 7, the etching reaches the top of the protective film layers on both sides of the ridge, such that the upper surface of the protective film layer is lower than the bottom of the second window. Ensuring that the second protective layer between the upper surface of the protective film layer and the bottom of the second window is not etched away can prevent the formation of electrodes on both sides of the ridge during the subsequent gold plating process and is also conducive to the formation of a suspended electrode structure.

[0031] Further, in step 7, the regions of the protective film layers corresponding to both sides of the ridge at the bottom of the second window are in a horizontal state or an upwardly inclined state. This is more convenient for precisely controlling the morphology of the suspended electrode structure.

[0032] Compared with the prior art, the method for preparing a DFB semiconductor laser provided by the present invention can form a suspended electrode structure in a ridge waveguide structure more simply, at low cost, and with high reliability, effectively reducing the metallization area of the ridge waveguide electrodes, reducing the parasitic capacitance, achieving high bandwidth and high-speed transmission of the chip, and can effectively reduce the manufacturing cost of high-speed semiconductor laser chips, facilitating mass production, and better meeting market demands. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 FIG. is a side view of an existing narrow-ridge ridge waveguide laser without a planar metal electrode structure.

[0035] Figure 2 FIG. is a side view of an existing narrow-ridge ridge waveguide laser after a planar metal electrode structure is provided.

[0036] Figure 3 is Figure 2 a top view of.

[0037] Figure 4 FIG. is a schematic structural diagram of the epitaxial structure prepared in step 1 in the preparation method provided in Embodiment 1 of the present invention.

[0038] Figure 5 FIG. is a schematic structural diagram of the ridge waveguide structure prepared in step 2 in the preparation method provided in Embodiment 1 of the present invention.

[0039] Figure 6 FIG. is a schematic structural diagram after the formation of the protective film layer in step 3 in the preparation method provided in Embodiment 1 of the present invention.

[0040] Figure 7In the preparation method provided in Embodiment 1, it is a schematic structural diagram after spin-coating photoresist in Step 3.

[0041] Figure 8 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after developing and exposing in Step 3.

[0042] Figure 9 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after etching in Step 3.

[0043] Figure 10 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after removing photoresist in Step 3.

[0044] Figure 11 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after forming the first protective layer in Step 4.

[0045] Figure 12 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after forming the second protective layer in Step 5.

[0046] Figure 13 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after window opening in Step 6.

[0047] Figure 14 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after window opening in Step 7. The upper surface of the entire ridge (i.e., the entire grating layer) is exposed in the figure.

[0048] Figure 15 In the preparation method provided in Embodiment 1, on Figure 14 the basis of forming a metal layer.

[0049] Figure 16 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after removing photoresist and the excess metal layer in Step 9.

[0050] Figure 17 In the preparation method provided in Embodiment 1, it is a schematic structural diagram after forming the N-side metal layer in Step 11.

[0051] Figure 18 It is a side view of the DFB semiconductor laser prepared by the preparation method provided in Embodiment 1, without a planar metal electrode structure.

[0052] Figure 19 It is a side view of the DFB semiconductor laser prepared by the preparation method provided in Embodiment 1, after setting the planar metal electrode structure.

[0053] Figure 20 ForFigure 19 Top view.

[0054] Marking description in the figure: Substrate 1, epitaxial structure 11, N-side metal layer 12; lower waveguide layer 21, active layer 22, upper waveguide layer 23, grating layer 24, P-type cladding layer 25, contact layer 26, photoresist 27; ridge waveguide structure 3, ridge 31, trench 32; protective film layer 4, upper surface 41 of silicon oxide protective film layer; first protective layer 5, second window 51; second protective layer 6, first window 61; metal layer 7; suspended electrode structure 8, electrode 81; planar metal electrode structure 9. Specific implementation mode

[0055] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention.

[0056] Embodiment 1

[0057] In this embodiment, a preparation method of a DFB semiconductor laser is provided, including the following main steps:

[0058] Step 1, on the N-type indium phosphide substrate 1, the lower waveguide layer 21, the active layer 22, the upper waveguide layer 23, the grating layer 24, the P-type cladding layer 25 (P-type indium phosphide cladding layer) and the indium gallium arsenide contact layer 26 are sequentially grown by MOCVD, as Figure 4 shown, to form the epitaxial structure 11.

[0059] Step 2, on the above epitaxial structure 11, a ridge waveguide structure 3 is formed through an RIE dry etching process and a wet etching (hydrochloric acid and phosphoric acid etching solutions can be used) process, as Figure 5 shown. In implementation, the process of forming the ridge waveguide structure 3 by RIE dry etching and wet etching can be realized by the prior art. For ease of description, the ridge waveguide structure 3 includes a ridge 31 and trenches 32 on both sides of the ridge 31, as Figure 5As shown, the uppermost layer of the ridge 31 is the indium gallium arsenide contact layer 26, and the bottom surface of the trench 32 reaches at least the P-type indium phosphide cladding layer 25. In this embodiment, the ridge waveguide structure 3 is a left-right symmetric structure, the ridge 31 is a straight ridge, and the width of the ridge 31 is 1-3 μm, belonging to a narrow-ridge ridge waveguide structure 3. In a preferred embodiment, the width of the ridge 31 in the ridge waveguide structure 3 can be preferentially controlled to be 1.5 μm or 2 μm or 2.5 μm, etc.

[0060] Step 3, form a protective film layer 4 on the upper part of the epitaxial structure 11 (including the area where the ridge waveguide structure 3 is located), such as Figure 6 shown; in this step, the protective film layer 4 can preferably be a silicon oxide protective film layer 4. The silicon oxide protective film layer 4 covers the upper surface of the epitaxial structure 11, the inner surface of the trench 32, and the upper surface of the ridge 31, as Figure 6 shown. In this embodiment, along the direction from bottom to top, the ridge 31 sequentially includes a P-type indium phosphide cladding layer 25, an indium gallium arsenide contact layer 26, and a silicon oxide protective film layer 4; in implementation, the thickness of the silicon oxide protective film layer 4 is preferably controlled to be 0.3-1.5 μm. For example, in this embodiment, the thickness of the silicon oxide protective film layer 4 is 0.9 μm or 1 μm or 1.1 μm, etc., which is beneficial to achieving a better protection effect. Then, open a window on the silicon oxide protective film layer 4, as Figure 10 shown, at least remove at least part of the protective film layer 4 directly above the ridge 31 to expose at least part of the contact layer 26 at the upper end of the ridge 31, so as to form a metal electrode on the exposed contact layer 26 subsequently. In implementation, the silicon oxide protective film layer 4 can preferably be formed by plasma-enhanced chemical vapor deposition (PECVD) process. At the same time, the RIE dry etching process can also be preferably used to open a window on the protective film layer 4. In implementation, the etching depth can be controlled by precisely controlling parameters such as the etching time. The specific etching time and other parameters can be determined according to actual needs. For example, in implementation, by controlling parameters such as the etching time, only part of the protective film layer 4 directly above the ridge 31 can be etched away to expose part of the contact layer 26 of the ridge 31; another example is that in implementation, by controlling parameters such as the etching time, all of the protective film layer 4 directly above the ridge 31 can be just etched away, so that the contact layer 26 at the upper end of the ridge 31 is completely exposed. At this time, the upper surface of the protective film layer 4 on both sides of the ridge 31 can be flush with the upper surface of the ridge 31 (i.e., the upper surface of the contact layer 26), or slightly lower than the upper surface of the ridge 31 (i.e., the upper surface of the contact layer 26); it can be understood that in implementation, regardless of the size of the area of the protective film layer 4 etched away, the protective film layer 4 needs to maintain at least the state of covering both sides of the ridge, that is, both sides of the ridge 31 are always in the state of being covered by the protective film layer 4; as Figure 10As shown, in the preferred embodiment provided in this embodiment, through the RIE dry etching process, along the direction close to the ridge 31, the upper surface 41 of the protective film layer on the side of the ridge 31 gradually slopes upward, and the top of the protective film layer is flush with the upper surface of the ridge 31, as Figure 10 shown. This can not only ensure that the protective film layer completely wraps the side of the ridge 31, playing a role in protecting the ridge 31, but also is beneficial to the subsequent process for controlling the morphology of the suspended electrode structure 8, without causing obstacles and interference to the subsequent process; during implementation, the upper surface 41 of the protective film layer is preferably configured as an inclined surface or a curved surface, as Figure 10 shown.

[0061] Of course, during implementation, other processes can also be used to open windows in the silicon oxide protective film layer 4. For example, wet etching processes can also be used to open windows in the silicon oxide protective film layer 4; it can be understood that during implementation, both the RIE dry etching process and the wet etching process can be realized using existing technologies. For example, in this embodiment, the RIE dry etching process is used to open windows in the silicon oxide protective film layer 4. Specifically: First, a layer of photoresist is spin-coated on the silicon oxide protective film layer 4, as Figure 7 shown, to form a photoresist layer; then, through mask plate UV exposure, the window opening pattern is defined; then, a developer solution (such as AZ400K dilution solution) is used to dissolve the exposed area to form the required pattern, as Figure 8 shown. The pattern will serve as a mask for the subsequent etching process to protect the areas that do not need to be etched; then, the selected etching gas is introduced into the reaction chamber of the etching equipment, and by adjusting parameters such as gas flow rate and pressure, the reaction chamber is made to reach a suitable etching atmosphere and environment; then, a high-frequency electric field is applied in the reaction chamber to ionize the etching gas to form a plasma. By controlling parameters such as electric field strength, frequency, and power, the density, energy distribution, and types of active particles of the plasma can be adjusted, thereby precisely controlling the etching rate and selectivity; in the plasma environment, the area on the epitaxial structure 11 that is not masked by the photoresist (i.e., the silicon oxide protective film layer 4 at the window position) reacts with the active particles in the etching gas to form volatile compounds, and these compounds are pumped out of the reaction chamber under the action of a vacuum pump, thereby realizing the removal of the protective film layer 4 and gradually forming the required window opening structure, as Figure 9 shown; during the etching process, precisely control the etching time, temperature, gas flow rate, and plasma parameters, etc., to ensure the etching accuracy and obtain the morphology as Figure 9 shown. After the etching is completed, the photoresist is removed and the cleaning is carried out, as Figure 10 shown.

[0062] Step 4, spin-coat a negative photoresist on the upper part of the epitaxial structure 11 (including the area where the ridge waveguide structure 3 is located) and expose it to form a whole-surface first protective layer 5, as Figure 11As shown, specifically, the negative photoresist fills the trench 32 and covers the upper end of the ridge 31, and a flat first protective layer 5 is formed on the upper surface of the entire epitaxial structure 11, as Figure 11 shown, the upper surface of the ridge 31 is covered by the negative photoresist. In this embodiment, the first protective layer 5 mainly plays a protective role.

[0063] Step 5: Then, spin-coat and expose positive photoresist on the first protective layer 5 to form a second protective layer 6 on the first protective layer 5, as Figure 12 shown, the second protective layer 6 covers the first protective layer 5, enabling the second protective layer 6 to effectively protect the first protective layer 5.

[0064] Step 6: Then, open a window in the second protective layer 6 above the ridge waveguide structure 3, as Figure 13 shown. For ease of description, the window formed on the second protective layer 6 is called the first window 61. During implementation, an RIE dry etching process or a wet etching process can be preferably used to precisely open a window in the second protective layer 6. At the same time, during implementation, the width of the first window 61 is configured to be greater than or equal to the sum of the thickness of the ridge 31 and the thickness of the silicon oxide protective film layers 4 on both sides of the ridge 31, and the ridge 31 is directly opposite the first window 61 above, so as to use the first window 61 opened in the second protective layer 6 to precisely limit and control the subsequent windowing effect, thus making it more convenient to achieve a more precise windowing in the next step.

[0065] Step 7: Then, continue to open a window in the ridge waveguide structure 3 below the first window 61 through an RIE dry etching process or a wet etching process to form a second window 51 to expose the underlying indium gallium arsenide contact layer 26 (i.e., expose the upper end of the ridge 31). In this embodiment, an RIE dry etching process is preferably used to fabricate the second window 51. During implementation, parameters such as the etching time can be controlled to etch away the second protective layer 6 between the two protective film layers 4 on both sides of the ridge 31, so as to fabricate electrodes in the region between the two protective film layers 4 on both sides of the ridge 31 subsequently, ensuring that the electrodes cover the contact layer 26 of the ridge 31 and the electrodes are respectively butted against the protective film layers 4 on both sides of the ridge 31, avoiding unprotected areas between the electrodes and the protective film layers 4. By way of example, as Figure 14 shown, in this embodiment, by controlling parameters such as the etching time, all the second protective layer 6 directly above the ridge 31 is just etched away, exposing all the contact layer 26 at the upper end of the ridge 31, as Figure 14 shown, and at this time, it also just etches to the top of the protective film layers 4 on both sides of the ridge 31, as Figure 14As shown, the upper surface of the protective film layer 4 is lower than the bottom of the second window 51, that is, the second protective layer 6 between the upper surface of the protective film layer 4 and the bottom of the second window 51 is not etched away. It can be understood that during implementation, the area where the bottom of the second window 51 exceeds the upper surface of the contact layer 26 (that is, the area of the protective film layer corresponding to both sides of the ridge at the bottom of the second window) can be in a horizontal state or in an upwardly inclined state, as Figure 14 shown.

[0066] In this embodiment, in step 6, an RIE dry etching process is used to precisely open a window in the second protective layer 6. At the same time, in step 7, an RIE dry etching process is used to continue opening a window in the ridge waveguide structure 3 below the first window 61. Through the cooperation of steps 4 - 7, a positive and negative photoresist dry etching method (Etch Back process) is formed, which can more precisely control the morphology of the suspended electrode structure 8, effectively prevent the metal electrode from exposing downward from both sides of the ridge 31, and can more reliably form the suspended electrode structure 8, effectively eliminating the electrode capacitance, improving the chip bandwidth performance, and being beneficial to achieving high bandwidth and high-speed transmission of the chip.

[0067] Step 8, then a magnetron sputtering method is used for metal coating, as Figure 15 shown. Specifically, gold is magnetron sputtered on the upper surface of the second protective layer 6 and the inner surface of the second window 51 (including the upper surface of the ridge 31 and the partial side surfaces on both sides of the ridge 31 not covered by the silicon oxide protective film layer 4) to form a metal layer 7, as Figure 15 shown.

[0068] Step 9, remove the photoresist and the excess metal layer 7, and only retain the metal layer 7 at the upper end of the ridge 31 and the upper ends of the silicon oxide protective film layers 4 on both sides of the ridge 31 to obtain the suspended electrode structure 8 as Figures 16 - 18 shown, effectively eliminating the electrode capacitance and achieving the purpose of effectively reducing the parasitic capacitance. During implementation, the existing technology can be used to remove the photoresist and the excess metal layer 7, which will not be elaborated here. Step 10, through a yellow light process, a window is opened in the flat metal electrode area on one side of the ridge waveguide structure 3 to form a third window, and then a flat metal electrode structure 9 is formed in the third window through a magnetron sputtering process, as Figure 19 and Figure 20 shown.

[0069] Step 11, on the back of the InP substrate 11, grinding and polishing are carried out to thin it to 100μm ± 10μm; then an N-side metal layer 712 is formed through a magnetron sputtering method, as Figures 17 - 19 shown.

[0070] Step 12, the Bar strips are dissociated, and an AR anti-reflection film layer and an HR high-reflection film layer are formed on the AR end face and the HR end face respectively. At this point, the process is completed and a DFB semiconductor laser chip with a suspended electrode structure 8 is obtained.

[0071] The preparation method, for narrow ridge waveguide lasers, adopts a double exposure process to reduce the electrode metallization area above the ridge waveguide and form a suspended electrode structure 8, which can effectively reduce parasitic capacitance; at the same time, the preparation method is simple to manufacture and low in cost, and the size of the suspended electrode structure 8 can be precisely controlled by controlling the etching time (i.e., by controlling the Etch Back etching time) through a positive and negative resist dry etching method (Etch Back process), thereby further reducing the parasitic capacitance, which is conducive to realizing high-bandwidth and high-speed transmission of high-speed semiconductor lasers.

[0072] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for preparing a DFB semiconductor laser, characterized in that: The steps include: Step 1, forming an epitaxial structure on a substrate, wherein the outermost layer of the epitaxial structure is a contact layer; Step 2: forming a ridge waveguide structure on the epitaxial structure, wherein the ridge waveguide structure comprises a ridge and grooves on both sides of the ridge, and the width of the ridge is 1-3 μm; Step 3, forming a protective film layer on the upper part of the ridge waveguide structure, and opening a window in the protective film layer, removing at least a portion of the protective film layer directly above the ridge to expose the contact layer at the upper end of the ridge, and the protective film layer is kept in a state of covering at least both sides of the ridge; Step 4, spin-coating a negative resist on the upper portion of the ridge waveguide structure and exposing the negative resist to form a first protective layer; Step 5, spin-coating a positive resist on the first protective layer and exposing the positive resist to form a second protective layer; Step 6: Open a window in the second protective layer above the ridge waveguide structure to form a first window, wherein the width of the first window is greater than or equal to the sum of the thickness of the ridge portion and the thickness of the protective film layers on both sides of the ridge portion; Step 7, continue to open a window on the first protective layer below the first window, and form a second window to expose the contact layer exposed in step 3, and the bottom of the second window is not lower than the upper surface of the contact layer above the protective film layer on the side of the ridge; Step 8: performing magnetron sputtering gold plating by using a magnetron sputtering process to form a metal layer at least on the inner surface of the second window; Step 9: remove the photoresist and the excess metal layer, and only retain the metal layer above the upper end of the ridge and the protective film layer on both sides of the ridge to obtain a suspended electrode structure.

2. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: The method further includes step 10, opening a window in the planar metal electrode region on one side of the ridge waveguide structure by a yellow light process to form a third window; and then forming a planar metal electrode structure in the third window by a magnetron sputtering process; Step 11, grinding and polishing the back side of the substrate, and forming an N-side metal layer by a magnetron sputtering process; Step 12: The Bar strips are dissociated, and reflective film layers are formed on the AR end face and the HR end face respectively.

3. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: The epitaxial structure comprises a lower waveguide layer, an active layer, an upper waveguide layer, a grating layer, a P-type cladding layer and a contact layer which are sequentially grown on a substrate.

4. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: In step 2, the width of the ridge portion in the ridge waveguide structure is 1.5 μm, 2 μm, or 2.5 μm.

5. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: In step 3, the thickness of the protective film layer is 0.3-1.5 μm.

6. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: In step 3, a window is opened in the protective film layer to expose the entire contact layer at the upper end of the ridge.

7. The method for preparing a DFB semiconductor laser according to claim 6, characterized in that: In step 3, after the window is opened, the upper surfaces of the protective film layers on both sides of the ridge are flush with the upper surface of the ridge.

8. The method for preparing a DFB semiconductor laser according to claim 6, characterized in that: In step 3, after the window is opened, the upper surface of the protective film layer on the side of the ridge gradually tilts upward along the direction close to the ridge, and the top of the protective film layer is flush with the upper surface of the ridge.

9. The method for preparing a DFB semiconductor laser according to claim 8, characterized in that: The upper surface of the protective film layer on the side of the ridge is configured as a curved surface or an inclined surface.

10. The method for preparing a DFB semiconductor laser according to claim 1, characterized in that: In step 6, a window is opened on the second protective layer by using a RIE dry etching process; In step 7, a window is opened on the first protective layer by using a RIE dry etching process.

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