Digital-to-analog converter chip

Abstract

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a digital-to-analog converter chip. Background Art

[0002] Digital-to-analog conversion chips are widely used in fields such as wireless communication, direct digital synthesis, and instrumentation. Existing digital-to-analog conversion chips usually adopt Figure 1 the architecture diagram shown. It is powered by an analog power supply (AVDD / AVSS), a digital power supply (DVDD / DVSS), and a clock power supply (CVDD / CVSS), and is correspondingly divided into three power domains. The analog power supply is used to supply power to the current source array and the bias circuit. The digital power supply generates a logic voltage through an internal LDO to supply power to the decoding logic and other auxiliary digital circuits. The clock power supply generates a logic voltage through an internal LDO to supply power to the clock circuit and the latch.

[0003] In the prior art, in Figure 1 the digital-to-analog conversion chip with the architecture shown, there is an overvoltage problem at the connection of low-voltage devices between different power domains. For example, at the connection of the decoding logic and the latch, since the time for the LDOs in the digital power domain and the clock power domain to establish voltage during the power-on startup process may be different, the LDO (linear voltage regulator) in one voltage domain establishes voltage earlier than the LDO in the other voltage domain. Such a timing difference will cause a voltage difference exceeding the maximum withstand voltage of the low-voltage device between the gate and the source-drain of the input transistor of the latch, thereby causing an overvoltage problem, which may lead to device damage or unstable operation.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a digital-to-analog converter chip to at least solve the problem of overvoltage at the connection of low-voltage devices between different power domains of the existing digital-to-analog converter.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] The embodiment of the present invention provides a digital-to-analog converter chip, including an analog power supply for supplying power to the analog power domain, a digital power supply for supplying power to the digital power domain, and a clock power supply for supplying power to the clock power domain. The digital power domain includes a first linear voltage regulator, and the clock power domain includes a second linear voltage regulator. The power output terminals of the analog power supply, the digital power supply, and the clock power supply are respectively connected to a power detection circuit, and the power detection circuit outputs a power establishment signal after the power voltage of the power source it is connected to is established;

[0008] The digital power supply domain further includes a second AND gate unit connected in series to the input terminal of the first linear voltage regulator. The clock power supply domain includes a third AND gate unit connected in series to the input terminal of the second linear voltage regulator. Both the second AND gate unit and the third AND gate unit are configured to obtain the power supply establishment signal sent by the power supply detection circuit;

[0009] Among them, the second AND gate unit is configured to enable the first linear voltage regulator to start when it obtains the power supply establishment signals output by each of the power supply detection circuits; the third AND gate unit is configured to enable the second linear voltage regulator to start when it obtains the power supply establishment signals output by each of the power supply detection circuits.

[0010] Further, the analog power supply domain includes a current source unit, and the current source unit includes MOS transistors PM1, PM2, PM3a, PM3b, PM4a, and PM4b;

[0011] The source electrode of the MOS transistor PM1 is connected to the positive power supply voltage of the analog power supply. The gate electrode of the MOS transistor PM1 is connected to the bias voltage. The drain electrode of the MOS transistor PM1 is connected to the source electrode of the MOS transistor PM2. The source electrodes of the MOS transistors PM3a and PM3b are commonly connected and then connected to the drain electrode of the MOS transistor PM2. The drain electrode of the MOS transistor PM3a is connected to the source electrode of the MOS transistor PM4a. The drain electrode of the MOS transistor PM3b is connected to the source electrode of the MOS transistor PM4b. The gate electrodes of the MOS transistors PM4a and PM4b are connected to each other. The drain electrodes of the MOS transistors PM4a and PM4b are the two output terminals of the current source unit;

[0012] The gate electrodes of the MOS transistors PM3a and PM3b are respectively connected to the latches in the clock power supply domain.

[0013] Further, the analog power supply domain includes a first AND gate unit, a first protection circuit, and a first bias circuit. The first protection circuit and the first bias circuit are respectively connected to the output terminal of the first AND gate unit;

[0014] The clock power supply domain further includes an under-voltage lockout circuit, and the under-voltage lockout circuit is connected between the clock power supply ground voltage of the second linear voltage regulator and the input of the first AND gate unit;

[0015] After the second linear voltage regulator is started, the ground voltage of its clock power supply passes through the under-voltage lockout circuit, and the under-voltage lockout circuit outputs a control signal. After obtaining the power supply establishment signal output by the power supply detection circuit connected to the analog power supply and the control signal, the first AND gate unit is started and controls the first protection circuit and the first bias circuit.

[0016] Further, the first AND gate unit further includes a NOT gate unit and a delay unit. The NOT gate unit is connected in series to the output end of the first AND gate unit, and the delay unit is connected in series to the output end of the NOT gate unit. Both the NOT gate unit and the delay unit are connected to the first bias circuit and the first protection circuit.

[0017] After obtaining the power supply establishment signal output by the power supply detection circuit connected to the analog power supply and the control signal, the first AND gate unit outputs a first switch signal, the NOT gate unit outputs a second switch signal, and the delay unit outputs a third switch signal. The first switch signal, the second switch signal, and the third switch signal are used to control the start of the first bias circuit and the first protection circuit.

[0018] Further, the first protection circuit includes a MOS transistor PM5, a MOS transistor NM2, a MOS transistor NM1, a first switch, a second switch, a third switch, a first capacitor, and a first resistor.

[0019] The source of the MOS transistor PM5 is respectively connected to the drain of the MOS transistor PM1 and the gate of the MOS transistor PM5. The gate of the MOS transistor PM5 is used to connect a control voltage. The drain of the MOS transistor NM2 is connected to the source of the MOS transistor PM5, and the gate of the MOS transistor NM2 is connected to the drain of the MOS transistor PM5. The drain of the MOS transistor NM1 is respectively connected to the drain of the MOS transistor PM5 and the gate of the MOS transistor NM2. The gate of the MOS transistor NM1 is used to connect a control voltage, and the source of the MOS transistor NM1 is connected to the negative power supply voltage of the analog power supply.

[0020] The first capacitor is connected between the gate of the MOS transistor PM2 and the positive power supply voltage of the analog power supply. The common input terminal of the first switch and the first resistor connected in series is connected to the first capacitor, and the common output terminal is connected to a bias voltage. The second switch is connected in parallel with the structure of the first switch and the first resistor connected in series. One end of the third switch is connected to the input terminal of the second switch, and the other end is connected to the negative power supply voltage of the analog power supply.

[0021] Among them, the first switch is used to open and close under the action of the first switch signal, the second switch is used to open and close under the action of the third switch signal, and the third switch is used to open and close under the action of the second switch signal.

[0022] Further, the first bias circuit includes MOS transistors NM0, second resistor, MOS transistors NM9, NM10, NM6, NM4a, NM4b, NM7, PM6, PM11, PM0, NM3a, NM3b, NM3c, PM7a, PM7b, PM8a, PM8b, NM5a, NM5b, fourth switch, fifth switch, sixth switch, seventh switch, second capacitor, third resistor, PM9, PM10, NM8;

[0023] The gates of MOS transistors NM0, NM9, NM10, NM6, NM4a, NM4b, NM7 are connected to each other, and the sources of MOS transistors NM0, NM9, NM10, NM6, NM4a, NM4b, NM7 are all connected to the negative power supply voltage of the analog power supply;

[0024] The drain of MOS transistor NM0 is connected to the gate of MOS transistor NM0, the second resistor is connected between the drain of MOS transistor NM0 and the positive power supply voltage of the analog power supply, the drain of MOS transistor PM6 is respectively connected to the gate of MOS transistor NM6 and the drain of MOS transistor NM9, the drain of MOS transistor PM11 is connected to the source of MOS transistor NM6, the gate of MOS transistor PM11 is connected to the gate of MOS transistor NM6, the source of MOS transistor PM11 is connected to the positive power supply voltage of the analog power supply, the drain of MOS transistor PM0 is respectively connected to the drain of MOS transistor NM10 and the gate of MOS transistor NM0, and the source of MOS transistor PM0 is connected to the positive power supply voltage of the analog power supply;

[0025] The gate of the MOS transistor NM3a is connected to the low-noise regulated output voltage of the second linear regulator. The drain of the MOS transistor NM3a is connected to the drain of the MOS transistor NM3b. The source of the MOS transistor NM3a is connected to the source of the MOS transistor NM3b. The gate of the MOS transistor NM3b is connected to a given voltage VBC. The sources of the MOS transistor NM3b and the MOS transistor NM3c are both connected to the drain of the MOS transistor NM6. The gate of the MOS transistor NM3c is connected to the drain of the MOS transistor NM8. The drain of the MOS transistor NM3c is connected to the drain of the MOS transistor PM7b. The drain of the MOS transistor NM3b is connected to the drain of the MOS transistor PM8a;

[0026] The sources of the MOS transistor PM8a and the MOS transistor PM8b are both connected to the positive power supply voltage of the analog power supply. After the gates of the MOS transistor PM8a and the MOS transistor PM8b are connected, they are connected to the gates of the MOS transistor PM0 and the MOS transistor PM9. The drain of the MOS transistor PM8a is also connected to the source of the MOS transistor PM7a. The drain of the MOS transistor PM8b is also connected to the source of the MOS transistor PM7b. The gates of the MOS transistor PM7a, the MOS transistor PM7b, and the MOS transistor PM6 are connected to each other. The drain of the MOS transistor PM7a is connected to the drain of the MOS transistor NM5a. The drain of the MOS transistor PM7b is connected to the drain of the MOS transistor NM5b. The gate of the MOS transistor NM5a is respectively connected to the drain of the MOS transistor NM5a and the gate of the MOS transistor NM5b. The sources of the MOS transistor NM5a and the MOS transistor NM5b are both connected to the negative power supply voltage of the analog power supply. The gates of the MOS transistor NM5a and the MOS transistor NM5b are both connected to the drain of the MOS transistor NM4a;

[0027] The drain of the MOS transistor NM4b is connected to the drain of the MOS transistor NM5b. One end of the fourth switch is connected to the drain of the MOS transistor NM4b, and the other end is connected to the negative power supply voltage of the analog power supply. One end of the fifth switch is connected to the drain of the MOS transistor PM7b, and the other end is connected to the gate of the MOS transistor PM10. The sixth switch is connected between the other end of the fifth switch and the positive power supply voltage of the analog power supply. The series structure formed by the third resistor and the seventh switch is connected between the positive power supply voltage of the analog power supply and the gate of the MOS transistor PM10. One end of the second capacitor is connected to the other end of the fifth switch, and the other end is connected to the negative power supply voltage of the analog power supply;

[0028] The source of the MOS transistor PM9 is connected to the positive power supply voltage of the analog power supply. The drain of the MOS transistor PM9 is connected to the source of the MOS transistor PM10 and the gate of the MOS transistor NM3c. The gate of the MOS transistor PM10 is connected to the source of the MOS transistor PM10. The drain of the MOS transistor PM10 is connected to the drain of the MOS transistor NM7 and the gate of the MOS transistor NM8. The source of the MOS transistor NM8 is connected to the negative power supply voltage of the analog power supply;

[0029] Among them, the gate of the MOS transistor PM10 is connected to the MOS transistor PM5, and the gate of the MOS transistor NM7 is connected to the gate of the MOS transistor NM1.

[0030] Further, the given voltage VBC is generated by the bandgap reference in the analog power supply domain, and the difference between the given voltage VBC and the negative power supply voltage of the analog power supply is equal to the standard operating voltage of the low-voltage device.

[0031] Further, the analog power supply domain further includes a second protection circuit, and the second protection circuit includes a PMOS transistor M1, an NMOS transistor m2, and an NMOS transistor m1;

[0032] The source of the PMOS transistor M1 is connected to the source of the MOS transistor PM3a. The gate of the PMOS transistor M1 is connected to the positive power supply voltage of the analog power supply and the control voltage. The drain of the PMOS transistor M1 is connected to the gate of the NMOS transistor m2. The drain of the NMOS transistor m2 is connected to the source of the PMOS transistor M1. The source of the MOS transistor M2 is connected to the negative power supply voltage of the analog power supply. The drain of the NMOS transistor m1 is connected to the drain of the PMOS transistor M1. The source of the NMOS transistor m1 is connected to the negative power supply voltage of the analog power supply. The gate of the NMOS transistor m1 is connected to the control voltage.

[0033] Further, the analog power supply domain further includes a second bias circuit, and the second bias circuit includes an NMOS transistor m5, an NMOS transistor m4, an NMOS transistor m3, a PMOS transistor M5, a PMOS transistor M4, a fourth resistor, a first operational amplifier OTA2, a PMOS transistor M2, a PMOS transistor M3, an NMOS transistor m6, a second operational amplifier OTA1, and a fifth resistor;

[0034] The gates of the NMOS transistor m5, the NMOS transistor m4, the NMOS transistor m3, and the NMOS transistor m1 are connected to each other. The sources of the NMOS transistor m5, the NMOS transistor m4, and the NMOS transistor m3 are connected to the negative power supply voltage of the analog power supply;

[0035] The drain of the NMOS transistor m5 is connected to the drain of the PMOS transistor M5. The drain of the PMOS transistor M5 is connected to the gate of the PMOS transistor M5. The gate of the PMOS transistor M5 is respectively connected to the gate of the PMOS transistor M1 and the positive power supply voltage of the analog power supply. The source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M4. The source of the PMOS transistor M4 is connected to the positive power supply voltage of the analog power supply. The drain of the PMOS transistor M4 is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the drain of the NMOS transistor m4;

[0036] The gate of the PMOS transistor M4 is connected to the output terminal of the first operational amplifier OTA2. The positive input terminal of the first operational amplifier OTA2 is connected to the other end of the fourth resistor, and the negative input terminal is connected to the negative voltage source of the clock power supply;

[0037] The drain of the NMOS transistor m3 is respectively connected to the gate of the NMOS transistor m3 and the drain of the PMOS transistor M2. The sources of the PMOS transistor M2 and the PMOS transistor M3 are both connected to the positive power supply voltage of the analog power supply. The gates of the PMOS transistor M2 and the PMOS transistor M3 are connected to each other and then connected to the drain of the PMOS transistor M3. The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor m6. The source of the MOS transistor M6 is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the negative power supply voltage of the analog power supply. The output terminal of the second operational amplifier OTA1 is connected to the gate of the NMOS transistor m6. The negative input terminal of the second operational amplifier OTA1 is connected to one end of the fifth resistor.

[0038] Furthermore, the positive input terminal of the second operational amplifier OTA1 is connected to the reference voltage generated by the on-chip bandgap reference.

[0039] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present invention at least include:

[0040] In a digital-to-analog converter chip of the present invention, when the second AND gate unit and the third AND gate unit both obtain the power supply establishment signals output by the power supply detection circuits connected to different power supplies, the second AND gate unit enables the first linear voltage regulator to start, and the third AND gate unit enables the second linear voltage regulator to start. Thus, when the digital power supply voltage and the clock power supply are both established, the corresponding linear voltage regulators are started, avoiding the situation that the linear voltage regulator in the digital power supply domain establishes voltage earlier than the linear voltage regulator in the clock power supply domain, solving the problem that the time difference in establishing voltage during the power-on startup process of the low-dropout regulators (LDOs) in the digital power supply domain and the clock power supply domain may cause overvoltage of low-voltage devices, and improving the reliability of the digital-to-analog converter chip. Brief Description of the Drawings

[0041] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0042] Figure 1 It is a schematic diagram of the conventional architecture of an existing digital-to-analog converter chip;

[0043] Figure 2 It is the connection of the P-terminal current source and the external circuit in an existing digital-to-analog converter chip;

[0044] Figure 3 It is a schematic diagram of the architecture of a digital-to-analog converter chip according to an embodiment of the present invention;

[0045] Figure 4 It is a schematic connection diagram of the current source unit, the first protection circuit, and the first bias circuit according to an embodiment of the present invention;

[0046] Figure 5 It is a schematic connection diagram of the current source unit, the second protection circuit, and the second bias circuit according to an embodiment of the present invention. Detailed Description of the Embodiments

[0047] The embodiments of the present application will be described in detail below with reference to the drawings.

[0048] The following illustrates the embodiments of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. The present application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0049] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device can be implemented and this method can be practiced using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0050] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this application schematically. The diagrams only show the components related to this application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0051] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that these examples can be practiced without these specific details.

[0052] High-speed and high-precision current-steering DAC chips (digital-to-analog converter chips) are widely used in the fields of wireless communication, direct digital synthesis, and instrumentation. Their AC linearity and dynamic performance are one of the key indicators restricting system applications. To improve their high-frequency dynamic performance, the traditional design scheme is to use only high-voltage devices as the current-source transistors and output cascode transistors for the current-source unit, while using low-voltage devices operating in the saturation region as switch transistors. By utilizing the high cut-off frequency and small parasitic capacitance characteristics of low-voltage devices, the switching speed of the switches is increased and the energy of the output glitch impulse during a single switch is reduced, thereby improving dynamic performance indicators such as the spurious-free dynamic range (SFDR) and noise spectral density (NSD) of the output signal at high frequencies.

[0053] Figure 1The schematic diagram of the architecture of a DAC chip adopting a traditional design scheme is given. The DAC chip is powered by three power supplies, namely the analog power supply (AVDD / AVSS), the digital power supply (DVDD / DVSS), and the clock power supply (CVDD / CVSS). Among them, the analog power supply is used to power the current source array and the bias circuit; the digital power supply generates a logic voltage through an internal LDO (linear regulator) to power the decoding logic and other auxiliary digital circuits; the clock power supply generates a logic voltage through an internal LDO to power the clock circuit and the latch. The three groups of power supplies are connected to the outside of the chip through different PADs to avoid mutual interference between different modules through the power lines during data conversion. At the same time, AVSS, DVSS, and CVSS are connected to the outside of the chip through the EP pad on the package. The N-bit binary input digital signal BI(N-1:0) first generates an appropriate digital code pattern Codes through the decoding logic in the DVDD power domain, and then generates the control signals SWN / SWP for the switches of the current source units through the latch array, so as to control the current flow directions of different current source units. The decoding logic, the latch, and the switching transistors of the current source are all directly coupled through the gates.

[0054] Figure 2 The connection schematic diagram of a P-terminal current source unit and its peripheral circuits in a current-output DAC is given. Figure 2 In it, MOS transistors PM1, PM2, PM3a, PM3b, PM4a, and PM4b constitute the whole current source unit. Among them, MOS transistors PM1 and PM2 are current source transistors, MOS transistors PM4a and PM4b are output cascode transistors, and the right circuit is the bias circuit for generating PM1, PM2, PM4a, and PM4b. MOS transistors PM3a and PM3b are switching transistors. The high and low operating logic voltages of the switching transistors are VDDC and VSSC respectively, and their values are generated by the analog power supply through the global bias circuit. The difference between the two is the standard operating voltage of the low-voltage device. The gates of the switching transistors are directly coupled to the latch output. The LDO operating in the CVDD power domain generates the internal power supplies CVDDC / CVSSC from VDDC / VSSC to power the latch. The LDO operating in the DVDD power domain generates the internal power supplies DVDDC / DVSSC from VDDC / VSSC to power the decoding logic and other auxiliary digital circuits.

[0055] Figure 1 and 2 The circuit scheme shown has a potential overvoltage problem at the connection of low-voltage devices between different power domains. Specifically as follows:

[0056] 1. For the connection between the decoding logic and the latch, overvoltage occurs during the power-on startup process. If there is a time difference in the establishment processes of DVDD and CVDD, causing the LDO in one voltage domain to be established before the LDO in the other voltage domain, then the voltage difference between the gate and the source-drain of the input transistor of the latch will reach VDDC - VSS in the worst case, exceeding the maximum withstand voltage of the low-voltage device and resulting in an overvoltage process.

[0057] 2. For the connection between the latch and the switching transistor, if the output pins IOUTP / IOUTN are in an open-circuit condition (e.g., a solder joint is loose or the externally connected differential transimpedance amplifier is not powered on), at this time the current source output is open, and the source potential of the MOS transistor PM3a / MOS transistor PM3b will track the power supply voltage AVDD. The gate-source voltage difference of the switching transistor is AVDD - VSSC, resulting in an overvoltage phenomenon. This overvoltage problem may be more serious during the power-on startup process because if AVDD is established before CVDD, the voltage value of CVSSC is no longer VSSC but VSS at this time, and the gate-source voltage of the MOS transistor PM3a / MOS transistor PM3b will directly reach AVDD - VSS, resulting in a more serious overvoltage process.

[0058] Regarding the above chip reliability problems caused by overvoltage, most of the reported literature does not mention how to solve them.

[0059] Based on this, the embodiments of this specification propose a processing solution: as Figure 3 shown, a digital-to-analog converter chip of the present invention provides a power-on timing scheme for a low-dropout linear regulator that supplies power to a digital logic circuit and a latch. When the second AND gate unit 40 and the third AND gate unit 50 simultaneously obtain an analog power supply voltage establishment signal, a clock power supply voltage establishment signal, and a digital power supply voltage establishment signal, they enable the first linear regulator 10 in the digital power domain and the second linear regulator 20 in the clock power domain to start simultaneously, thereby avoiding the possible difference in the time of establishing voltage by the LDOs in the digital power domain and the clock power domain during the power-on startup process, solving the problem of overvoltage at the connection of low-voltage devices between different power domains of the existing digital-to-analog converter, and improving the reliability of the digital-to-analog converter chip. And during the power-on process, it can also avoid the overvoltage problem caused by the gate-source voltage of the current source transistor PM3a / MOS transistor PM3b directly reaching AVDD - VSS due to AVDD being established before CVDD.

[0060] The present invention also provides a power-on protection circuit and a bias circuit to protect the safety of the switching transistor when the three power supplies of the analog power supply, the digital power supply, and the clock power supply are in different power-on sequences.

[0061] The present invention also provides another power-on protection circuit and a bias circuit for protecting the switching transistor of the current source unit when the output pin of the digital-to-analog converter chip is in an open state.

[0062] The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

[0063] As Figure 3 shown, a digital-to-analog converter chip of the present invention includes an analog power supply for supplying power to the analog power supply domain, a digital power supply for supplying power to the digital power supply domain, and a clock power supply for supplying power to the clock power supply domain. The digital power supply domain includes a first linear voltage regulator 10, and the clock power supply domain includes a second linear voltage regulator 20.

[0064] Among them, the linear voltage regulator 20 described in the present invention is a low-dropout linear regulator (LDO).

[0065] Among them, the analog power supply, digital power supply, and clock power supply in the digital-to-analog converter chip of the present application are the same as those in the prior art, and are mainly used to supply power to the analog power supply domain, digital power supply domain, and clock power supply domain respectively.

[0066] Furthermore, the clock power supply domain further includes a latch array, the digital power supply domain further includes a decoding logic, and the analog power supply domain further includes a current source array and other circuit structures.

[0067] Among them, the connection method of different power supply domains is the same as that in the prior art and will not be elaborated here. The present application mainly focuses on protecting the power-on logic of the low-dropout linear regulators in the digital power supply domain and the clock power supply domain, as well as the protection circuit and bias circuit of the current source array.

[0068] Specifically, the power output terminals of the analog power supply, digital power supply, and clock power supply are respectively connected to a power detection circuit, and the power detection circuit outputs a power establishment signal after the power voltage of the power supply it is connected to is established.

[0069] Among them, the output terminal of the analog power supply is connected to a power detection circuit. When the voltage of the analog power supply is higher than a given threshold, its output follows the change of the voltage of the analog power supply, and when the power voltage of the analog power supply is lower than the given threshold, the output of the analog power supply is VSS (ground voltage or negative power voltage).

[0070] Among them, the specific circuit structure of the power detection circuit is the same as the existing circuit structure, and it is mainly used to output a power establishment signal AVDDOK when the power voltage of the analog power supply reaches the given threshold to indicate that the voltage of the analog power supply is established.

[0071] Among them, the working principles of the power detection circuits connected to the digital power supply and the clock power supply are the same as those of the power detection circuit connected to the analog power supply, and are respectively used to output a power supply establishment signal DVDDOK (used to indicate the establishment of the power supply voltage of the digital power supply) and a power supply establishment signal CVDDOK (used to indicate the establishment of the power supply voltage of the clock power supply).

[0072] Furthermore, the digital power supply domain further includes a second AND gate unit 40 connected in series to the input end of the first linear voltage regulator 10, and the clock power supply domain includes a third AND gate unit 50 connected in series to the input end of the second linear voltage regulator 20. Both the second AND gate unit 40 and the third AND gate unit 50 are used to obtain the power supply establishment signals sent by the power detection circuits. Among them, the second AND gate unit 40 is used to enable the first linear voltage regulator 10 to start when obtaining the power supply establishment signals output by each power detection circuit; the second AND gate unit 40 is used to enable the second linear voltage regulator 20 to start when obtaining the power supply establishment signals output by each power detection circuit.

[0073] Among them, the second AND gate unit 40 is powered by the digital power supply, and the third AND gate unit 50 is powered by the clock power supply.

[0074] Specifically, when the second AND gate unit 40 simultaneously obtains AVDDOK, DVDDOK, and CVDDOK, the second AND gate unit 40 generates an enable signal for the first linear voltage regulator 10 in the digital power supply domain. When the enable signal is high, the first linear voltage regulator 10 starts. Otherwise, regardless of whether the digital power supply is established or not, the output signal DVDDC (positive digital power supply voltage) and the output signal DVSSC (digital power supply ground voltage) of the first linear voltage regulator 10 are both VSS.

[0075] When the third AND gate unit 50 simultaneously obtains AVDDOK, DVDDOK, and CVDDOK, the third AND gate unit 50 generates an enable signal for the second linear voltage regulator 20 under the clock power supply. When the enable signal is high, the second linear voltage regulator 20 starts. Otherwise, regardless of whether the clock power supply is established or not, the output signal CVDDC (positive clock power supply voltage) and the output signal CVSSC (clock power supply ground voltage) of the second linear voltage regulator 20 are both VSS.

[0076] Through the second AND gate unit 40 and the third AND gate unit 50 of the present application, mutual control between the digital power supply and the clock power supply can be achieved, so that the first linear voltage regulator 10 in the digital power supply and the second linear voltage regulator 20 in the clock power supply can be established synchronously, ensuring the safety of the low-voltage devices directly coupled at the interface between the digital power supply domain and the clock power supply domain.

[0077] Furthermore, as Figures 4 - 5As shown, the analog power supply domain includes a current source unit, and the current source unit includes MOS transistors PM1, PM2, PM3a, PM3b, PM4a, and PM4b. Among them, the source of MOS transistor PM1 is connected to the positive power supply voltage of the analog power supply, the gate of MOS transistor PM1 is connected to the control voltage, the drain of MOS transistor PM1 is connected to the source of MOS transistor PM2, the sources of MOS transistors PM3a and PM3b are commonly connected and then connected to the drain of MOS transistor PM2, the drain of MOS transistor PM3a is connected to the source of MOS transistor PM4a, the drain of MOS transistor PM3b is connected to the source of MOS transistor PM4b, the gates of MOS transistors PM4a and PM4b are connected to each other, and the drains of MOS transistors PM4a and PM4b are the two output terminals of the current source unit. The gates of MOS transistors PM3a and PM3b are respectively connected to the latches in the clock power supply domain.

[0078] The current source unit of the present application supplies power to the analog power supply and is mainly used to provide a stable current.

[0079] As Figures 3 - 4 As shown, the analog power supply domain includes a first AND gate unit 30, a first protection circuit, and a first bias circuit. The first protection circuit and the first bias circuit are respectively connected to the output terminal of the first AND gate unit 30. The clock power supply domain further includes an under-voltage lockout circuit 60, and the under-voltage lockout circuit 60 is connected between the clock power supply ground voltage of the second linear voltage regulator 20 and the input of the first AND gate unit 30. Among them, after the second linear voltage regulator 20 is started, its clock power supply ground voltage outputs a control signal through the under-voltage lockout circuit 60. The first AND gate unit 30 starts and controls the first protection circuit and the first bias circuit after obtaining the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply.

[0080] Among them, the clock power supply negative power voltage output by the second linear voltage regulator 20 generates a control signal CLDOOK under the action of the under-voltage lockout circuit 60. After the first AND gate unit 30 simultaneously obtains the power establishment signal AVDDOK and the control signal CLDOOK output by the power detection circuit connected to the analog power supply, the first AND gate unit 30 starts and controls the first protection circuit and the first bias circuit, so that the first protection circuit and the first bias circuit provide a bias voltage and protection for the current source unit.

[0081] As Figures 3 - 4As shown, the first AND gate unit 30 further includes a NOT gate unit 70 and a delay unit 80. The NOT gate unit 70 is connected in series to the output terminal of the first AND gate unit 30, and the delay unit 80 is connected in series to the output terminal of the NOT gate unit 70. Both the NOT gate unit 70 and the delay unit 80 are connected to the first bias circuit and the first protection circuit. After obtaining the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply, the first AND gate unit 30 outputs a first switch signal F1. The NOT gate unit 70 outputs a second switch signal NF1, and the delay unit 80 outputs a third switch signal F1D. The first switch signal F1, the second switch signal NF1, and the third switch signal F1D are used to control the startup of the first bias circuit and the first protection circuit.

[0082] Specifically, the first protection circuit includes a MOS transistor PM5, a MOS transistor NM2, a MOS transistor NM1, a first switch K1, a second switch K2, a third switch K3, a first capacitor C1, and a first resistor R1. The source electrode of the MOS transistor PM5 is respectively connected to the drain electrode of the MOS transistor PM1 and the gate electrode of the MOS transistor PM5. The gate electrode of the MOS transistor PM5 is used to connect to the control voltage. The drain electrode of the MOS transistor NM2 is connected to the source electrode of the MOS transistor PM5, and the gate electrode of the MOS transistor NM2 is connected to the drain electrode of the MOS transistor PM5. The drain electrode of the MOS transistor NM1 is respectively connected to the drain electrode of the MOS transistor PM5 and the gate electrode of the MOS transistor NM2. The gate electrode of the MOS transistor NM1 is used to connect to the control voltage, and the source electrode of the MOS transistor NM1 is connected to the negative power supply voltage of the analog power supply. The first capacitor C1 is connected between the gate electrode of the MOS transistor PM2 and the positive power supply voltage of the analog power supply. The common input terminal of the first switch K1 and the first resistor R1 in series is connected to the first capacitor C1, and the common output terminal is connected to the bias voltage. The second switch K2 is connected in parallel with the structure of the first switch K1 and the first resistor R1 in series. One end of the third switch K3 is connected to the input terminal of the second switch K2, and the other end is connected to the negative power supply voltage of the analog power supply. Among them, the first switch K1 is used to open and close under the action of the first switch signal F1, the second switch K2 is used to open and close under the action of the third switch signal F1D, and the third switch K3 is used to open and close under the action of the second switch signal NF1.

[0083] Among them, the MOS transistors NM1, NM2, and PM5 form a super source follower and are connected to the drain electrode of the MOS transistor PM1. At the same time, the first switch K1, the second switch K2, the third switch K3, the first resistor R1, and the first capacitor C1 are inserted between the gate electrode of the MOS transistor PM2 and the bias voltage.

[0084] Among them, the first protection circuit is used to protect the current source unit.

[0085] As Figure 4As shown, the first bias circuit includes MOS transistor NM0, second resistor R2, MOS transistor NM9, MOS transistor NM10, MOS transistor NM6, MOS transistor NM4a, MOS transistor NM4b, MOS transistor NM7, MOS transistor PM6, MOS transistor PM11, MOS transistor PM0, MOS transistor NM3a, MOS transistor NM3b, MOS transistor NM3c, MOS transistor PM7a, MOS transistor PM7b, MOS transistor PM8a, MOS transistor PM8b, MOS transistor NM5a, MOS transistor NM5b, fourth switch K4, fifth switch K5, sixth switch K6, seventh switch K7, second capacitor C2, third resistor R3, MOS transistor PM9, MOS transistor PM10, MOS transistor NM8; the gates of MOS transistor NM0, MOS transistor NM9, MOS transistor NM10, MOS transistor NM6, MOS transistor NM4a, MOS transistor NM4b, MOS transistor NM7 are connected to each other, and the sources of MOS transistor NM0, MOS transistor NM9, MOS transistor NM10, MOS transistor NM6, MOS transistor NM4a, MOS transistor NM4b, MOS transistor NM7 are all connected to the negative power supply voltage of the analog power supply; the drain of MOS transistor NM0 is connected to the gate of MOS transistor NM0, the second resistor R2 is connected between the drain of MOS transistor NM0 and the positive power supply voltage of the analog power supply, the drain of MOS transistor PM6 is respectively connected to the gate of MOS transistor NM6 and the drain of MOS transistor NM9, the drain of MOS transistor PM11 is connected to the source of MOS transistor NM6, the gate of MOS transistor PM11 is connected to the gate of MOS transistor NM6, the source of MOS transistor PM11 is connected to the positive power supply voltage of the analog power supply, the drain of MOS transistor PM0 is respectively connected to the drain of MOS transistor NM10 and the gate of MOS transistor NM0, the source of MOS transistor PM0 is connected to the positive power supply voltage of the analog power supply; the gate of MOS transistor NM3a is connected to the low-noise regulated output voltage of the second linear regulator 20, the drain of MOS transistor NM3a is connected to the drain of MOS transistor NM3b, the source of MOS transistor NM3a is connected to the source of MOS transistor NM3b, the gate of MOS transistor NM3b is connected to the given voltage VBC, the sources of MOS transistor NM3b and MOS transistor NM3c are both connected to the drain of MOS transistor NM6, the gate of MOS transistor NM3c is connected to the drain of MOS transistor NM8, the drain of MOS transistor NM3c is connected to the drain of MOS transistor PM7b, the drain of MOS transistor NM3b is connected to the drain of MOS transistor PM8a;The source electrodes of MOS transistor PM8a and MOS transistor PM8b are both connected to the positive power supply voltage of the analog power supply. After the gate electrodes of MOS transistor PM8a and MOS transistor PM8b are connected, they are connected to the gate electrodes of MOS transistor PM0 and MOS transistor PM9. The drain electrode of MOS transistor PM8a is also connected to the source electrode of MOS transistor PM7a, and the drain electrode of MOS transistor PM8b is also connected to the source electrode of MOS transistor PM7b. The gate electrodes of MOS transistor PM7a, MOS transistor PM7b, and MOS transistor PM6 are connected to each other. The drain electrode of MOS transistor PM7a is connected to the drain electrode of MOS transistor NM5a, and the drain electrode of MOS transistor PM7b is connected to the drain electrode of MOS transistor NM5b. The gate electrode of MOS transistor NM5a is connected to the drain electrode of MOS transistor NM5a and the gate electrode of MOS transistor NM5b respectively. The source electrodes of MOS transistor NM5a and MOS transistor NM5b are both connected to the negative power supply voltage of the analog power supply. The gate electrodes of MOS transistor NM5a and MOS transistor NM5b are both connected to the drain electrode of MOS transistor NM4a; the drain electrode of MOS transistor NM4b is connected to the drain electrode of MOS transistor NM5b. One end of the fourth switch K4 is connected to the drain electrode of MOS transistor NM4b, and the other end is connected to the negative power supply voltage of the analog power supply. One end of the fifth switch K5 is connected to the drain electrode of MOS transistor PM7b, and the other end is connected to the gate electrode of MOS transistor PM10. The sixth switch K6 is connected between the other end of the fifth switch K5 and the positive power supply voltage of the analog power supply. The series structure formed by the third resistor R3 and the seventh switch K7 is connected between the positive power supply voltage of the analog power supply and the gate electrode of MOS transistor PM10. One end of the second capacitor C2 is connected to the other end of the fifth switch K5, and the other end is connected to the negative power supply voltage of the analog power supply; the source electrode of MOS transistor PM9 is connected to the positive power supply voltage of the analog power supply. The drain electrode of MOS transistor PM9 is connected to the source electrode of MOS transistor PM10 and the gate electrode of MOS transistor NM3c. The gate electrode of MOS transistor PM10 is connected to the source electrode of MOS transistor PM10. The drain electrode of MOS transistor PM10 is connected to the drain electrode of MOS transistor NM7 and the gate electrode of MOS transistor NM8. The source electrode of MOS transistor NM8 is connected to the negative power supply voltage of the analog power supply; among them, the gate electrode of MOS transistor PM10 is connected to MOS transistor PM5, and the gate electrode of MOS transistor NM7 is connected to the gate electrode of MOS transistor NM1.;

[0086] Further, the given voltage VBC is generated by the bandgap reference in the analog power supply domain, and the difference between the given voltage VBC and the negative power supply voltage of the analog power supply is equal to the standard operating voltage of the low-voltage device.

[0087] As Figure 4 shown, Figure 4The upper half of the dashed-line box in the middle is a bias circuit for generating the gate control voltages VBNPON / VBPPON of MOS transistor NM1 and MOS transistor PM5. Among them, the gate control voltage VBNPON is the control voltage connected to MOS transistor PM5, and the gate control voltage VBPPON is the control voltage connected to MOS transistor NM1.

[0088] MOS transistors NM3a, NM3b, NM3c, MOS transistors NM5a, NM5b, NM6, MOS transistors PM7a, PM7b, MOS transistors PM8a, PM8b form a folded operational amplifier with two positive inputs and one negative input. During the power-on process of the analog power supply AVDD, the first switch signals F1 and F1D are both low, and the second switch signal NF1 is high. The gate of MOS transistor PM10 is connected to the output point of the folded operational amplifier.

[0089] After the power supply voltage of the analog power supply exceeds the threshold voltage of MOS transistor NM0, the branch where MOS transistor NM0 and the second resistor R2 are located conducts, and all current sources with their gates connected to the gate of MOS transistor NM0 and MOS transistors PM0, PM8a, PM8b, PM9 are activated. However, at this time, MOS transistor PM6 is in the non-conducting state, so the current flowing downward from MOS transistor PM7b is 0, and MOS transistor NM4b pulls down the gate voltage of MOS transistor PM10 to VSS.

[0090] When the power supply voltage of the analog power supply further rises, MOS transistor PM6 conducts, and the folded operational amplifier is activated. The effect of negative feedback makes the source potential of MOS transistor PM10 track the maximum of the gate potentials between MOS transistors NM3a and NM3b. The voltage of MOS transistor NM3a is connected to the output CVDDC of the third linear voltage regulator in the clock power supply domain, and the voltage of MOS transistor NM3b is connected to the given voltage VBC. VBC is generated by the bandgap reference in the analog power supply domain, and the voltage difference between its value and VSS is exactly equal to the standard operating voltage of the low-voltage device. When the voltage amplitude of the analog power supply does not activate the bandgap reference, the given voltage VBC remains at VSS, and when the analog power supply increases to activate the bandgap reference, the given voltage VBC is established to the preset value without overshoot (not exceeding the target value).

[0091] The gate voltages of MOS transistor PM10 and MOS transistor NM7 at the output of the first bias circuit are respectively applied to the gates of MOS transistor PM5 and MOS transistor NM1 of the super source follower. During the period when the first switching signal F1 is low, the first bias circuit ensures that the drain voltage of MOS transistor PM1 is always the maximum value between the output voltage CVDDC of the second linear voltage regulator 20 and the given voltage VBC. At the same time, the gate of MOS transistor PM2 is connected to VSS and is in the linear region. The sources of MOS transistor PM3a / MOS transistor PM3b are connected to the drain of MOS transistor PM1. In this way, the voltage difference between the gate and the source-drain of MOS transistor PM3a / MOS transistor PM3b can ensure that the overvoltage process will never occur during the period when the first switching signal F1 is low.

[0092] When Figure 3 the output of the UVLO (under-voltage lockout circuit 60) suspended under CVSSC is high, it indicates that the second linear voltage regulator 20 in the clock power supply domain has been established. At this time, the first switching signal F1 becomes high, the first switch K1 closes, and the gate of MOS transistor PM2 is connected to VBP2 through the first resistor R1. The gate potential is disconnected from VSS and exponentially builds from VSS to VBP2 through the first-order RC network composed of the first resistor R1 and the first capacitor C1. Its time constant is R1C1. At the same time, the fourth switch K4 and the seventh switch K7 close, and the fifth switch K5 opens. The gate of MOS transistor PM10 is disconnected from the output of the folded amplifier and starts to exponentially build to AVDD through the first-order RC network composed of the third resistor R3 and the second capacitor C2. Its time constant is R2C2. After the gate potentials of MOS transistor PM2 and MOS transistor PM10 build up to a sufficient and appropriate amplitude, the second switching signal NF1 becomes high, and the second switch K2 and the sixth switch K6 open, further providing a low-resistance path between the gate of MOS transistor PM10 and the analog power supply, and between the gate of MOS transistor PM2 and the bias voltage VBP2. Thereafter, MOS transistor PM5 is completely cut off, and the gate of MOS transistor PM2 is completely connected to the bias voltage VBP2, and the current source unit enters the normal operating mode.

[0093] Through the above two-step switch opening method of the present invention, it can effectively ensure that at the moment of switch opening, the source potential of MOS transistor PM3a and MOS transistor PM3b will not briefly experience the overvoltage process due to parasitic capacitance, thus solving the problem that the existing current source is prone to overvoltage during the power-on process.

[0094] Such as Figure 5As shown, the analog power supply domain further includes a second protection circuit. The second protection circuit includes PMOS transistor M1, NMOS transistor m2, and NMOS transistor m1. The source of PMOS transistor M1 is connected to the source of MOS transistor PM3a. The gate of PMOS transistor M1 is connected to the positive power supply voltage of the analog power supply and the control voltage. The drain of PMOS transistor M1 is connected to the gate of NMOS transistor m2. The drain of NMOS transistor m2 is connected to the source of PMOS transistor M1. The source of MOS transistor M2 is connected to the negative power supply voltage of the analog power supply. The drain of NMOS transistor m1 is connected to the drain of PMOS transistor M1. The source of NMOS transistor m1 is connected to the negative power supply voltage of the analog power supply. The gate of NMOS transistor m1 is connected to the control voltage.

[0095] Figure 5 A protection circuit for the current output pin of the digital-to-analog converter chip in an open state is given. The super source follower composed of PMOS transistor M1, PMOS transistor M2, and NMOS transistor m1 is connected to the sources of MOS transistors PM3a and PM3b. Under normal operation, PMOS transistor M1 is in the cut-off region, and the current source current only flows through MOS transistors PM3a and PM3b to the outside of the chip. When the output pin is open, PMOS transistor M1 conducts, and the current source current flows through NMOS transistor m2 to AVSS. The source potentials of MOS transistors PM3a and PM3b are controlled at the gate potential of PMOS transistor M1 minus the gate-source voltage difference in its conducting state. In the design, it only needs to be ensured that the gate-source voltage difference of MOS transistors PM3a / PM3b is less than or equal to the standard operating voltage of the low-voltage device in this state.

[0096] Further, the analog power supply domain further includes a second bias circuit, and the second bias circuit includes NMOS transistor m5, NMOS transistor m4, NMOS transistor m3, PMOS transistor M5, PMOS transistor M4, fourth resistor R4, first operational amplifier OTA2, PMOS transistor M2, PMOS transistor M3, NMOS transistor m6, second operational amplifier OTA1, and fifth resistor R5; the gates of NMOS transistor m5, NMOS transistor m4, NMOS transistor m3, and NMOS transistor m1 are connected to each other, and the sources of NMOS transistor m5, NMOS transistor m4, and NMOS transistor m3 are connected to the negative power supply voltage of the analog power supply; the drain of NMOS transistor m5 is connected to the drain of PMOS transistor M5, the drain of PMOS transistor M5 is connected to the gate of PMOS transistor M5, the gate of PMOS transistor M5 is respectively connected to the gate of PMOS transistor M1 and the positive power supply voltage of the analog power supply, the source of PMOS transistor M5 is connected to the drain of PMOS transistor M4, the source of PMOS transistor M4 is connected to the positive power supply voltage of the analog power supply, the drain of PMOS transistor M4 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the drain of NMOS transistor m4; the gate of PMOS transistor M4 is connected to the output terminal of the first operational amplifier OTA2, the positive input terminal of the first operational amplifier OTA2 is connected to the other end of the fourth resistor R4, and the negative input terminal is connected to the negative voltage source of the clock power supply; the drain of NMOS transistor m3 is respectively connected to the gate of NMOS transistor m3 and the drain of PMOS transistor M2, the sources of PMOS transistor M2 and PMOS transistor M3 are both connected to the positive power supply voltage of the analog power supply, the gates of PMOS transistor M2 and PMOS transistor M3 are connected to each other and then connected to the drain of PMOS transistor M3, the drain of PMOS transistor M3 is connected to the drain of NMOS transistor m6, the source of MOS transistor M6 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the negative power supply voltage of the analog power supply, the output terminal of the second operational amplifier OTA1 is connected to the gate of NMOS transistor m6, and the negative input terminal of the second operational amplifier OTA1 is connected to one end of the fifth resistor R5; the positive input terminal of the second operational amplifier OTA1 is connected to the reference voltage generated by the on-chip bandgap reference.

[0097] The bias circuit for the gate voltages of PMOS transistor M1 and NMOS transistor m1 is given within the dashed box in the figure. VREF is the reference voltage generated by the on-chip bandgap reference. The reference voltage generates a current through the fifth resistor R5. This current flows through the fourth resistor R4 after passing through two pairs of current mirrors formed by PMOS transistor M2, PMOS transistor M3, NMOS transistor m3, and NMOS transistor m4. The first operational amplifier OTA2 forces the drain voltage of PMOS transistor M5 to be equal to the sum of the voltage difference between VSSC and the fourth resistor R4. By adjusting the ratio between the fourth resistor R4 and the fifth resistor R5, the voltage difference between the source voltage of PMOS transistor M5 and VSSC can be precisely adjusted, thereby reasonably setting the gate control voltage of PMOS transistor M1.

[0098] A digital-to-analog converter chip of the present invention proposes a power-on timing scheme for the low-dropout linear regulator used for powering the digital logic circuit and latch inside the chip, thereby avoiding the problem of overvoltage of low-voltage devices caused by different power-on times of the linear regulator connected to the digital power supply and the clock power supply. The present invention can also protect the current source unit during power-on through the first protection circuit and the first bias circuit, and protect the safety of the current source switching transistor under different power-on sequences of the analog power supply, digital power supply, and clock power supply. The present invention can protect the switching transistor of the current source unit when the output pin of the current source is in an open circuit state through the second protection circuit and the second bias circuit.

[0099] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can refer to the partial descriptions of the system embodiments.

[0100] As described above, only the specific implementation manners of the present application are provided, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A digital-to-analog converter chip, comprising an analog power supply for supplying power to an analog power domain, a digital power supply for supplying power to a digital power domain, and a clock power supply for supplying power to a clock power domain, wherein the digital power domain comprises a first linear regulator, and the clock power domain comprises a second linear regulator, wherein: The power output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected to a power detection circuit, and the power detection circuit outputs a power establishment signal after the power supply voltage of the power supply connected to itself is established; The digital power domain further includes a second AND gate unit connected in series to the input end of the first linear regulator, and the clock power domain includes a third AND gate unit connected in series to the input end of the second linear regulator, and the second AND gate unit and the third AND gate unit are both used to obtain the power establishment signal sent by the power detection circuit; Among them, the second AND gate unit is used to enable the first linear regulator to start when the power supply establishment signal output by each of the power supply detection circuits is obtained; the third AND gate unit is used to enable the second linear regulator to start when the power supply establishment signal output by each of the power supply detection circuits is obtained.

2. The digital-to-analog converter chip according to claim 1, characterized in that: The analog power domain includes a current source unit, and the current source unit includes a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM3a, a MOS transistor PM3b, a MOS transistor PM4a, and a MOS transistor PM4b; The source of the MOS transistor PM1 is connected to the positive power supply voltage of the analog power supply, the gate of the MOS transistor PM1 is connected to the bias voltage, the drain of the MOS transistor PM1 is connected to the source of the MOS transistor PM2, the sources of the MOS transistor PM3a and the MOS transistor PM3b are connected together and then connected to the drain of the MOS transistor PM2, the drain of the MOS transistor PM3a is connected to the source of the MOS transistor PM4a, the drain of the MOS transistor PM3b is connected to the source of the MOS transistor PM4b, the gate of the MOS transistor PM4a and the gate of the MOS transistor PM4b are connected to each other, and the drains of the MOS transistor PM4a and the MOS transistor PM4b are two output ends of the current source unit; The gate of the MOS transistor PM3a and the gate of the MOS transistor PM3b are respectively connected to the latch in the clock power domain.

3. The digital-to-analog converter chip according to claim 2, characterized in that: The analog power domain includes a first AND gate unit, a first protection circuit and a first bias circuit, wherein the first protection circuit and the first bias circuit are respectively connected to the output end of the first AND gate unit; The clock power domain further includes an undervoltage lockout circuit, wherein the undervoltage lockout circuit is connected between a clock power ground voltage of the second linear regulator and an input of the first AND gate unit; Among them, after the second linear regulator is started, its clock power ground voltage passes through the undervoltage lockout circuit and the undervoltage lockout circuit outputs a control signal; the first AND gate unit starts and controls the first protection circuit and the first bias circuit after obtaining the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply.

4. The digital-to-analog converter chip according to claim 3, characterized in that: The first AND gate unit further includes a NOT gate unit and a delay unit, the NOT gate unit is connected in series to the output end of the first AND gate unit, the delay unit is connected in series to the output end of the NOT gate unit, and the NOT gate unit and the delay unit are both connected to the first bias circuit and the first protection circuit; The first AND gate unit outputs a first switch signal after acquiring the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply, the NOT gate unit outputs a second switch signal, and the delay unit outputs a third switch signal. The first switch signal, the second switch signal and the third switch signal are used to control the start-up of the first bias circuit and the first protection circuit.

5. The digital-to-analog converter chip according to claim 4, characterized in that: The first protection circuit includes a MOS transistor PM5, a MOS transistor NM2, a MOS transistor NM1, a first switch, a second switch, a third switch, a first capacitor and a first resistor; The source of the MOS transistor PM5 is connected to the drain of the MOS transistor PM1 and the gate of the MOS transistor PM5 respectively, and the gate of the MOS transistor PM5 is used to connect the control voltage; the drain of the MOS transistor NM2 is connected to the source of the MOS transistor PM5, and the gate of the MOS transistor NM2 is connected to the drain of the MOS transistor PM5; the drain of the MOS transistor NM1 is connected to the drain of the MOS transistor PM5 and the gate of the MOS transistor NM2 respectively, and the gate of the MOS transistor NM1 is used to connect the control voltage, and the source of the MOS transistor NM1 is connected to the negative power supply voltage of the analog power supply; The first capacitor is connected between the gate of the MOS transistor PM2 and the positive power supply voltage of the analog power supply, the common input end of the first switch and the first resistor connected in series is connected to the first capacitor, and the common output end is connected to the bias voltage; The second switch is connected in parallel with a structure in which the first switch and the first resistor are connected in series; one end of the third switch is connected to the input end of the second switch, and the other end is connected to the negative power supply voltage of the analog power supply; The first switch is used to open and close under the action of the first switch signal, the second switch is used to open and close under the action of the third switch signal, and the third switch is used to open and close under the action of the second switch signal.

6. The digital-to-analog converter chip according to claim 5, characterized in that: The first bias circuit includes a MOS transistor NM0, a second resistor, a MOS transistor NM9, a MOS transistor NM10, a MOS transistor NM6, a MOS transistor NM4a, a MOS transistor NM4b, a MOS transistor NM7, a MOS transistor PM6, a MOS transistor PM11, a MOS transistor PM0, a MOS transistor NM3a, a MOS transistor NM3b, a MOS transistor NM3c, a MOS transistor PM7a, a MOS transistor PM7b, a MOS transistor PM8a, a MOS transistor PM8b, a MOS transistor NM5a, a MOS transistor NM5b, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a second capacitor, a third resistor, a MOS transistor PM9, a MOS transistor PM10, and a MOS transistor NM8; The gate of the MOS tube NM0, the gate of the MOS tube NM9, the gate of the MOS tube NM10, the gate of the MOS tube NM6, the gate of the MOS tube NM4a, the gate of the MOS tube NM4b, and the gate of the MOS tube NM7 are connected to each other, and the source of the MOS tube NM0, the source of the MOS tube NM9, the source of the MOS tube NM10, the source of the MOS tube NM6, the source of the MOS tube NM4a, the source of the MOS tube NM4b, and the source of the MOS tube NM7 are all connected to the negative power supply voltage of the analog power supply; The drain of the MOS transistor NM0 is connected to the gate of the MOS transistor NM0, the second resistor is connected between the drain of the MOS transistor NM0 and the positive power supply voltage of the analog power supply, the drain of the MOS transistor PM6 is respectively connected to the gate of the MOS transistor NM6 and the drain of the MOS transistor NM9, the drain of the MOS transistor PM11 is connected to the source of the MOS transistor NM6, the gate of the MOS transistor PM11 is connected to the gate of the MOS transistor NM6, the source of the MOS transistor PM11 is connected to the positive power supply voltage of the analog power supply, the drain of the MOS transistor PM0 is respectively connected to the drain of the MOS transistor NM10 and the gate of the MOS transistor NM0, and the source of the MOS transistor PM0 is connected to the positive power supply voltage of the analog power supply; The gate of the MOS tube NM3a is connected to the low-noise regulated output voltage of the second linear regulator, the drain of the MOS tube NM3a is connected to the drain of the MOS tube NM3b, the source of the MOS tube NM3a is connected to the source of the MOS tube NM3b, the gate of the MOS tube NM3b is connected to the given voltage VBC, the source of the MOS tube NM3b and the source of the MOS tube NM3c are both connected to the drain of the MOS tube NM6, the gate of the MOS tube NM3c is connected to the drain of the MOS tube NM8, the drain of the MOS tube NM3c is connected to the drain of the MOS tube PM7b, and the drain of the MOS tube NM3b is connected to the drain of the MOS tube PM8a; The source of the MOS transistor PM8a and the source of the MOS transistor PM8b are both connected to the positive power supply voltage of the analog power supply. The gate of the MOS transistor PM8a is connected to the gate of the MOS transistor PM8b and then connected to the gates of the MOS transistors PM0 and PM9. The drain of the MOS transistor PM8a is also connected to the source of the MOS transistor PM7a. The drain of the MOS transistor PM8b is also connected to the source of the MOS transistor PM7b. The gates of the MOS transistors PM7a, PM7b and PM6 are connected to each other. The drain of the MOS transistor PM7a is connected to the drain of the MOS transistor NM5a, the drain of the MOS transistor PM7b is connected to the drain of the MOS transistor NM5b, the gate of the MOS transistor NM5a is respectively connected to the drain of the MOS transistor NM5a and the gate of the MOS transistor NM5b, the source of the MOS transistor NM5a and the source of the MOS transistor NM5b are both connected to the negative power supply voltage of the analog power supply, and the gate of the MOS transistor NM5a and the gate of the MOS transistor NM5b are both connected to the drain of the MOS transistor NM4a; The drain of the MOS transistor NM4b is connected to the drain of the MOS transistor NM5b, one end of the fourth switch is connected to the drain of the MOS transistor NM4b, and the other end is connected to the negative power supply voltage of the analog power supply, one end of the fifth switch is connected to the drain of the MOS transistor PM7b, and the other end is connected to the gate of the MOS transistor PM10, the sixth switch is connected between the other end of the fifth switch and the positive power supply voltage of the analog power supply, the series structure formed by the third resistor and the seventh switch is connected between the positive power supply voltage of the analog power supply and the gate of the MOS transistor PM10, one end of the second capacitor is connected to the other end of the fifth switch, and the other end is connected to the negative power supply voltage of the analog power supply; The source of the MOS transistor PM9 is connected to the positive power supply voltage of the analog power supply, the drain of the MOS transistor PM9 is connected to the source of the MOS transistor PM10 and the gate of the MOS transistor NM3c, the gate of the MOS transistor PM10 is connected to the source of the MOS transistor PM10, the drain of the MOS transistor PM10 is connected to the drain of the MOS transistor NM7 and the gate of the MOS transistor NM8, and the source of the MOS transistor NM8 is connected to the negative power supply voltage of the analog power supply; The gate of the MOS transistor PM10 is connected to the gate of the MOS transistor PM5 , and the gate of the MOS transistor NM7 is connected to the gate of the MOS transistor NM1 .

7. The digital-to-analog converter chip according to claim 6, characterized in that: The given voltage VBC is generated by a bandgap reference of the analog power domain, and a difference between the given voltage VBC and a negative power voltage of the analog power domain is equal to a standard operating voltage of a low voltage device.

8. The digital-to-analog converter chip according to claim 2, characterized in that: The analog power domain further includes a second protection circuit, which includes a PMOS tube M1, an NMOS tube m2 and an NMOS tube m1; The source of the PMOS tube M1 is connected to the source of the MOS tube PM3a, the gate of the PMOS tube M1 is connected to the positive power supply voltage and the control voltage of the analog power supply, the drain of the PMOS tube M1 is connected to the gate of the NMOS tube m2, the drain of the NMOS tube m2 is connected to the source of the PMOS tube M1, the source of the MOS tube M2 is connected to the negative power supply voltage of the analog power supply, the drain of the NMOS tube m1 is connected to the drain of the PMOS tube M1, the source of the NMOS tube m1 is connected to the negative power supply voltage of the analog power supply, and the gate of the NMOS tube m1 is connected to the control voltage.

9. The digital-to-analog converter chip according to claim 8, characterized in that: The analog power domain also includes a second bias circuit, which includes an NMOS tube m5, an NMOS tube m4, an NMOS tube m3, a PMOS tube M5, a PMOS tube M4, a fourth resistor, a first operational amplifier OTA2, a PMOS tube M2, a PMOS tube M3, an NMOS tube m6, a second operational amplifier OTA1 and a fifth resistor; The gate of the NMOS tube m5, the gate of the NMOS tube m4, the gate of the NMOS tube m3, and the gate of the NMOS tube m1 are connected to each other, and the source of the NMOS tube m5, the source of the NMOS tube m4, and the source of the NMOS tube m3 are connected to the negative power supply voltage of the analog power supply; The drain of the NMOS tube m5 is connected to the drain of the PMOS tube M5, the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M5, the gate of the PMOS tube M5 is respectively connected to the gate of the PMOS tube M1 and the positive power supply voltage of the analog power supply, the source of the PMOS tube M5 is connected to the drain of the PMOS tube M4, the source of the PMOS tube M4 is connected to the positive power supply voltage of the analog power supply, the drain of the PMOS tube M4 is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the NMOS tube m4; The gate of the PMOS tube M4 is connected to the output end of the first operational amplifier OTA2, the positive input end of the first operational amplifier OTA2 is connected to the other end of the fourth resistor, and the negative input end is connected to the negative voltage source of the clock power supply; The drain of the NMOS tube m3 is connected to the gate of the NMOS tube m3 and the drain of the PMOS tube M2 respectively, the source of the PMOS tube M2 and the source of the PMOS tube M3 are both connected to the positive power supply voltage of the analog power supply, the gate of the PMOS tube M2 and the gate of the PMOS tube M3 are connected to each other and then connected to the drain of the PMOS tube M3, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube m6, the source of the MOS tube M6 is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the negative power supply voltage of the analog power supply, the output end of the second operational amplifier OTA1 is connected to the gate of the NMOS tube m6, and the negative input end of the second operational amplifier OTA1 is connected to one end of the fifth resistor.

10. The digital-to-analog converter chip according to claim 9, characterized in that: A positive input terminal of the second operational amplifier OTA1 is connected to a reference voltage generated by an on-chip bandgap reference.

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