Multi-scattering-point target echo simulation implementation method and device based on multi-resource cooperation

Abstract

The invention discloses a multi-scattering-point target echo simulation implementation method and device based on multi-resource collaboration, and the method comprises the steps: calculating an echo delay value according to the distance between a scattering point and a radar, and determining a first delay, a second delay and a third delay; delaying the baseband signal by a first delay through an FPGA off-chip DDR (Double Data Rate); the first delay signal is delayed by a second delay through an Ultra RAM in an FPGA chip; the second delay signal is delayed by third delay through a Block RAM in an FPGA chip; the method comprises the following steps of: moving each multi-path scattering point echo signal in a clock period to ensure that the delay precision is smaller than that of an FPGA (Field Programmable Gate Array) in a working clock period; and combining the multiple paths of scattering point echo signals after accurate time delay into one path of multi-scattering point target echo analog signal, and carrying out interpolation, up-conversion and DAC (Digital-to-Analog Converter). The distance distribution range of scattering point targets is increased, and the utilization rate of resources is improved.

Description

Technical Field

[0001] The present invention belongs to the field of radar simulation, and particularly relates to a method and device for simulating the echo of a multi-scattering point target based on multi-resource collaboration. Background Art

[0002] With the continuous improvement of the technological level, various new types of radars have emerged. In the process of developing new radars, it is essential to test the radar performance. Initially, the radar performance was tested in the outfield environment. However, constructing an outfield test environment requires a large amount of resources, and the test environment is not flexible enough. With the continuous development of radar technology and simulation technology, the radar echo simulation technology has emerged. The emergence of the radar echo simulation technology enables the performance of new radars to be tested in the in-field environment, which helps to save the test cost and improve the test efficiency.

[0003] With the upgrade and iteration of radar equipment, the range resolution of the radar is less than the target size. At this time, the target can no longer be considered a point target. Theory and practice show that when the target size is less than the radar range resolution, the echo of the target is synthesized by the scattered echoes of the scattering sources at some local positions on the target. These local scattering sources are usually called multi-scattering centers, and these multi-scattering centers can be approximately treated as point targets.

[0004] In the previous methods for simulating the echo of a multi-scattering point target, for the simulation of the scattering point distance, multiple identical storage spaces are set using the Block RAM (Block Random Access Memory) resources inside the FPGA (Field Programmable Gate Array). Each storage space stores a copy of the radar transmit signal. The simulation of the scattering point distance is achieved by controlling the reading time of each storage space. Finally, the multiple paths of data are merged into one path of data for output. However, this method has the following two disadvantages:

[0005] 1. The scattering point distance distribution range is small. Due to the limited Block RAM resources inside the FPGA, a large storage space cannot be formed, resulting in a small scattering point distance distribution range that can be achieved.

[0006] 2. Excessive use of Block RAM resources. If the delay values of two scattering point targets are the same, two identical storage spaces are still used to achieve the same delay value, which will cause waste of Block RAM resources.

[0007] Another solution is to use the structure of DDR + multi - stage registers to implement the echo simulation of multi - scatter - point targets. Specifically, the radar transmit signal is stored in the DDR, and the first delay of the multi - scatter - points is achieved by controlling the reading time of the DDR. The delay value is determined by the minimum initial distance of the multi - scatter - points. The multi - stage registers achieve the second delay of the multi - scatter - points, and the delay value is determined by the dynamic distance of each scatter - point. If the dynamic distances of the scatter - points are different, different levels of register groups are selected. Finally, the multiple paths of data are merged into one path of data for output. However, this solution requires multiple - stage register groups to implement the second delay. One - stage register can only achieve a delay of 1 clock cycle. If multiple multi - scatter - point target echoes need to be generated, the number of levels of the multi - stage register groups needs to be increased, which will correspondingly increase the control logic of the register groups, resulting in an increase in the complexity of the overall structure and making it difficult to implement.

[0008] Therefore, there is an urgent need for a multi - scatter - point target echo simulation scheme that can improve the utilization rate of resources and increase the distance distribution range of scatter - point targets. Summary of the Invention

[0009] To solve the above problems existing in the prior art, the present invention provides a method and device for implementing multi - scatter - point target echo simulation based on multi - resource collaboration.

[0010] The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0011] A method for implementing multi - scatter - point target echo simulation based on multi - resource collaboration includes:

[0012] Calculating the echo delay value according to the distances between the scatter - points of the multi - scatter - point target from the radar, and determining the first delay, the second delay, and the third delay according to the echo delay value; wherein, the first delay is the delay value of the scatter - point closest to the radar among all multi - scatter - point targets, the second delay is the delay value between scatter - point targets, and the third delay is the delay value between the scatter - points of the multi - scatter - point target itself;

[0013] Implementing the first - delay of the baseband signal through the off - chip DDR of the FPGA to obtain the first delayed signal;

[0014] Implementing the second - delay of the first delayed signal through the cascaded FIFO and multiplexer implemented by the on - chip Ultra RAM of the FPGA to obtain the second delayed signal;

[0015] Implementing the third - delay of the second delayed signal through the parallel FIFO implemented by the on - chip Block RAM of the FPGA to obtain the third delayed signal; the third delayed signal includes multi - path scatter - point echo signals;

[0016] By shifting the echo signal of each scattering point within one clock cycle to make its delay accuracy less than one working clock cycle of the FPGA, multi-path echo signals of scattering points after precise delay are obtained;

[0017] The multi-path echo signals of scattering points after precise delay are merged, and interpolation, up-conversion and DAC are performed on the multi-scattering point target echo simulation signal obtained after merging.

[0018] Optionally, the method further includes:

[0019] When merging the multi-path echo signals of scattering points after precise delay, it is judged whether data overflow occurs; if data overflow occurs, data saturation processing is performed to ensure the continuation of merging.

[0020] Optionally, the calculating the echo delay value according to the distance between the scattering points of the multi-scattering point target and the radar includes:

[0021] Set m multi-scattering point targets, and each multi-scattering point target contains n scattering points; m>1, n>1;

[0022] According to the distance between each scattering point of each multi-scattering point target and the radar, the echo delay value of this scattering point is calculated;

[0023] The multi-scattering point targets are sorted in ascending order of the distance from the radar, and the scattering points of each multi-scattering point target are sorted in ascending order of the distance from the radar. According to the sorting result, the calculated m×n echo delay values are constructed into an echo delay value matrix.

[0024] Optionally, in the echo delay value matrix, the element in the i-th row (i = [1, 2,..., m]) and the j-th column (j = [1, 2,..., n]) is the echo delay value of the j-th scattering point (i, j) of the i-th multi-scattering point target;

[0025] The determining the first delay, the second delay and the third delay according to the echo delay value includes:

[0026] Taking the element in the first row and the first column of the echo delay value matrix t delay as the first delay of the scattering point (i, j); 11 As the first delay of the scattering point (i, j);

[0027] For the elements in the first column of the echo delay value matrix t delay calculate the difference between each element t i1 in this column and the first element t 11 of this column to obtain the second delay Δi of the scattering point (i, j);

[0028] Calculate the echo delay value matrix t delayEach element t in ij is subtracted from the element t in the first row and first column 11 to obtain the sum of the second delay Δi and the third delay δ of the scattering point (i, j). ij ;

[0029] Subtract the second delay Δi of the scattering point (i, j) from the sum of the second delay Δi and the third delay δ of the scattering point (i, j) to obtain the third delay δ of the scattering point (i, j). ij ij 。

[0030] Optionally, the multiplexer includes m - 1; in the cascaded FIFO, the output of each stage of the FIFO is connected to each multiplexer;

[0031] The cascaded FIFO and multiplexer implemented by the on - chip Ultra RAM of the FPGA to delay the first delay signal to obtain the second delay signal includes:

[0032] Input the first delay signal into the cascaded FIFO, select FIFOs of different stages through each multiplexer to delay the first delay signal by different magnitudes of the second delay, and output the second delay signals of m - 1 multi - scattering - point targets through m - 1 multiplexers respectively.

[0033] Optionally, there are multiple parallel FIFOs, and multiple parallel FIFOs and multiple multiplexers correspond one by one; among them, the input of each parallel FIFO is the second delay signal output by its corresponding multiplexer;

[0034] The parallel FIFO implemented by the on - chip Block RAM of the FPGA to delay the second delay signal to obtain the third delay signal includes:

[0035] Input the second delay signal output by the multiplexer into each FIFO in the corresponding parallel FIFO, so as to delay the second delay signal by the third delay through each FIFO in the parallel FIFO, and output the multi - path scattering - point echo signals through each FIFO.

[0036] Optionally, the number of FIFO stages and the FIFO depth of the cascaded FIFO are calculated and designed according to the number of multi - scattering - point targets and the distance distribution range between multi - scattering - point targets by using the following formula:

[0037]

[0038] ​Wherein, x is the number of FIFO stages, l is the FIFO depth, L is the total depth of cascaded FIFOs, m is the number of multi-scattering point targets, d is the maximum distance between multi-scattering point targets, f clk is the working clock frequency of the FPGA, c is the speed of light, n is a natural number, and n is related to the FIFO bit width and the resources of the Ultra RAM used.

[0039] Optionally, the number of FIFOs of the parallel FIFOs is the number of scattering points included in a single multi-scattering point target, the FIFO depth of the parallel FIFOs is the maximum third delay between the scattering points of the scattering point target, and the FIFO depth is a power of 2.

[0040] The present invention also provides a multi-scattering point target echo simulation implementation device based on multi-resource collaboration, including:

[0041] A delay value calculation module, configured to calculate an echo delay value according to the distance between the scattering points of the multi-scattering point target from the radar, and determine a first delay, a second delay, and a third delay according to the echo delay value; wherein, the first delay is the delay value of the scattering point closest to the radar of the multi-scattering point target, the second delay is the delay value between the scattering point targets, and the third delay is the delay value between the scattering points of the multi-scattering point target itself;

[0042] A DDR delay module, configured to delay the baseband signal by the first delay through the off-chip DDR of the FPGA to obtain a first delayed signal;

[0043] A cascaded FIFO module, configured to delay the first delayed signal by the second delay through a cascaded FIFO and a multiplexer implemented by the on-chip Ultra RAM of the FPGA to obtain a second delayed signal;

[0044] A parallel FIFO module, configured to delay the second delayed signal by the third delay through a parallel FIFO implemented by the on-chip Block RAM of the FPGA to obtain a third delayed signal; the third delayed signal includes multi-path scattering point echo signals;

[0045] An accurate delay module, configured to move each path of scattering point echo signal within one clock cycle so that its delay accuracy is less than one working clock cycle of the FPGA to obtain an accurately delayed multi-path scattering point echo signal;

[0046] A data accumulation and signal playback module, configured to merge the accurately delayed multi-path scattering point echo signals, and perform interpolation, up-conversion, and DAC on the multi-scattering point target echo simulation signal obtained after merging.

[0047] Optionally, the data accumulation and signal playback module is further configured to: when combining the multi-path scattered point echo signals after precise delay, determine whether a data overflow occurs; if a data overflow occurs, ensure the continuation of the combination by performing data saturation processing.

[0048] The method for simulating the echo of a multi-scattered point target based on multi-resource collaboration provided by the present invention decomposes the delay value of each scattered point into multiple different types of delay values according to the position of the scattered point, and designs different delay structures based on different storage resources to implement different types of delay values. It can improve the utilization rate of resources and increase the distance distribution range of the scattered point target.

[0049] The following will further elaborate on the present invention in conjunction with the accompanying drawings. Description of the Drawings

[0050] Figure 1 is a schematic flowchart of a method for simulating the echo of a multi-scattered point target based on multi-resource collaboration provided by an embodiment of the present invention;

[0051] Figure 2 is a schematic diagram of implementing the second delay through the on-chip Ultra RAM of the FPGA in the method of the present invention;

[0052] Figure 3 is a schematic diagram of implementing the third delay through the on-chip Block RAM of the FPGA in the method of the present invention;

[0053] Figure 4 is a schematic diagram of achieving precise delay by moving the scattered point echo signal within one clock cycle in the method of the present invention;

[0054] Figure 5 is a time-domain diagram of implementing the echo of 4 multi-scattered point targets using the method of the present invention;

[0055] Figure 6 is the pulse compression result of implementing the echo of 4 multi-scattered point targets using the method of the present invention;

[0056] Figure 7 is a partial enlarged view of one pulse compression result of implementing the echo of 4 multi-scattered point targets using the method of the present invention;

[0057] Figure 8 is another partial enlarged view of the pulse compression result of implementing the echo of 4 multi-scattered point targets using the method of the present invention.

[0058] Figure 9 is a schematic structural diagram of a device for simulating the echo of a multi-scattered point target based on multi-resource collaboration provided by an embodiment of the present invention. Detailed Embodiment

[0059] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0060] In order to improve the utilization rate of resources and increase the distance distribution range of scattered point targets, an echo simulation implementation method for multi-scattered point targets based on multi-resource collaboration is provided in an embodiment of the present invention. As Figure 1 shown, the method includes the following steps:

[0061] S10. Calculate the echo delay value according to the distance between the scattered points of the multi-scattered point target and the radar, and determine the first delay, the second delay, and the third delay according to the echo delay value; wherein, the first delay is the delay value of the scattered point closest to the radar among all multi-scattered point targets, the second delay is the delay value between the scattered point targets, and the third delay is the delay value between the scattered points of the multi-scattered point target itself.

[0062] Among them, calculating the echo delay value according to the distance between the scattered points of the multi-scattered point target and the radar includes:

[0063] (1) Set m scattered point targets, and each scattered point target includes n scattered points; m>1, n>1.

[0064] Specifically, different scattered points are set for each scattered point target by setting the distance of the scattered points of each scattered point target on the upper computer interface, and each scattered point target can set n scattered points.

[0065] (2) Calculate the echo delay value of the scattered point according to the distance between each scattered point of each multi-scattered point target and the radar.

[0066] (3) Sort the scattered point targets in ascending order of the distance from the radar, and sort the scattered points of each scattered point target in ascending order of the distance from the radar. According to the sorting result, construct the calculated m×n echo delay values into an echo delay value matrix. In this echo delay value matrix, the element in the i-th row (i = [1, 2,..., m]) and the j-th column (j = [1, 2,..., n]) is the echo delay value of the j-th scattered point of the i-th scattered point target.

[0067] For example, sort the scattered point targets in ascending order of the distance from the radar, and sort the scattered points of each scattered point target in ascending order of the distance from the radar, and obtain:

[0068]

[0069] Among them, the elements in the first row are the distance parameters of the first scatterer target, the elements in the second row are the distance parameters of the second scatterer target, the elements in the m-th row are the distance parameters of the m-th scatterer target, and the elements in different columns in the same row are the distances R of different scatterers in a scatterer target.

[0070] Then, calculate the echo delay value of each scatterer:

[0071]

[0072] Among them, f clk is the working clock frequency of the FPGA, c is the speed of light, t delay is the echo delay value matrix, t is the echo delay value, and this echo delay value is in units of FPGA clock cycles.

[0073] Then, determine the first delay, the second delay, and the third delay according to the echo delay value, including:

[0074] (1) Take the element t delay in the first row and the first column of the echo delay value matrix t 11 as the first delay of the scatterer (i, j).

[0075] (2) For the elements in the first column of the echo delay value matrix t delay , calculate the difference between each element t i1 in this column and the first element t 11 in this column to obtain the second delay Δi of the scatterer (i, j).

[0076] Here, it is equivalent to decomposing the echo delay value matrix t delay into the following form:

[0077]

[0078] Among them, Δ1 = 0, Δ i = t i1 - t (i-1)1 , i = 2, 3,..., m, and this Δ represents the delay difference between the scatterers closest to the radar in adjacent two rows. It can be understood that if the delay value of the scatterer closest to the radar in each target is used to represent the delay value of the target, then Δ can also represent the delay value between adjacent targets.

[0079] (3) Calculate the difference between each element t delay in the echo delay value matrix t ij and the element t 11 in the first row and the first column to obtain the sum of the second delay Δi and the third delay δ ij of the scatterer (i, j).

[0080] Here, it is equivalent to decomposing the echo delay value matrix t delay into the following form:

[0081]

[0082] where, it is numerically equal to the sum of the second delay and the third delay of the scattering point.

[0083] (4) Subtract the second delay Δi of the scattering point (i, j) from the sum of the second delay Δi and the third delay δ ij of the scattering point (i, j) to obtain the third delay δ of the scattering point (i, j). ij .

[0084] Thus, it is equivalent to decomposing the echo delay value matrix t delay into the following form:

[0085]

[0086] where, δ i0 = 0, δ ij = t ij -(t 11 +Δ i ), i = 1, 2, … m, j = 1, 2, …, n. This δ represents the delay difference between each scattering point in a row and the scattering point closest to the radar in that row.

[0087] Thus, the delay value of each scattering point can be decomposed into the sum of three parts, namely: the first delay value t 11 , the second delay value Δ m , and the third delay value δ mn . The variation ranges of these three parts of delay values gradually decrease. Therefore, a large-capacity DDR outside the FPGA is selected to implement t 11 , a medium-capacity Ultra RAM inside the FPGA is selected to implement Δ m , and a small-capacity Block RAM inside the FPGA is selected to implement δ mn . For the specific implementation method, please refer to the subsequent steps.

[0088] S20. Through the DDR outside the FPGA, delay the baseband signal by the first delay to obtain the first delayed signal.

[0089] Specifically, a radar signal is collected by a signal acquisition module, and the radar signal is subjected to ADC and digital down-conversion to obtain a baseband signal. Then, after detecting the input of the baseband signal, the baseband signal is written into the off-chip DDR of the FPGA. After delaying the baseband signal by a certain time according to the first delay, the baseband signal is read out from the DDR, thereby realizing the delay of the first delay for the baseband signal.

[0090] S30. Through the cascaded FIFO and multiplexer implemented by the on-chip Ultra RAM of the FPGA, the first delay signal is delayed by a second delay to obtain a second delay signal.

[0091] Specifically, the cascaded FIFO can use the on-chip Ultra RAM resources of the FPGA to form a medium-capacity storage space to realize the delay value Δ between scatter point targets. m . See Figure 2 , the cascaded FIFO is composed of multiple FIFOs with the same depth in cascade, and the multiplexer includes m - 1; in the cascaded FIFO, the output of each stage of FIFO is connected to each multiplexer; different multiplexers output the second delay signals of different multi-scatter point targets. Thus, by setting multiple data selectors together with the first delay signal input to the cascaded FIFO, the echoes of m scatter point targets are simulated.

[0092] In this step, through the cascaded FIFO and multiplexer implemented by the on-chip Ultra RAM of the FPGA, the first delay signal is delayed by a second delay to obtain a second delay signal, including:

[0093] The first delay signal is input into the cascaded FIFO, and the first delay signal is delayed by different sizes of the second delay by selecting different stages of FIFO through each multiplexer, and the second delay signals of m - 1 multi-scatter point targets are respectively output through m - 1 multiplexers.

[0094] It can be seen that in this step, for the second delay of the echo of the multi-scatter point target with a long distance, it is realized on the basis of the second delay of the echo of the multi-scatter point target with a short distance, which effectively improves the resource utilization rate.

[0095] In the embodiment of the present invention, the number of FIFO stages and the depth of the FIFO of the cascaded FIFO are calculated and designed according to the number of multi-scatter point targets and the distance distribution range between the multi-scatter point targets by using the following formula:

[0096]

[0097] Wherein, x is the number of FIFO stages, l is the FIFO depth, L is the total depth of cascaded FIFOs, m is the number of multi-scattering point targets, d is the maximum distance between multi-scattering point targets, f clk is the working clock frequency of the FPGA, c is the speed of light, n is a natural number, and n is related to the FIFO bit width and the resources of the Ultra RAM used.

[0098] For example, assuming that m scattered point target echoes need to be generated, and the distance distribution range between the nearest scattered point target and the farthest scattered point target is 0 to d meters, and the cascaded FIFO module is composed of x FIFOs in cascade, then the total depth after FIFO cascade is at least:

[0099]

[0100] In the above formula, the reason for subtracting m - 2 in the denominator is that in the present invention, the cascaded FIFO module only needs to generate the first scattered point echo signal of the remaining targets except the first target, that is, the cascaded FIFO module actually only generates m - 1 signals. To generate m - 1 signals, (m - 1) - 1 FIFOs plus 1 FIFO with a depth that can satisfy the distance distribution range of 0 to d meters can be cascaded.

[0101] Let m = 4, d = 5000m, c = 3×10 8 m / s, fclk = 300MHz, then the above formula can be simplified to:

[0102]

[0103] The depth of each FIFO is:

[0104]

[0105] When implemented on the FPGA, the FIFO bit width is set to 128bit, and the Ultra RAM resources are used to implement the FIFO. The capacity of each Ultra RAM is 288kb. Then the number of Ultra RAMs required is:

[0106]

[0107] The above formula is a monotonically decreasing function. When x → ∞, y obtains the minimum value of 4.3403. Therefore, 5 pieces of 288kb Ultra RAMs need to be used. When y = 5, x = 15.1579. Therefore, at least 16 FIFOs are required. At the same time, the depth of the FIFO must be a power of 2. Substituting l = 2 n , n = 0, 1, 2,... into formula (3), we can get:

[0108]

[0109] According to Equation (5), the value range of n is n ≤ 9.4804. The smaller the value of n, the larger the number x of FIFOs, and the more resources are required for the read / write control logic of the FIFOs. Therefore, n = 9 is sufficient. At this time, the depth l of the FIFO is 512, and the number x of FIFOs is 21.5312. According to Equation (2), the depth after cascading x - 2 FIFOs should be greater than or equal to 10000. Therefore, the final number x of FIFOs is 22, and the depth l of the FIFO is 512.

[0110] S40. For the parallel FIFO implemented by the on-chip Block RAM of the FPGA, the second delay signal is used to implement the third delay, and the third delay signal is obtained; the third delay signal includes multiplex scattered point echo signals.

[0111] Specifically, the parallel FIFO module uses the Block RAM resources inside the FPGA to form multiple FIFOs with smaller depths to implement the delay value δ between the scattered points within the target. mn This is because the delay values between the scattered points in the scattered point target are relatively small. Therefore, a FIFO with a smaller depth can be set for each scattered point to implement the delay value between the scattered points.

[0112] See Figure 3 The parallel FIFO is composed of multiple FIFOs with the same depth, and there are multiple parallel FIFOs, which correspond one-to-one with multiple multiplexers; among them, the input of each parallel FIFO is the second delay signal output by its corresponding multiplexer.

[0113] Correspondingly, for the parallel FIFO implemented by the on-chip Block RAM of the FPGA, the second delay signal is used to implement the third delay, and the third delay signal is obtained, including:

[0114] The second delay signal output by the multiplexer is input to each FIFO in the corresponding parallel FIFO, so that each FIFO in the parallel FIFO implements the third delay of the second delay signal, and the multiplex scattered point echo signals are output through the respective FIFOs.

[0115] In the embodiment of the present invention, the number of FIFOs in the parallel FIFO is the number of scattered points included in a single multi-scattered point target, the depth of the FIFO in the parallel FIFO is the maximum third delay between the scattered points of the scattered point target, and the FIFO depth is a power of 2.

[0116] S50. The multiplex scattered point echo signals after precise delay are merged, and interpolation, up-conversion, and DAC are performed on the multi-scattered point target echo analog signal obtained after merging.

[0117] It can be understood that the delay resolution of the multipath scattered point echo signals output by the parallel FIFO is one clock cycle. To improve the delay resolution, it is necessary to move the data within one clock cycle longitudinally, so as to accurately reflect the delay of the fractional part of the echo delay value in the simulated echo signal. If the working clock frequency of the FPGA is fclk and the number of parallel processing channels of the FPGA is N, then the data sampling period is Tclk / N, and the delay resolution is Tclk / N. When specifically moving, within one clock cycle, the delay of each multipath scattered point echo signal can be p×Tclk / 4, where p is the number of movements, and the maximum value of p is N - 1.

[0118] Specifically, as Figure 4 , when inputting 4-channel parallel data a, b, c, d to the FPGA, let a, b, c, d move once in the longitudinal direction (time dimension), and take d_d, a, b, c as the output, then a delay of 1×Tclk / 4 can be achieved, where d_d is the data of d after being registered for one beat. If let a, b, c, d move twice in the longitudinal direction and take c_d, d_d, a, b as the output, then a delay of 2×Tclk / 4 can be achieved, where c_d is the data of c after being registered for one beat.

[0119] S60. Merge the multipath scattered point echo signals after precise delay, and perform interpolation, up-conversion, and DAC on the multi-scattered point target echo simulation signal obtained after merging.

[0120] Among them, when merging the multipath scattered point echo signals after precise delay, it can be judged whether a data overflow phenomenon occurs; if a data overflow phenomenon occurs, ensure the continuation of the merge by performing data saturation processing. If no data overflow phenomenon occurs, merge the multipath scattered point echo signals after precise delay into one multi-scattered point target echo simulation signal according to the conventional merge process.

[0121] The embodiment of the present invention adopts a multi-stage delay structure to simulate the multi-scattered point target echo. According to the position of the scattered points, the delay value of each scattered point is decomposed into multiple different types of delay values, and storage resources with different capacities are used to implement the delay value, avoiding the single use of the limited Block RAM storage resources inside the FPGA chip, and increasing the distance distribution range of the multi-scattered point target. Moreover, the embodiment of the present invention realizes the same type of delay value by repeatedly using a section of storage space, avoiding setting multiple identical storage spaces, and improving the resource utilization rate of the system. In addition, the number of scattered point targets and the number of scattered points included in each scattered point target can be set in real time by the host computer.

[0122] In the embodiments of the present invention, a design method of a cascaded FIFO for generating echoes of multiple multi-scattering point targets is also proposed. This design method can calculate the optimal cascaded FIFO scheme according to the number of multi-scattering point targets and the distance distribution range between multi-scattering point targets, and has the advantages of strong flexibility and good versatility.

[0123] The following uses simulation experiments to further illustrate the embodiments of the present invention.

[0124] I. Experimental conditions

[0125] The input excitation signal used in the experiment is a linear frequency modulation signal with a bandwidth of 100 MHz and a pulse width of 10 us. The target simulation parameters set in the experiment are: the initial distance of multi-scattering point target 1 is 16700 m, the initial distance of multi-scattering point target 2 is 17500 m, the initial distance of multi-scattering point target 3 is 18300 m, the initial distance of multi-scattering point target 4 is 19100 m, and the initial distance interval of each scattering point is 20 m.

[0126] Figure 5 is the time-domain diagram of the echoes of 4 multi-scattering point targets realized by the method of the present invention. Among them, the yellow pulse signal is the reference signal (input excitation signal), and the green pulse signal is the echo signal of the multi-scattering point target. From Figure 5 it can be seen that the delay of the echo signal relative to the reference signal is 111.88 us, and the distance of the target is 111.88×10 6 ×3×10 8 / 2 = 16712 m, which is consistent with the set parameters (within the error range).

[0127] The Figure 5 echo signal data of the multi-scattering point target is imported into Matlab for pulse compression processing. Figure 6 is the pulse compression result of the echo of the multi-scattering point target. Figure 6 In Figure 6 the left main lobe is the pulse compression result of the reference signal, and the multiple main lobes on the right are the pulse compression results of the echoes of the multi-scattering point targets. From Figure 6 it can be seen that the distance of multi-scattering point target 1 is (48531.2 - 15106.6) / 2 = 16712.3 m, which is consistent with the set parameters.

[0128] Figure 7 and Figure 8 are Figure 6 partial enlarged views. Figure 7 is the pulse compression result of the echoes of multi-scattering point targets 1 to 4. From Figure 7It can be seen that the distance interval between target 2 and target 1 is (50131.2 - 48531.2) / 2 = 800 m, the distance interval between target 3 and target 2 is (51731.2 - 50131.2) / 2 = 800 m, and the distance interval between target 4 and target 3 is (53331.2 - 51731.2) / 2 = 800 m, which is consistent with the set parameters. Figure 8 is the echo pulse compression result of multi-scattering point target 1. It can be seen from the figure that the distance interval between scattering point 2 and scattering point 1 is (48571.2 - 48531.2) / 2 = 20 m, the distance interval between scattering point 3 and scattering point 2 is (48611.2 - 48571.2) / 2 = 20 m, the distance interval between scattering point 4 and scattering point 3 is (48651.2 - 48611.2) / 2 = 20 m, the distance interval between scattering point 5 and scattering point 4 is (48691.2 - 48651.2) / 2 = 20 m, the distance interval between scattering point 6 and scattering point 5 is (48731.2 - 48691.2) / 2 = 20 m, the distance interval between scattering point 7 and scattering point 6 is (48771.2 - 48731.2) / 2 = 20 m, and the distance interval between scattering point 8 and scattering point 7 is (48811.2 - 48771.2) / 2 = 20 m, which is consistent with the set parameters.

[0129] The method provided by the embodiments of the present invention can be applied to an electronic device. Specifically, the electronic device can be: a desktop computer, a portable computer, a smart mobile terminal, a server, etc. There is no limitation here. Any electronic device that can implement the present invention belongs to the protection scope of the present invention.

[0130] Based on the same inventive concept, the embodiments of the present invention also provide a multi-scattering point target echo simulation implementation device based on multi-resource collaboration. See Figure 9 , including:

[0131] A delay value calculation module, configured to calculate an echo delay value according to the distance between the scattering points of the multi-scattering point target from the radar, and determine a first delay, a second delay, and a third delay according to the echo delay value; wherein, the first delay is the delay value of the scattering point of the multi-scattering point target closest to the radar, the second delay is the delay value between the scattering point targets, and the third delay is the delay value between the scattering points of the multi-scattering point target itself;

[0132] A DDR delay module, configured to delay the baseband signal by the first delay through off-chip DDR of the FPGA to obtain a first delayed signal;

[0133] A cascaded FIFO module, configured to delay the first delayed signal by the second delay through a cascaded FIFO and a multiplexer implemented by on-chip Ultra RAM of the FPGA to obtain a second delayed signal;

[0134] Parallel FIFO modules are used to implement a parallel FIFO through the on-chip Block RAM of the FPGA, delay the second delay signal to achieve a third delay, and obtain a third delay signal; the third delay signal includes multi-path scattered point echo signals;

[0135] An accurate delay module is used to move each path of scattered point echo signals within one clock cycle, so that its delay accuracy is less than one working clock cycle of the FPGA, and obtain multi-path scattered point echo signals after accurate delay;

[0136] A data accumulation and signal playback module is used to merge the multi-path scattered point echo signals after accurate delay, and perform interpolation, up-conversion, and DAC on the multi-scattered point target echo analog signal obtained after merging.

[0137] Optionally, the data accumulation and signal playback module is further used to: when merging the multi-path scattered point echo signals after accurate delay, determine whether a data overflow occurs; if a data overflow occurs, ensure the continuation of the merge by performing data saturation processing.

[0138] Optionally, the delay value calculation module calculates the echo delay value according to the distance between the scattered points of the multi-scattered point target from the radar, including:

[0139] Set m multi-scattered point targets, each multi-scattered point target contains n scattered points; m>1, n>1;

[0140] According to the distance between each scattered point of each multi-scattered point target from the radar, calculate the echo delay value of this scattered point;

[0141] Sort the scattered point targets in ascending order of the distance from the radar, and sort the scattered points of each scattered point target in ascending order of the distance from the radar. According to the sorting results, construct the calculated m×n echo delay values into an echo delay value matrix.

[0142] In the echo delay value matrix, the element in the i=[1,2,...m]th row and the j=[1,2,...n]th column is the echo delay value of the jth scattered point of the ith scattered point target;

[0143] Optionally, the delay value calculation module determines the first delay, the second delay, and the third delay according to the echo delay value, including:

[0144] Take the element t delay in the first row and the first column of the echo delay value matrix t 11 as the first delay of the scattered point (i,j);

[0145] For the echo delay value matrix t delayFor the elements in the first column, calculate each element t in this column of elements i1 and the first element t of this column 11 to obtain the second delay Δi of the scattering point (i, j);

[0146] Calculate each element t in the echo delay value matrix t delay to obtain the difference between the sum of the second delay Δi and the third delay δ of the scattering point (i, j) and the first element t in the first row and first column ij of the matrix; 11 ij ;

[0147] Subtract the second delay Δi of the scattering point (i, j) from the sum of the second delay Δi and the third delay δ of the scattering point (i, j) to obtain the third delay δ of the scattering point (i, j). ij ij .

[0148] Optionally, the multiplexer includes m - 1; in the cascaded FIFO, the output of each stage of FIFO is connected to each multiplexer; the cascaded FIFO module is specifically configured to:

[0149] Input the first delay signal into the cascaded FIFO, and select FIFOs with different numbers of stages through each multiplexer to delay the first delay signal by different magnitudes of second delays, and output the second delay signals of m - 1 multi-scattering point targets through m - 1 multiplexers respectively.

[0150] Optionally, there are multiple parallel FIFOs, and multiple parallel FIFOs correspond to multiple multiplexers one by one; wherein, the input of each parallel FIFO is the second delay signal output by its corresponding multiplexer; the parallel FIFO module is specifically configured to:

[0151] Input the second delay signal output by the multiplexer into each FIFO in the corresponding parallel FIFO, so as to delay the second delay signal by the third delay through each FIFO in the parallel FIFO, and output multi-path scattering point echo signals through each FIFO.

[0152] Optionally, the number of FIFO stages and the FIFO depth of the cascaded FIFO are calculated and designed according to the number of multi-scattering point targets and the distance distribution range between multi-scattering point targets by using the following formula:

[0153]

[0154] where x is the number of FIFO stages, l is the FIFO depth, L is the total depth of the cascaded FIFO, m is the number of multi-scattering point targets, d is the maximum distance between multi-scattering point targets, f​​clk is the operating clock frequency of the FPGA, c is the speed of light, n is a natural number, and n is related to the FIFO bit width and the resources of the Ultra RAM used.

[0155] Optionally, the number of FIFOs of the parallel FIFOs is the number of scatter points included in a single multi-scatter point target, the FIFO depth of the parallel FIFOs is the maximum third delay between the scatter points of the scatter point target, and the FIFO depth is a power of 2.

[0156] In addition, the device further includes a signal acquisition module for acquiring radar signals, performing ADC and digital down-conversion on the radar signals, and obtaining baseband signals.

[0157] It should be noted that for the device / embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment.

[0158] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are only examples of devices and methods consistent with some aspects of the present invention.

[0159] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0160] Although the present invention has been described in connection with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "including" does not exclude other components or steps, the term "one" or "a" does not exclude a plurality of cases, and the meaning of "a plurality" is two or more unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0161] It should be noted that the devices in the embodiments of the present invention are respectively devices applying the above-mentioned method for simulating the echo of a multi-scattering point target. Therefore, all embodiments of the above-mentioned method for simulating the echo of a multi-scattering point target are applicable to this device, and all can achieve the same or similar beneficial effects.

[0162] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices (equipment), or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects, and here they are all collectively referred to as "modules" or "systems". Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. The computer program is stored / distributed in a suitable medium, provided together with other hardware or as part of the hardware, and can also be in other distribution forms, such as through the Internet or other wired or wireless telecommunication systems.

[0163] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (equipment), and computer program products of the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to generate a machine, so that the instructions executed by the processors of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0164] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the functions in Figure 1 one process or multiple processes and / or blocksFigure 1 Steps of functions specified in one or more boxes.

[0166] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for realizing the echo simulation of multi-scattering point targets based on multi-resource collaboration, characterized in that, Including: Calculating an echo delay value according to the distance between the scatter points of a multi-scatter point target and the radar, and determining a first delay, a second delay, and a third delay according to the echo delay value; wherein, the first delay is the delay value of the scatter point closest to the radar among all multi-scatter point targets, the second delay is the delay value between scatter point targets, and the third delay is the delay value between the scatter points of the multi-scatter point target itself; Implementing a delay of the first delay for the baseband signal through off-chip DDR of the FPGA to obtain a first delayed signal; Implementing a delay of the second delay for the first delayed signal through a cascaded FIFO and a multiplexer implemented by on-chip Ultra RAM of the FPGA to obtain a second delayed signal; Implementing a delay of the third delay for the second delayed signal through a parallel FIFO implemented by on-chip Block RAM of the FPGA to obtain a third delayed signal; the third delayed signal includes multi-path scatter point echo signals; By moving each path of scatter point echo signal within one clock cycle to make its delay accuracy less than one working clock cycle of the FPGA, obtaining multi-path scatter point echo signals with precise delay; Merging the multi-path scatter point echo signals with precise delay, and performing interpolation, up-conversion, and DAC on the multi-scatter point target echo analog signal obtained after merging.

2. The method for realizing echo simulation of multi-scattering point targets based on multi-resource collaboration according to claim 1, wherein The method further includes: When merging the multi-path scatter point echo signals with precise delay, determining whether a data overflow phenomenon occurs; if a data overflow phenomenon occurs, ensuring the continuation of the merging by performing data saturation processing.

3. The method for simulating the echo of a multi-scattering point target based on multi-resource collaboration according to claim 1, wherein The calculating the echo delay value according to the distance between the scatter points of the multi-scatter point target and the radar includes: Setting m scatter point targets, each scatter point target including n scatter points; m>1, n>1; Calculating the echo delay value of each scatter point according to the distance between each scatter point of each multi-scatter point target and the radar; Sorting the scatter point targets in ascending order of the distance from the radar, and sorting the scatter points of each scatter point target in ascending order of the distance from the radar, and constructing an echo delay value matrix with the calculated m×n echo delay values according to the sorting result.

4. The method for simulating the echo of a multi-scattering point target based on multi-resource collaboration according to claim 3, characterized in that In the echo delay value matrix, the element in the i-th row (i = [1, 2,..., m]) and the j-th column (j = [1, 2,..., n]) is the echo delay value of the j-th scatter point (i, j) of the i-th scatter point target; The determining the first delay, the second delay, and the third delay according to the echo delay value includes: Take the element t in the first row and the first column of the echo delay value matrix tdelay 11 as the first delay of the scattering point (i, j); For the echo delay value matrix t delay in the first column elements, calculate each element t in this column of elements i1 and the difference from the first element t 11 of this column to obtain the second delay Δi of the scattering point (i, j); Calculate the echo delay value matrix t delay for each element t ij in it, and calculate the difference between it and the element t 11 at the first row and first column to obtain the sum of the second delay Δi and the third delay δ ij of the scatter point (i, j); Subtract the second delay Δi of the scattering point (i, j) from the sum of the second delay Δi and the third delay δ of the scattering point (i, j) to obtain the third delay δ of the scattering point (i, j). ij ij .​ 5. The method for implementing echo simulation of multi-scattering point targets based on multi-resource collaboration according to claim 4, characterized in that The multiplexer includes m - 1; in the cascaded FIFO, the output of each stage of FIFO is connected to each multiplexer; The implementing a delay of the second delay for the first delayed signal through the cascaded FIFO and the multiplexer implemented by on-chip Ultra RAM of the FPGA to obtain a second delayed signal includes: Inputting the first delayed signal into the cascaded FIFO, implementing delays of different sizes of the second delay for the first delayed signal by selecting FIFOs of different stages through each multiplexer, and respectively outputting second delayed signals of m - 1 multi-scatter point targets through m - 1 multiplexers.

6. The method for simulating the echo of a multi-scattering point target based on multi-resource collaboration according to claim 5, wherein The parallel FIFOs include multiple ones, and the multiple parallel FIFOs correspond to multiple multiplexers one by one; wherein, the input of each parallel FIFO is the second delayed signal output by its corresponding multiplexer. For the parallel FIFO implemented by the on-chip Block RAM of the FPGA, delaying the second delayed signal to achieve a third delay to obtain a third delayed signal includes: Inputting the second delayed signal output by the multiplexer into each FIFO in the corresponding parallel FIFO, so as to delay the second delayed signal by the third delay through each FIFO in the parallel FIFO, and outputting multi-path scattered point echo signals through the respective FIFOs.

7. The method for simulating the echo of a multi-scattering point target based on multi-resource collaboration according to claim 5, wherein The number of FIFO stages and the FIFO depth of the cascaded FIFO are calculated and designed by using the following formula according to the number of multi-scattered point targets and the distance distribution range between the multi-scattered point targets: l＝2 n ； Where x is the number of FIFO stages, l is the FIFO depth, L is the total depth of cascaded FIFOs, m is the number of multi-scattering point targets, d is the maximum distance between multi-scattering point targets, f clk is the working clock frequency of the FPGA, c is the speed of light, n is a natural number, and n is related to the FIFO bit width and the resources of the Ultra RAM used.

8. The method for simulating the echo of a multi-scattering point target based on multi-resource collaboration according to claim 6, wherein The number of FIFOs of the parallel FIFO is the number of scattered points included in a single multi-scattered point target, and the FIFO depth of the parallel FIFO is the maximum third delay between the scattered points of the scattered point target, and this FIFO depth is a power of 2.

9. An apparatus for simulating the echo of a multi-scattering point target based on multi-resource collaboration, characterized in that, Including: A delay value calculation module, configured to calculate an echo delay value according to the distance between the scattered points of the multi-scattered point target from the radar, and determine a first delay, a second delay, and a third delay according to the echo delay value; wherein, the first delay is the delay value of the scattered point closest to the radar among the multi-scattered point targets, the second delay is the delay value between the scattered point targets, and the third delay is the delay value between the scattered points of the multi-scattered point target itself. A DDR delay module, configured to delay the baseband signal by the first delay through the off-chip DDR of the FPGA to obtain a first delayed signal. A cascaded FIFO module, configured to delay the first delayed signal by the second delay through the cascaded FIFO and multiplexer implemented by the on-chip Ultra RAM of the FPGA to obtain a second delayed signal. A parallel FIFO module, configured to delay the second delayed signal by the third delay through the parallel FIFO implemented by the on-chip Block RAM of the FPGA to obtain a third delayed signal; the third delayed signal includes multi-path scattered point echo signals. An accurate delay module, configured to move each path of scattered point echo signal within one clock cycle so that its delay accuracy is less than one working clock cycle of the FPGA to obtain an accurately delayed multi-path scattered point echo signal. A data accumulation and signal playback module, configured to merge the accurately delayed multi-path scattered point echo signals, and perform interpolation, up-conversion, and DAC on the multi-scattered point target echo analog signal obtained after the merging.

10. The multi-scattering point target echo simulation implementation device based on multi-resource collaboration according to claim 9, characterized in that, The data accumulation and signal playback module is further configured to: when merging the accurately delayed multi-path scattered point echo signals, determine whether a data overflow occurs; if a data overflow occurs, ensure the continuation of the merging by performing data saturation processing.

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