Control circuit for memory, operation method and electronic device

Abstract

A control circuit is used for being coupled to a memory through a plurality of channels, and the plurality of channels comprise a first channel. The control circuit comprises a storage circuit and a processor. The storage circuit is used for storing a plurality of read voltage tables and index registers. The processor is coupled to the storage circuit and is used for executing a first reread test on the memory by using the plurality of read voltage tables in sequence through the first channel until the first reread test is successfully executed by using a target read voltage table in the plurality of read voltage tables when an error occurs in the read operation of the first channel. When the processor successfully executes the first reread test, the processor determines whether to update the index register according to the change history of the stored data in the index register. Therefore, the probability of retry reading can be reduced, and the reading efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to memory technologies, and more particularly to a control circuit for a memory and an operation method thereof. Background Art

[0002] A memory control circuit reads a memory by applying a threshold voltage to a word line of the memory. Memory cells that are often operated together (e.g., multiple pages in the same block) may have similar characteristics. Thus, for example, the memory control circuit may use the same threshold voltage setting (e.g., threshold voltage offset) to read multiple pages in the same block, and the memory control circuit may update the threshold voltage setting when a read failure occurs, thereby reducing the probability of read failure. However, if the threshold voltage setting is updated every time a read failure occurs, the memory control circuit may continuously use a threshold voltage setting with a low read success rate, which may instead increase the probability of read failure. Summary of the Invention

[0003] This disclosure provides a control circuit for coupling to a memory through multiple channels, and the multiple channels include a first channel. The control circuit includes a storage circuit and a processor. The storage circuit is used to store multiple read voltage tables and an index register. The processor is coupled to the storage circuit and is configured to, when an error occurs in the read operation of the first channel, perform a first reread test on the memory through the first channel using the multiple read voltage tables in sequence until the first reread test is successfully performed using a target read voltage table in the multiple read voltage tables. When the processor successfully performs the first reread test, the processor determines whether to update the index register based on analyzing the change history of the stored data in the index register.

[0004] In one embodiment, the change history represents the adjustment process of the stored data in the index register during a preset period after an error occurs in the read operation of the first channel.

[0005] In one embodiment, the index register stores an initial index value, and the processor uses one of the multiple read voltage tables corresponding to the initial index value to perform the read operation of the first channel.

[0006] In one embodiment, when the processor successfully performs the first reread test, the processor determines whether to update the index register based on analyzing the change history to determine whether the index register has been updated.

[0007] In one embodiment, when the processor determines, based on the analysis of the change history, that the index register has not been updated during the first period from when a read operation of the index register in the first channel encounters an error to when the first reread test is successfully executed, the processor updates the index register with a target index value corresponding to the target read voltage table. When the processor determines, based on the analysis of the change history, that the index register has been updated during the first period, the processor does not update the index register with the target index value.

[0008] In one embodiment, the multiple channels include a second channel, and the update of the index register during the first period is associated with a second reread test that the processor performs on the memory through the second channel during the first period.

[0009] In one embodiment, when the processor successfully executes the first reread test, the processor updates the index register based on the relationship between the following two obtained by analyzing the change history: (1) the initial index value stored when a read operation of the index register in the first channel encounters an error; and (2) the target index value corresponding to the target read voltage table.

[0010] In one embodiment, when the processor determines, based on the analysis of the change history, that the initial index value is the same as the target index value, the processor does not update the index register with the target index value. When the processor determines, based on the analysis of the change history, that the initial index value is different from the target index value, the processor updates the index register with the target index value.

[0011] The present disclosure provides an operation method applicable to a control circuit. The control circuit is used to couple to a memory through multiple channels, and the multiple channels include a first channel. A storage circuit of the control circuit stores an index register and multiple read voltage tables. The operation method includes: when a read operation of the first channel encounters an error, sequentially performing, through the first channel, a first reread test on the memory using the multiple read voltage tables until the first reread test is successfully executed using the target read voltage table in the multiple read voltage tables; and when the first reread test is successfully executed, determining whether to update the index register based on an analysis of the change history of the stored data of the index register.

[0012] In one embodiment, the change history represents the adjustment process of the stored data in the index register during a preset period after a read operation of the index register in the first channel encounters an error.

[0013] In one embodiment, when the first reread test is successfully executed, determining whether to update the index register based on an analysis of the change history of the stored data of the index register includes: determining whether to update the index register based on a judgment of whether the index register has been updated by analyzing the change history.

[0014] In one embodiment, determining whether to update the index register based on analyzing the change history includes: when it is determined based on the analyzed change history that the index register has not been updated during a first period from an error in the read operation of the first channel to the successful execution of the first reread test, updating the index register with a target index value corresponding to a target read voltage table; and when it is determined based on the analyzed change history that the index register has been updated during the first period, not updating the index register with the target index value.

[0015] In one embodiment, the multiple channels include a second channel, and the update of the index register during the first period is associated with a second reread test performed on the memory through the second channel during the first period.

[0016] In one embodiment, determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: updating the index register based on the relationship between the following two obtained by analyzing the change history: (1) an initial index value stored when an error occurs in the read operation of the first channel of the index register; and (2) a target index value corresponding to a target read voltage table.

[0017] In one embodiment, updating the index register based on the relationship obtained by analyzing the change history includes: when it is determined based on the analyzed change history that the initial index value is the same as the target index value, not updating the index register with the target index value; and when it is determined based on the analyzed change history that the initial index value is different from the target index value, updating the index register with the target index value.

[0018] The present disclosure provides an electronic device, which includes a memory and a control circuit. The control circuit is coupled to the memory and is used to store a plurality of read voltage tables and an index register. The control circuit is used to execute a first thread, and the first thread is used to: when an error occurs in the read operation of the first thread, sequentially perform a first reread test on the memory using the plurality of read voltage tables until the first reread test is successfully performed using a target read voltage table in the plurality of read voltage tables; and when the first reread test is successfully performed, determine whether to update the index register based on analyzing the change history of the stored data in the index register.

[0019] In one embodiment, the control circuit is further used to execute a second thread, and determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: analyzing the change history to determine whether the index register has been updated by the second thread to determine whether to update the index register.

[0020] In one embodiment, analyzing the change history to determine whether the index register has been updated by a second thread to decide whether to update the index register includes: when it is determined according to the analysis of the change history that the second thread has not updated the index register during a first period from an error in the read operation of the first thread to the successful execution of the first reread test, updating the index register with a target index value corresponding to a target read voltage table; and when it is determined according to the analysis of the change history that the index register has been updated during the first period, not updating the index register with the target index value.

[0021] In one embodiment, determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: updating the index register based on the relationship between the following two obtained from the analysis of the change history: (1) an initial index value stored when a read operation of the index register on a first channel encounters an error; and (2) a target index value corresponding to a target read voltage table.

[0022] In one embodiment, updating the index register based on the relationship obtained from the analysis of the change history includes: when it is determined according to the analysis of the change history that the initial index value is the same as the target index value, not updating the index register with the target index value; and when it is determined according to the analysis of the change history that the initial index value is different from the target index value, updating the index register with the target index value.

[0023] One of the advantages of the above control circuit, operation method, and electronic device is that it can reduce the probability of read retry to improve the read efficiency. Description of the Drawings

[0024] Figure 1 It is a simplified functional block diagram of an electronic device according to an embodiment of the present disclosure document.

[0025] Figure 2 It is a schematic diagram of a mapping table according to an embodiment of the present disclosure document.

[0026] Figure 3 It is a schematic diagram of the correspondence relationship among a superpage, an index register, and a read voltage table according to an embodiment of the present disclosure document.

[0027] Figure 4 It is a flowchart of an operation method according to an embodiment of the present disclosure document.

[0028] Figure 5 It is a detailed flowchart of the steps of an operation method according to an embodiment of the present disclosure document.

[0029] Figure 6 It is a detailed flowchart of the steps of an operation method according to an embodiment of the present disclosure document.

[0030] Figure 7 A flowchart of additional steps of an operation method according to an embodiment of the present disclosure document.

[0031] Figure 8 A schematic diagram of updating an index register by an operation method according to an embodiment of the present disclosure document. Detailed implementation manners

[0032] Embodiments of the present disclosure document will be described below in conjunction with relevant drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0033] Figure 1 A simplified functional block diagram of an electronic device 100 according to an embodiment of the present disclosure document. The electronic device 100 includes a control circuit 110 and a memory 120, wherein. The control circuit 110 is configured to perform read, write, and erase operations on the memory 120 correspondingly according to read, write, and erase instructions of an external arithmetic circuit (not shown, such as a central processing unit). In some embodiments, the memory 120 may be implemented by a flash memory or other suitable type of non-volatile memory.

[0034] The control circuit 110 includes a processor 112 and a storage circuit 114 which are coupled to each other. The processor 112 is communicatively coupled to a plurality of logical units (LUNs, or also referred to as Dies) 122[0] to 122[3] of the memory 120 through a plurality of channels CH[0] to CH[3]. Each of the logical units 122[0] to 122[3] includes a plurality of blocks, and each block further includes a plurality of pages. The storage circuit 114 stores a plurality of index registers ID0 to IDn, a mapping table TA, and a plurality of read voltage tables TB0 to TBk, where k is a positive integer greater than 1.

[0035] Figure 2 A schematic diagram of the mapping table TA according to an embodiment of the present disclosure document. The mapping table TA includes a plurality of index values 0 to k, and records that the index values 0 to k respectively correspond to the read voltage tables TB0 to TBk. Each of the index registers ID0 to IDn is used to store one of the index values 0 to k. For example, the index registers ID0 and ID1 may store the same index value 1; the index register ID2 may store the index value 3, and so on.

[0036] Please refer to Figures 2 to 3 simultaneously, wherein Figure 3Schematic diagram of the correspondence between super pages SP0 to SPn, index registers ID0 to IDn, and read voltage tables TB0 to TBk according to an embodiment of the present disclosure. Pages with the same physical location in logic units 122[0] to 122[3] can be combined into super pages SP0 to SPn. For example, multiple page 0s are combined into super page SP0; multiple page 1s are combined into super page SP2; and multiple page ns are combined into super page SPn, and so on, where n is a positive integer greater than 1. Index registers ID0 to IDn respectively correspond to super pages SP0 to SPn. A super page is the minimum unit when the processor 112 reads the memory 120. The processor 112 is used to read a super page simultaneously through channels CH[0] to CH[3], and the processor 112 will perform a read operation on the super page according to the stored data in the index register corresponding to the super page.

[0037] For example, as Figure 3 shown, when the processor 112 reads the super page SP0, the processor 112 will use the read voltage table TB1 corresponding to the index value 1 based on the index value 1 stored in the index register ID0 and based on the mapping relationship of the index value 1 in the mapping table TA to read the super page SP0. Similarly, since the index value 1 is stored in the index register ID1, the processor 112 will use the read voltage table TB1 to read the super page SP1. For another example, since the index value k is stored in the index register IDn, the processor 112 will use the read voltage table TBk to read the super page SPn.

[0038] The following describes the uses of the read voltage tables TB1 to TBk. When reading the memory 120, the processor 112 will sequentially apply one or more threshold voltages to the word lines to determine the bit values stored in the memory cells of the memory 120. For example, if the memory 120 is a multi-level cell (MLC) memory, the processor 112 will sequentially apply 3 different threshold voltages to the word lines. For another example, if the memory 120 is a triple-level cell (TLC) memory, the processor 112 will sequentially apply 7 different threshold voltages to the word lines. Each of the read voltage tables TB0 to TBk records the offsets of the aforementioned one or more threshold voltages, and the processor 112 can adjust the threshold voltages applied to the word lines according to the offsets recorded in the read voltage tables TB0 to TBk to compensate for the threshold voltage variations generated by the memory 120 under different usage conditions (such as ambient temperature or total usage hours).

[0039] When a read error occurs during the process of the processor 112 reading a certain superpage (for example, an ECC check error occurs), the processor 112 can update the index value register corresponding to the superpage, so as to use a read voltage table with better compensation effect in subsequent read operations. The following will be described in conjunction with Figures 3 to 7 a detailed description.

[0040] Figure 4 FIG. 400 is a flowchart of an operation method 400 according to an embodiment of the present disclosure. The operation method 400 is applicable to Figure 1 the control circuit 110. In the following embodiments, it is assumed that the control circuit 110 reads the superpage SP0 and adaptively updates the index register ID0 corresponding to the superpage SP0. However, the present disclosure is not limited thereto. The index registers ID1-IDn of other superpages SP1-SPn can also be adaptively updated in a similar manner. For the sake of simplicity, this will not be repeated here. It is worth mentioning that since the threads of channels CH0-CH3 will simultaneously read the superpage SP0, these threads may successively have read errors in a short period of time. Among them, the operation method 400 can prevent these threads from repeatedly updating the index register ID0 in a short period of time.

[0041] In step S410, in response to receiving a read instruction for the superpage SP0, the processor 112 accesses the index register ID0 corresponding to the superpage SP0 among the multiple index registers ID0-IDn of the storage circuit 114. Therefore, the processor 112 obtains the initial index value (for example, index value 1) stored in the index register ID0.

[0042] In step S420, the processor 112 executes a first thread. The first thread selects the read voltage table TB1 from the multiple read voltage tables TB0-TBk corresponding to the initial index value according to the mapping relationship in the mapping table TA based on the initial index value (for example, index value 1), as Figure 3 shown. Then, the first thread uses the read voltage table TB1 through the channel CH0 to perform the read operation of the first thread (or channel CH0) on the part of the logical unit 122[0] belonging to the superpage SP0. Specifically, the first thread will determine one or more threshold voltages applied to the multiple word lines of the memory 120 according to the read voltage table TB1 to perform its read operation on the part of the logical unit 122[0] belonging to the superpage SP0. For ease of understanding, the first thread is described as performing the read operation through the channel CH0 in Figure 4 the embodiment, but the present disclosure is not limited thereto. In some embodiments, the first thread can perform the read operation through any one of the channels CH0-CH3.

[0043] In step S430, when an error occurs in the read operation of the first thread (or channel CH0) (such as an ECC check error), the first thread sequentially uses read voltage tables TB0 to TBk to perform a first re-read test on the logic unit 122[0] through channel CH0 until a first re-read test is successfully performed using one of the read voltage tables TB0 to TBk. Specifically, the first thread first uses read voltage table TB0 to determine the threshold voltage applied to the word line, reads the bit values of the memory cells belonging to superpage SP0 in the logic unit 122[0], and determines whether an ECC check error occurs. If an ECC check error occurs, it means that the first re-read test fails. The first thread will then use read voltage table TB1 to determine the threshold voltage applied to the word line to read the bit values of the memory cells belonging to superpage SP0 in the logic unit 122[0], and determine whether an ECC check error occurs, and so on. On the other hand, if the ECC check of the first re-read test is correct after the first thread uses a certain read voltage table, it means that the first re-read test is successful, and the control circuit 110 ends step S430, and so on. For ease of explanation, the read voltage table that successfully performs the first re-read test will be referred to as the target read voltage table below.

[0044] When the first re-read test is successfully performed, the first thread analyzes the change history of the index register ID0 and determines whether to update the index register ID0 based on the analysis result, where the change history can be stored in the storage circuit 114. In some embodiments, the change history of the index register ID0 represents the adjustment process of the stored data in the index register ID0 during a preset period (such as Figure 8 periods P0 to P10) after an error occurs in the read operation of the first thread (or channel CH0). Specifically, in step S440, when the first re-read test is successfully performed, the first thread determines whether to update the index register ID0 by analyzing whether the index register ID0 has been updated (such as updated by other threads) based on the change history of the index register ID0. In step S450, when the first re-read test is successfully performed, the first thread determines whether to update the index register ID0 based on the relationship between the following two obtained by analyzing the change history: (1) the initial index value stored in the index register ID0 when an error occurs in the read operation of channel CH0 (for example, the index value 1); and (2) the target index value, where the target index value corresponds to the target read voltage table that makes the first re-read test successful.

[0045] Please refer to Figure 5 where Figure 5A detailed flowchart of step S440 according to an embodiment of the present disclosure document. Step S440 includes steps S442 to S444. In step S442, the first thread determines whether the index register ID0 has not been updated during the first period from an error in the read operation to the successful execution of the first re-read test. If the determination in step S442 is "yes" (i.e., the index register ID0 has not been updated by other threads during the first period), the control circuit 110 will execute step S450 to further determine whether to update the index register ID0 with the target index value. If the index register ID0 has been updated by other threads during the first period, the determination in step S442 is "no", and the control circuit 110 will execute step S444. In step S444, the first thread does not update the index register ID0 with the target index value and ends the execution of the operation method 400.

[0046] In some embodiments, the update of the index register ID0 during the first period may be triggered, for example, by a second thread executed by the processor 112 through a second re-read test on the super page SP0 through the channel CH1 during the first period. In summary, step S440 is used to analyze the change history of the index register ID0 to determine whether other threads have updated the index register ID0 during the first period, and then decide whether to update the index register ID0. If the index register ID0 has been updated by other threads, the index value stored in the current index register ID0 may have a higher read success rate (i.e., the read voltage table corresponding to the current index value may have a higher read success rate). Step S440 helps to keep the index register ID0 with an index value that may have a higher read success rate.

[0047] Please refer to Figure 6 , wherein Figure 6 is a detailed flowchart of step S450 according to an embodiment of the present disclosure document, and step S450 includes steps S452 to S456. In step S452, the first thread determines whether the initial index value when the first read operation fails is the same as the target index value when the first re-read test is successfully executed. If the determination in step S452 is "yes", the control circuit 110 will execute step S454 and not update the index register ID0 with the target index value. If the determination in step S452 is "no", the control circuit 110 will execute step S456 to cause the first thread to update the index register ID0 with the target index value, that is, update the stored data in the index register ID0 to the target index value. In summary, step S450 helps to avoid repeatedly storing index values with a lower read success rate in the index register ID0.

[0048] Please refer to Figure 7 , wherein Figure 7Flowcharts of additional steps S460 to S490 of the operation method 400 according to an embodiment of the present disclosure document. As described above, the processor 112 executes multiple threads to simultaneously read the superpage SP0 through channels CH0 to CH3, and these threads may successively encounter read errors in a short period of time. The foregoing Figure 3 Is used to illustrate the case where a read error occurs in channel CH0 and the index register ID0 is selectively updated. Figure 6 Is used to illustrate the case where a read error also occurs in channel CH1 and the content of the index register ID0 is successively updated by channels CH0 and CH1. The control circuit 110 can perform operations similar to those described in steps S460 to S490 on channels CH2 to CH3. For the sake of brevity, it will not be repeated here.

[0049] In some embodiments, the operation method 400 further includes steps S460 to S490 that are executed in parallel with steps S420 to S450 (i.e., executed after step S410). In step S460, the processor 112 executes a second thread, and the second thread selects the read voltage table TB1 according to the initial index value (e.g., index value 1) stored in the index register ID0, as Figure 3 Shown. Then, the second thread uses the read voltage table TB1 through channel CH1 to determine the threshold voltage applied to the word line to perform a read operation on the portion of the logic unit 122[1] that belongs to the superpage SP0.

[0050] In step S470, when a read operation of the second thread (or channel CH1) encounters an error (e.g., an ECC check error occurs), the second thread sequentially uses the read voltage tables TB0 to TBk through channel CH1 to perform a second reread test on the logic unit 122[1] until the second reread test is successfully executed. Specifically, the second thread first uses the read voltage table TB0 to determine the threshold voltage applied to the word line to read the bit value of the memory cell of the logic unit 122[1] that belongs to the superpage SP0, and determines whether an ECC check error occurs. If an ECC check error occurs, it means that the second reread test fails. The second thread will then use the read voltage table TB1 to determine the threshold voltage applied to the word line to read the bit value of the memory cell of the logic unit 122[1], and determine whether an ECC check error occurs, and so on. On the other hand, if the target read voltage table in the read voltage tables TB0 to TBk makes the ECC check of the second reread test correct, it means that the second reread test is successful, and the control circuit 110 ends step S470, and so on.

[0051] When the second re-reading test is successfully executed, the second thread analyzes the change history of the index register ID0 and decides whether to update the index register ID0 based on the analysis result. In some embodiments, the change history represents the adjustment process of the stored data in the index register ID0 during a preset period (e.g., Figure 8 the period P0 to P10) after an error occurs in the reading operation of the second thread (or channel CH1). Specifically, in step S480, the second thread determines whether the index register ID0 has been updated after an error occurs in the reading operation of the second thread (or channel CH1) based on the analysis of the change history, so as to decide whether to update the index register ID0. In step S490, the second thread decides whether to update the index register ID0 based on the relationship between the following two obtained from the analysis of the change history: (1) the initial index value (e.g., index value 1) stored in the index register ID0 when an error occurs in the reading operation of channel CH1; and (2) the target index value, where the target index value corresponds to the target reading voltage table that makes the second re-reading test successful. The details of steps S480 and S490 are respectively similar to those of steps S440 and S450. For the sake of brevity, they will not be repeated here.

[0052] Figure 8 FIG. is a schematic diagram of updating the index register ID0 by the operation method 400 according to an embodiment of the present disclosure. The following will be through Figure 8 illustrate the situation where channels CH0 to CH3 update the content of the index register ID0 due to successive reading errors in a short time when reading the superpage SP0. In period P0, in response to the instruction to read the superpage SP0, the processor 112 of the control circuit 110, as Figure 3 , Figure 8 shown, selects the reading voltage table TB1 according to the index value 1 in the index register ID0 and executes the first to fourth threads to read the superpage SP0 through channels CH0 to CH3 respectively. The first to fourth threads all have reading errors in period P0.

[0053] In periods P1 and P2, the first thread sequentially uses the reading voltage tables TB0 and TB1 to execute the first re-reading test and successfully executes the first re-reading test in period P2. Since the first thread uses the reading voltage table TB1 in both period P0 and period P2, according to Figure 5In step S450, the first thread does not update the index register ID0 with the index value 1 corresponding to the read voltage table TB1. During time periods P3 to P5, the second thread sequentially uses the read voltage tables TB0 to TB2 to perform the second reread test and successfully performs the second reread test during time period P5. Since the index register ID0 has not been updated during time periods P0 to P5 and the second thread uses different read voltage tables during time periods P0 and P5, according to Figures 5 to 6 In step S450, the second thread updates the index register ID0 with the index value 2 corresponding to the read voltage table TB2.

[0054] During time period P6, the third thread successfully performs the third reread test using the read voltage table TB0. Since the index register ID0 has been updated by the second thread during time period P5, according to Figure 5 In step S440, the third thread does not update the index register ID0 with the index value 0 corresponding to the read voltage table TB0. During time periods P7 to P10, the fourth thread sequentially uses the read voltage tables TB0 to TB3 to perform the fourth reread test and successfully performs the fourth reread test during time period P10. Since the index register ID0 has been updated by the second thread during time period P5, according to Figure 5 In step S440, the fourth thread does not update the index register ID0 with the index value 3 corresponding to the read voltage table TB3. Therefore, the index register ID0 is finally updated to the index value 2 corresponding to the read voltage table TB2.

[0055] In summary, when repeatedly reading the same superpage, the operation method 400 helps to increase the chance for the control circuit 110 to use a read voltage table with a higher read success rate, thereby reducing the probability of a read retry to improve the read efficiency.

[0056] In the above-described multiple embodiments, index registers ID0 to IDn respectively correspond to super pages SP0 to SPn. Therefore, multiple pages in each super page share the same index value (i.e., share the same read voltage table), but the present disclosure is not limited thereto. The operation method 400 is also applicable to embodiments in which the memory cells in the memory 120 are grouped in other forms to share an index value (i.e., share the same read voltage table). In some embodiments, blocks having the same physical location in the logic units 122[0] to 122[3] can be combined into multiple super blocks, and the index registers ID0 to IDn respectively correspond to the multiple super blocks, so that multiple blocks in each super block share the same index value (i.e., share the same read voltage table). In other embodiments, pages having the same type of memory cells in the logic units 122[0] to 122[3] can be combined into super pages, and multiple pages in one super page share the same index value (i.e., share the same read voltage table). For example, multiple pages composed of multi-level cells (MLCs) can be combined into one super page, and multiple pages composed of triple-level cells (TLCs) can be combined into another super page.

[0057] Any combination of the features of the operation method 400 can be implemented as multiple instructions stored in a non-transitory computer-readable storage medium. When these instructions are executed by the processor 112, these instructions will cause part or all of the operation method 400 to be executed. It should be understood that the operation method 400 may include more or fewer steps than those shown in the flowchart, and the steps in the operation method 300 can be executed in any suitable order. For example, step S440 can be omitted, and the control circuit 110 can directly execute step S450 after the end of step S430. Another example is that step S450 can be omitted, and the control circuit 110 can directly update the index register ID0 with the target index value when the judgment in step S442 is "yes".

[0058] In the specification and claims, certain terms are used to refer to specific elements. However, those skilled in the art should understand that the same element may be referred to by different names. The specification and claims do not use the difference in names as a way to distinguish elements, but use the difference in the functions of the elements as the basis for distinction. The term "comprising" mentioned in the specification and claims is an open-ended term, so it should be interpreted as "comprising but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission and other signal connection means, or indirectly electrically or signal-connected to the second element through other elements or connection means.

[0059] In addition, unless otherwise specified in the specification, any singular term shall also include the plural meaning.

[0060] The above are only the preferred embodiments of this disclosure document. Without departing from the scope or spirit of this disclosure document, various modifications and equivalent changes can be made to this disclosure document. In summary, all modifications and equivalent changes made to this disclosure document within the scope of the following claims are covered by this disclosure document.

[0061]

Symbol Explanation

[0062] 100: Electronic device

[0063] 110: Control circuit

[0064] 112: Processor

[0065] 114: Storage circuit

[0066] 120: Memory

[0067] 122[0]-122[3]: Logic unit

[0068] CH0-CH3: Channel

[0069] ID0-IDn: Index register

[0070] k: Index value

[0071] TA: Mapping table

[0072] TB0-TBk: Read voltage table

[0073] SP0-SPn: Super page

[0074] 400: Operating method

[0075] S410-S490: Steps

[0076] S442-S444: Steps

[0077] S452-S456: Steps

[0078] P0-P10: Time period

[0079] n: Page.

Claims

1. A control circuit for being coupled to a memory through multiple channels, characterized in that The multiple channels include a first channel, and the control circuit includes: a storage circuit for storing a plurality of read voltage tables and an index register; and a processor, coupled to the storage circuit, for, when an error occurs in the read operation of the first channel, performing a first re-reading test on the memory through the first channel sequentially using the plurality of read voltage tables until the first re-reading test is successfully performed using a target read voltage table among the plurality of read voltage tables, wherein when the processor successfully performs the first re-reading test, the processor determines whether to update the index register based on analyzing a change history of stored data in the index register.

2. The control circuit according to claim 1, wherein The change history represents an adjustment process of the stored data in the index register during a preset period after the error occurs in the read operation of the first channel.

3. The control circuit according to claim 1, wherein The index register stores an initial index value, and the processor uses one of the plurality of read voltage tables corresponding to the initial index value to perform the read operation of the first channel.

4. The control circuit according to claim 1, wherein When the processor successfully performs the first re-reading test, the processor determines whether to update the index register based on analyzing whether the index register has been updated by analyzing the change history.

5. The control circuit according to claim 4, characterized in that When the processor, based on analyzing the change history, determines that the index register has not been updated during a first period from when the error occurs in the read operation of the first channel to when the first re-reading test is successfully performed, the processor updates the index register with a target index value corresponding to the target read voltage table, when the processor, based on analyzing the change history, determines that the index register has been updated during the first period, the processor does not update the index register with the target index value.

6. The control circuit according to claim 5, wherein The multiple channels include a second channel, and an update of the index register during the first period is associated with a second re-reading test performed by the processor on the memory through the second channel during the first period.

7. The control circuit according to claim 1, characterized in that, When the processor successfully performs the first re-reading test, the processor updates the index register based on a relationship between the following two obtained by analyzing the change history: (1) an initial index value stored in the index register when the error occurs in the read operation of the first channel; and (2) a target index value corresponding to the target read voltage table.

8. The control circuit according to claim 7, characterized in that When the processor, based on analyzing the change history, determines that the initial index value is the same as the target index value, the processor does not update the index register with the target index value, when the processor, based on analyzing the change history, determines that the initial index value is different from the target index value, the processor updates the index register with the target index value.

9. An operating method, applicable to a control circuit, characterized in that, The control circuit is used to be coupled to a memory through multiple channels, the multiple channels include a first channel, the storage circuit of the control circuit stores an index register and a plurality of read voltage tables, and the operation method includes: when an error occurs in the read operation of the first channel, performing a first re-reading test on the memory through the first channel sequentially using the plurality of read voltage tables until the first re-reading test is successfully performed using a target read voltage table among the plurality of read voltage tables; and When the first reread test is successfully executed, it is determined whether to update the index register based on analyzing the change history of the stored data in the index register.

10. The operating method according to claim 9, characterized in that, This change history represents the adjustment process of the stored data in the index register during a preset period after an error occurs in the read operation of the first channel.

11. The operating method according to claim 9, characterized in that, When the first reread test is successfully executed, determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: determining whether to update the index register based on analyzing whether the index register has been updated by analyzing the change history.

12. The operating method according to claim 11, characterized in that, Determining whether to update the index register based on analyzing whether the index register has been updated by analyzing the change history includes: When it is determined based on analyzing the change history that the index register has not been updated during the first period from when an error occurs in the read operation of the first channel to when the first reread test is successfully executed, the index register is updated with the target index value corresponding to the target read voltage table; And When it is determined based on analyzing the change history that the index register has been updated during the first period, the index register is not updated with the target index value.

13. The operating method according to claim 12, characterized in that, The multiple channels include a second channel, The update of the index register during the first period is associated with a second reread test performed on the memory through the second channel during the first period.

14. The operating method according to claim 9, characterized in that, Determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: Updating the index register based on the relationship between the following two obtained by analyzing the change history: (1) the initial index value stored in the index register when an error occurs in the read operation of the first channel; and (2) the target index value corresponding to the target read voltage table.

15. The operating method according to claim 14, characterized in that, Updating the index register based on the relationship obtained by analyzing the change history includes: When it is determined based on analyzing the change history that the initial index value is the same as the target index value, the index register is not updated with the target index value; and When it is determined based on analyzing the change history that the initial index value is different from the target index value, the index register is updated with the target index value.

16. An electronic device, characterized in that, Includes: A memory; and A control circuit, coupled to the memory, for storing a plurality of read voltage tables and an index register, Wherein the control circuit is used to execute a first thread, and the first thread is used for: When an error occurs in the read operation of the first thread, sequentially using the plurality of read voltage tables to perform a first reread test on the memory until the first reread test is successfully executed using the target read voltage table in the plurality of read voltage tables; And When the first reread test is successfully executed, it is determined whether to update the index register based on analyzing the change history of the stored data in the index register.

17. The electronic device according to claim 16, wherein The control circuit is further used to execute a second thread, wherein determining whether to update the index register based on analyzing the change history of the stored data in the index register includes: analyzing the change history to determine whether the index register has been updated by the second thread to determine whether to update the index register.

18. The electronic device according to claim 17, characterized in that, Analyze the change history to determine whether the index register has been updated by the second thread, and decide whether to update the index register, including: When it is determined according to the analysis of the change history that the second thread does not update the index register during the first period from the occurrence of an error in the read operation of the first thread to the successful execution of the first re-read test, update the index register with the target index value corresponding to the target read voltage table; and When it is determined according to the analysis of the change history that the index register has been updated during the first period, do not update the index register with the target index value.

19. The electronic device according to claim 16, wherein, Determine whether to update the index register according to the analysis of the change history of the stored data of the index register, including: Update the index register according to the relationship between the following two obtained from the analysis of the change history: (1) the initial index value stored when an error occurs in the read operation of the first channel of the index register; and (2) the target index value corresponding to the target read voltage table.

20. The electronic device according to claim 19, wherein Update the index register according to the relationship obtained from the analysis of the change history, including: When it is determined according to the analysis of the change history that the initial index value is the same as the target index value, do not update the index register with the target index value; and When it is determined according to the analysis of the change history that the initial index value is different from the target index value, update the index register with the target index value.

Images