Capacitive switching power supply converter packaging structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a capacitive switching power converter packaging structure and a preparation method thereof, the packaging structure comprises an IPD wafer and an SCVR layer, the IPD wafer comprises a plurality of DTC chip first dielectric layers; the surface of each DTC chip comprises a plurality of first metal bonding pads; the first metal bonding pad is exposed on the surface of the IPD wafer; the SCVR layer comprises at least one SCVR chip; the SCVR chip comprises a plurality of second metal bonding pads and a second dielectric layer, and the second metal bonding pads and the second dielectric layer are located on the surface of one side of the IPD wafer; the IPD wafer and the SCVR layer are connected into an integrated structure through hybrid bonding, the first dielectric layer and the second dielectric layer are in contact and bonding connection, and the first metal bonding pads and the second metal bonding pads are in one-to-one correspondence contact and bonding connection. According to the packaging structure, the occupied area of the DTC capacitor can be reduced, the size of the packaging structure is reduced, and the integration level, stability and reliability of the packaging structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a capacitive switched-mode power supply converter packaging structure and a preparation method thereof. Background Art

[0002] To reduce the impedance of the power delivery network (PDN), improve the efficiency of the power network, and reduce the system power consumption, the integrated voltage regulator (IVR) technology has become a potential solution. The IVR technology can be divided into two technical routes: capacitive switched-mode power supply and inductive switched-mode power supply. However, since an inductor that meets the requirements of the IVR system cannot be integrated in the interposer of the 2.5D package, the current inductive switched-mode power supply can only integrate the inductor in the plastic package substrate, which not only occupies the area of the plastic package substrate, but also extends the power transmission path, increases the system power consumption, and affects the overall layout and wiring.

[0003] Although the switched-capacitor voltage regulator (SCVR) does not require the integration of an inductor, it also needs to solve the problem of capacitor embedding. The current capacitor solutions include: (1) mounting the capacitor on the bottom of the plastic package substrate. Although this solution can integrate a large-capacity capacitor, the power transmission path is long, resulting in a large system power consumption and unable to meet the requirements of advanced packaging; (2) embedding the capacitor inside the plastic package substrate or the 2.5D interposer. This solution will increase the processing difficulty and production cost; (3) integrating the capacitor inside the SoC (system-on-chip) chip. This solution will occupy the area of the SoC chip, making the chip too large in volume and affecting the chip design.

[0004] Therefore, a solution is needed that can package the capacitor and the capacitive switched-mode power supply converter together, reduce the volume of the packaging structure, and improve the integration degree of the packaging structure. Summary of the Invention

[0005] In view of this, the present invention provides a capacitive switched-mode power supply converter packaging structure and a preparation method thereof to solve the problems in the related art that when embedding a capacitor in a capacitive switched-mode power supply converter, the capacitor occupies a large area, the power transmission path is long, the process difficulty and production cost are high, resulting in a low integration degree of the packaging structure, a low packaging density, a large system power consumption, and limited chip design.

[0006] In a first aspect, the present invention provides a capacitive switched-mode power supply converter packaging structure, which includes:

[0007] The IPD wafer includes a plurality of DTC chips and a first dielectric layer surrounding the DTC chips; each surface of the DTC chips includes a plurality of first metal pads; the first metal pads are exposed on the first surface of the IPD wafer.

[0008] The SCVR layer is located on the first surface of the IPD wafer. The SCVR layer includes at least one SCVR chip; the SCVR chip includes a plurality of second metal pads and a second dielectric layer located on the side of the second metal pads. The second metal pads and the second dielectric layer are located on the surface of the SCVR layer facing the IPD wafer.

[0009] The IPD wafer and the SCVR layer are connected into an integrated structure by hybrid bonding. Among them, each SCVR chip is connected to at least two DTC chips; the first dielectric layer and the second dielectric layer are in contact and bonded together, and the first metal pads and the second metal pads are in contact and bonded together one by one.

[0010] The capacitive switching power converter packaging structure provided by the present invention integrates the IPD wafer containing DTC chips and the SCVR layer containing SCVR chips by hybrid bonding technology. Among them, the first dielectric layer and the second dielectric layer are in contact and bonded together, and the first metal pads of the DTC chips and the second metal pads of the SCVR chips are in contact and bonded together one by one. On the one hand, since the volume of the DTC chips is small, the occupied area of the DTC capacitors in the capacitive switching power converter packaging structure can be reduced, the integration degree of the packaging structure can be improved, so that the integrated packaging structure has a small volume and a height as low as the micron level, and the cost can be reduced at the same time; on the other hand, the bonding interface of the packaging structure formed by hybrid bonding has strong bonding properties and less heat generation, which has little impact on the system heat dissipation, can improve the stability and reliability of the packaging structure, and can also shorten the power transmission path, reduce the system power consumption, and thus improve the performance of the capacitive switching power converter; on the third hand, the thermal expansion coefficient of the packaging structure matches that of the 2.5D packaging, so that the packaging structure can be integrated into the 2.5D packaging or used alone, improving the application scenarios and application flexibility of the capacitive switching power converter packaging structure. Therefore, the capacitive switching power converter packaging structure provided by the present invention can reduce the occupied area of the DTC capacitors, thereby reducing the height and volume of the capacitive switching power converter packaging structure, improving the integration degree of the packaging structure, reducing the cost, and can also improve the stability and reliability of the packaging structure, improve the performance of the capacitive switching power converter, and improve the application scenarios and application flexibility of the capacitive switching power converter packaging structure.

[0011] In an alternative embodiment, a first metal lead is further provided on the first surface of the IPD wafer, and each first metal lead is connected to a first metal pad of a DTC chip.

[0012] The capacitive switching power supply converter packaging structure further includes:

[0013] A plurality of metal bumps, located on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each metal bump is connected to at least one first metal lead; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads.

[0014] For the capacitive switching power supply converter packaging structure provided by the present invention, by providing the first metal leads and a plurality of metal bumps, the signals of the SCVR chip and the DTC chip can be led out to an external circuit. At the same time, the metal bumps are located on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer, which can enable multiple implementation methods of the capacitive switching power supply converter packaging structure and improve the application flexibility of the capacitive switching power supply converter packaging structure; the packaging structure can be used alone, in an array, as a single module, or integrated in a 2.5D package, and can be widely used in traditional packaging and advanced packaging. Especially in the IVR technology, it has high application flexibility and can meet the power supply requirements for future chiplet integration.

[0015] In an alternative embodiment, the metal bumps are located on the first surface of the IPD wafer and on the side of the SCVR chip; the metal bumps are in contact with and connected to the first metal leads; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads.

[0016] For the capacitive switching power supply converter packaging structure provided by the present invention, the SCVR chip and the DTC chip are connected together by hybrid bonding. The metal bumps are located on the first surface of the IPD wafer and on the side of the SCVR chip. The metal bumps lead out the signals of the SCVR chip and the DTC chip through the first metal leads, which can simplify the packaging structure, reduce costs, and can shorten the power transmission path, reduce the system power consumption, and thus improve the performance of the capacitive switching power supply converter.

[0017] In an alternative embodiment, the SCVR layer is an SCVR chip or an SCVR wafer; the SCVR wafer includes at least one SCVR chip;

[0018] The SCVR layer is provided with an interconnection lead-out structure, and the interconnection lead-out structure includes a second metal lead penetrating the SCVR layer and a third metal lead located on the surface of the SCVR layer facing away from the IPD wafer; the second metal lead is in contact with and connected to the first metal lead, and the third metal lead is in contact with and connected to the second metal lead;

[0019] The metal bumps are located on the surface of the SCVR layer facing away from the IPD wafer, and the metal bumps are in contact with and connected to the third metal leads; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal lead, the second metal lead, and the third metal lead.

[0020] For the capacitive switching power converter packaging structure provided by the present invention, the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal lead, the second metal lead, and the third metal lead, and the packaging structure can be mounted on the bottom of the substrate or integrated into a 2.5D package, so that there are multiple implementation methods for the capacitive switching power converter packaging structure, which can increase the application scenarios of the packaging structure and improve the application flexibility of the capacitive switching power converter packaging structure.

[0021] In an optional implementation manner, the SCVR layer further includes a third dielectric layer, and the third dielectric layer is located on the first surface of the IPD wafer and covers the surface and side surfaces of the SCVR chip;

[0022] A first through hole is further provided in the third dielectric layer, and the first through hole penetrates through the third dielectric layer; the second metal lead is located on the inner wall of the first through hole.

[0023] In an optional implementation manner, the area of the SCVR chip is smaller than the area of the IPD wafer;

[0024] When the SCVR layer is an SCVR chip, the material of the third dielectric layer is silicon dioxide;

[0025] When the SCVR layer is an SCVR wafer, the material of the third dielectric layer is silicon.

[0026] In an optional implementation manner, the area of the SCVR chip is greater than or equal to the area of the IPD wafer;

[0027] The SCVR chip includes a functional area and an edge area surrounding the functional area; the second metal pad is located in the functional area, and the functional area corresponds to the position of the DTC chip;

[0028] A second through hole is further provided in the edge area, and the second through hole penetrates through the edge area; the second metal lead is located on the inner wall of the second through hole.

[0029] In an optional implementation manner, the material of the first dielectric layer is silicon dioxide; the material of the second dielectric layer is silicon dioxide;

[0030] The material of the first metal pad is copper; the material of the second metal pad is copper;

[0031] The material of the first metal lead is copper.

[0032] In a second aspect, the present invention provides a method for manufacturing a capacitive switching power supply converter packaging structure for manufacturing the capacitive switching power supply converter packaging structure in the first aspect above. The manufacturing method includes:

[0033] Providing an IPD wafer; the IPD wafer includes a plurality of DTC chips and a first dielectric layer surrounding the DTC chips; each DTC chip surface includes a plurality of first metal pads; the first metal pads are exposed on the first surface of the IPD wafer;

[0034] Providing an SCVR layer, the SCVR layer includes at least one SCVR chip; the SCVR chip includes a plurality of second metal pads and a second dielectric layer located on the side of the second metal pads, and the second metal pads and the second dielectric layer are located on one surface of the SCVR layer facing the IPD wafer;

[0035] Bonding the IPD wafer and the SCVR layer into an integrated structure by hybrid bonding, wherein each SCVR chip is connected to at least two DTC chips; the first dielectric layer and the second dielectric layer are in contact and bonded together, and the first metal pads and the second metal pads are in one-to-one correspondence and bonded together.

[0036] The method for manufacturing the capacitive switching power supply converter packaging structure provided by the present invention integrates the IPD wafer containing DTC chips and the SCVR layer containing SCVR chips through hybrid bonding technology. On the one hand, it can reduce the occupied area of the DTC capacitor, thereby reducing the height and volume of the capacitive switching power supply converter packaging structure, improving the integration degree of the packaging structure, and at the same time, it can simplify the process flow and reduce the process cost; on the second hand, the bonding interface formed by hybrid bonding has strong bonding properties, which can improve the stability and reliability of the packaging structure, and at the same time, it can shorten the power transmission path, reduce the system power consumption, thereby improving the performance of the capacitive switching power supply converter, and at the same time, improving the application scenario and application flexibility of the capacitive switching power supply converter packaging structure.

[0037] In an optional implementation manner, a first metal lead is further provided on the first surface of the IPD wafer, and each first metal lead is connected to a first metal pad of a DTC chip;

[0038] After the step of bonding the IPD wafer and the SCVR layer into an integrated structure by hybrid bonding, the method further includes:

[0039] Forming a plurality of metal bumps on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each metal bump is connected to at least one first metal lead; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads.

[0040] In an alternative embodiment, the step of forming a plurality of metal bumps includes:

[0041] Forming a plurality of metal bumps on a first surface of an IPD wafer on a side of the SCVR chip; the metal bumps are in contact with and connected to the first metal leads; the metal bumps are adapted to lead out signals of the SCVR chip and the DTC chip through the first metal leads.

[0042] In an alternative embodiment, the SCVR layer is an SCVR chip or an SCVR wafer; the SCVR wafer includes at least one SCVR chip;

[0043] Before the step of forming a plurality of metal bumps, it further includes:

[0044] Forming an interconnection lead-out structure on the SCVR layer; the interconnection lead-out structure includes a second metal lead penetrating the SCVR layer and a third metal lead located on a surface of the SCVR layer facing away from the IPD wafer; the second metal lead is in contact with and connected to the first metal lead, and the third metal lead is in contact with and connected to the second metal lead;

[0045] Forming metal bumps on a surface of the SCVR layer facing away from the IPD wafer, the metal bumps are in contact with and connected to the third metal leads; the metal bumps are adapted to lead out signals of the SCVR chip and the DTC chip through the first metal leads, the second metal leads, and the third metal leads.

[0046] In an alternative embodiment, the SCVR layer further includes a third dielectric layer, the third dielectric layer is located on the first surface of the IPD wafer and covers the surface and sides of the SCVR chip;

[0047] Before the step of forming the interconnection lead-out structure, it further includes:

[0048] Forming a first through hole in the third dielectric layer, the first through hole penetrates the third dielectric layer;

[0049] The step of forming the interconnection lead-out structure includes:

[0050] Forming a second metal lead on an inner wall of the first through hole, the second metal lead is in contact with and connected to the first metal lead;

[0051] Forming a third metal lead on a surface of the third dielectric layer facing away from the IPD wafer, the third metal lead is in contact with and connected to the second metal lead.

[0052] In an alternative embodiment, the SCVR layer is an SCVR chip; the area of the SCVR chip is smaller than the area of the IPD wafer;

[0053] Before the step of forming the first through hole in the third dielectric layer, it further includes:

[0054] Form a third dielectric layer on the first surface of the IPD wafer on the side of the SCVR chip; the third dielectric layer covers the side and surface of the SCVR chip;

[0055] The material of the third dielectric layer is silicon dioxide.

[0056] In an alternative embodiment, the area of the SCVR chip is greater than or equal to the area of the IPD wafer;

[0057] The SCVR chip includes a functional area and an edge area; the second metal pad is located in the functional area, and the functional area corresponds to the position of the DTC chip;

[0058] Before the step of forming the interconnection lead-out structure, it further includes:

[0059] Form a second through hole in the edge area, and the second through hole penetrates the edge area;

[0060] The step of forming the interconnection lead-out structure includes:

[0061] Form a second metal lead on the inner wall of the second through hole, and the second metal lead contacts and connects with the first metal lead;

[0062] Form a third metal lead on the surface of the edge area facing away from the IPD wafer, and the third metal lead contacts and connects with the second metal lead. Description of the Drawings

[0063] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0064] Figure 1 It is a schematic structural diagram of a capacitive switching power supply converter packaging structure according to an embodiment of the present invention.

[0065] Figure 2 It is a schematic structural diagram of another capacitive switching power supply converter packaging structure according to an embodiment of the present invention.

[0066] Figure 3 It is a schematic structural diagram of yet another capacitive switching power supply converter packaging structure according to an embodiment of the present invention.

[0067] Figure 4 It is a schematic flowchart of a preparation method of a capacitive switching power supply converter packaging structure according to an embodiment of the present invention.

[0068] Figure 5It is a schematic diagram of the specific process of a preparation method for a capacitive switching power supply converter packaging structure according to an embodiment of the present invention.

[0069] Figure 6 It is a schematic diagram of the specific process of a preparation method for a capacitive switching power supply converter packaging structure provided in Example 1 of the embodiments of the present invention.

[0070] Figure 7 It is a schematic diagram of the structure of an IPD wafer in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 1 of the embodiments of the present invention.

[0071] Figure 8 It is a schematic diagram of the structure of an SCVR chip in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 1 of the embodiments of the present invention.

[0072] Figure 9 It is in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 1 of the embodiments of the present invention Figure 7 and Figure 8 Based on this, it is a schematic diagram of the integrated structure formed by hybrid bonding the IPD wafer and the SCVR chip.

[0073] Figure 10 It is in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 1 of the embodiments of the present invention Figure 9 Based on this, it is a schematic diagram of the structure forming metal bumps.

[0074] Figure 11 It is a schematic diagram of the specific process of a preparation method for a capacitive switching power supply converter packaging structure provided in Example 2 of the embodiments of the present invention.

[0075] Figure 12 It is in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 2 of the embodiments of the present invention Figure 9 Based on this, it is a schematic diagram of the structure forming a third dielectric layer.

[0076] Figure 13 It is in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 2 of the embodiments of the present invention Figure 12 Based on this, it is a schematic diagram of the structure forming a first via hole.

[0077] Figure 14 It is in a preparation method for a capacitive switching power supply converter packaging structure provided in Example 2 of the embodiments of the present invention Figure 13 Based on this, it is a schematic diagram of the structure forming a second metal lead.

[0078] Figure 15is a schematic structural diagram of forming a third metal lead and metal bumps based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 2 of the embodiments of the present invention Figure 14 on the basis of

[0079] Figure 16 is a specific process schematic diagram of the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention

[0080] Figure 17 is a schematic structural diagram of an SCVR wafer in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention

[0081] Figure 18 is a schematic structural diagram of forming a first via hole based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention Figure 7 and Figure 17 on the basis of which the IPD wafer and the SCVR wafer are connected into an integral structure by hybrid bonding

[0082] Figure 19 is a schematic structural diagram of forming a second metal lead based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention Figure 18 on the basis of

[0083] Figure 20 is a schematic structural diagram of forming a third metal lead and metal bumps based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention Figure 19 on the basis of

[0084] Figure 21 is a schematic structural diagram of forming a third metal lead and metal bumps based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 3 of the embodiments of the present invention Figure 20 on the basis of

[0085] Figure 22 is a specific process schematic diagram of the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 4 of the embodiments of the present invention

[0086] Figure 23 is a schematic structural diagram of an SCVR wafer in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 4 of the embodiments of the present invention

[0087] Figure 24 is a schematic structural diagram of forming a first via hole based on that in the method for preparing a capacitive switched-mode power supply converter packaging structure according to Example 4 of the embodiments of the present invention Figure 7 and Figure 23Schematic diagram of an integrated structure formed by hybrid bonding of an IPD wafer and an SCVR wafer on a substrate.

[0088] Figure 25 It is a schematic diagram of forming a second through-hole in the preparation method of a capacitive switching power supply converter packaging structure provided in Example 4 of the embodiments of the present invention on a Figure 24 substrate.

[0089] Figure 26 It is a schematic diagram of forming a second metal lead in the preparation method of a capacitive switching power supply converter packaging structure provided in Example 4 of the embodiments of the present invention on a Figure 25 substrate.

[0090] Figure 27 It is a schematic diagram of forming a third metal lead and metal bumps in the preparation method of a capacitive switching power supply converter packaging structure provided in Example 4 of the embodiments of the present invention on a Figure 26 substrate.

[0091] Reference numerals:

[0092] 10. DTC chip; 11. First metal pad; 12. First dielectric layer; 20. SCVR chip; 21. Second metal pad; 22. Second dielectric layer; 30. Third dielectric layer; 40. Metal bump; 51. First metal lead; 52. Second metal lead; 53. Third metal lead; 60. Through-hole filling material; 61. First through-hole; 62. Second through-hole. Detailed implementation manners

[0093] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, rather than all structures.

[0094] In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention. In the accompanying drawings, various structural schematic diagrams according to embodiments of the present invention are shown. These figures are not drawn to scale, where for the purpose of clear expression, certain details are enlarged and certain details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual requirements. In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0095] To reduce the impedance of the power delivery network (PDN), improve the efficiency of the power network, and reduce the system power consumption, the integrated voltage regulator (IVR) technology has become a potential solution. The IVR technology can be divided into two technical routes: capacitive switched-mode power supply and inductive switched-mode power supply. However, since it is impossible to integrate an inductor that meets the requirements of the IVR system in the interposer of a 2.5D package, the current inductive switched-mode power supply can only integrate the inductor in the plastic package substrate, which not only occupies the area of the plastic package substrate but also extends the power transmission path, increases the system power consumption, and affects the overall layout and wiring.

[0096] Although the switched-capacitor voltage regulator (SCVR) does not require the integration of an inductor, it also needs to solve the problem of capacitor embedding. The current capacitor solutions include: (1) surface-mounting the capacitor at the bottom of the plastic package substrate. Although this solution can integrate a large-capacity capacitor, the power transmission path is long, resulting in a large system power consumption and unable to meet the requirements of advanced packaging; (2) embedding the capacitor inside the plastic package substrate or in the 2.5D interposer. This solution will increase the processing difficulty and production cost; (3) integrating the capacitor inside the SoC (system-on-chip) chip. This solution will occupy the area of the SoC chip, making the chip too large in volume and affecting the chip design.

[0097] Therefore, a solution is needed that can package the capacitor and the switched-capacitor voltage regulator together to reduce the volume of the packaging structure and improve the integration degree of the packaging structure.

[0098] As Figure 1As shown, this embodiment provides a capacitive switched-mode power supply converter package structure, and the capacitive switched-mode power supply converter package structure includes:

[0099] An IPD (Integrated Passive Device) wafer, including a plurality of DTC (Deep Trench Capacitor) chips 10 and a first dielectric layer 12 surrounding the DTC chips 10; each DTC chip 10 surface includes a plurality of first metal pads 11; the first metal pads 11 are exposed on the first surface of the IPD wafer;

[0100] An SCVR (Switched-Capacitor Voltage Regulator) layer, located on the first surface of the IPD wafer, and the SCVR layer includes at least one SCVR chip 20; the SCVR chip 20 includes a plurality of second metal pads 21 and a second dielectric layer 22 located on the side of the second metal pads 21, and the second metal pads 21 and the second dielectric layer 22 are located on one side surface of the SCVR layer facing the IPD wafer;

[0101] The IPD wafer and the SCVR layer are connected into an integral structure by hybrid bonding, wherein each SCVR chip 20 is connected to at least two DTC chips 10; the first dielectric layer 12 and the second dielectric layer 22 are in contact and bonded together, and the first metal pads 11 and the second metal pads 21 are in one-to-one correspondence and bonded together.

[0102] In specific implementation, the arrangement of the first metal pads 11 of the DTC chips 10 corresponds one-to-one to the arrangement of the second metal pads 21 of the respective relevant functional ports on the SCVR chips 20.

[0103] The capacitive switching power supply converter packaging structure provided in this embodiment integrates the IPD wafer containing the DTC chip 10 and the SCVR layer containing the SCVR chip 20 through hybrid bonding technology. Among them, the first dielectric layer 12 and the second dielectric layer 22 are in contact and bonded together, and the first metal pads 11 of the DTC chip 10 and the second metal pads 21 of the SCVR chip 20 are in one-to-one contact and bonded together. On the one hand, since the volume of the DTC chip 10 is small, the occupied area of the DTC capacitor in the capacitive switching power supply converter packaging structure can be reduced, the integration degree of the packaging structure can be improved, so that the integrated packaging structure has a small volume and a height as low as the micron level. At the same time, the cost can be reduced. On the other hand, the bonding interface of the packaging structure formed by hybrid bonding has strong bonding properties and less heat generation, which has little impact on the system heat dissipation. It can improve the stability and reliability of the packaging structure. At the same time, it can also shorten the power transmission path, reduce the system power consumption, and thus improve the performance of the capacitive switching power supply converter. On the third hand, the thermal expansion coefficient of the packaging structure matches that of the 2.5D packaging, so that the packaging structure can be integrated into the 2.5D packaging or used alone, improving the application scenarios and application flexibility of the capacitive switching power supply converter packaging structure. Therefore, the capacitive switching power supply converter packaging structure provided in this embodiment can reduce the occupied area of the DTC capacitor, and further reduce the height and volume of the capacitive switching power supply converter packaging structure, improve the integration degree of the packaging structure, reduce the cost, and can also improve the stability and reliability of the packaging structure, improve the performance of the capacitive switching power supply converter, and improve the application scenarios and application flexibility of the capacitive switching power supply converter packaging structure.

[0104] In some alternative embodiments, a first metal lead 51 is further provided on the first surface of the IPD wafer, and each first metal lead 51 is connected to a first metal pad 11 of a DTC chip 10;

[0105] The capacitive switching power supply converter packaging structure further includes:

[0106] A plurality of metal bumps 40 are located on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each metal bump 40 is connected to at least one first metal lead 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal leads 51.

[0107] In specific implementation, the first metal pads 11 of the DTC chip 10 are in one-to-one contact and bonded to the second metal pads 21 of the SCVR chip 20. The first metal lead 51 is connected to the second metal pad 21 by connecting to the first metal pad 11. The first metal lead 51 is used to lead out the relevant control signals of the SCVR chip 20 and the first metal pad 11 of the SCVR chip 20. The metal bumps 40 include but are not limited to Solder ball (solder ball), Bump (bump), and uBump (micro bump). The sizes of the first metal lead 51 and the metal bumps 40 depend on the size of the designed IPD wafer and the SCVR chip 20 as well as the application scenario of the module.

[0108] For the capacitive switching power converter packaging structure provided in this embodiment, by providing the first metal lead 51 and multiple metal bumps 40, the signals of the SCVR chip 20 and the DTC chip 10 can be led out to the external circuit. At the same time, the metal bumps 40 are located on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer, which enables multiple implementation methods for the capacitive switching power converter packaging structure and improves the application flexibility of the capacitive switching power converter packaging structure. The packaging structure can be used alone, in an array, as a single module, or integrated into a 2.5D package, and can be widely used in traditional packaging and advanced packaging. Especially in the IVR technology, it has high application flexibility and meets the future requirements for power supply in chiplet integration.

[0109] In some alternative embodiments, such as Figure 1 shown, the metal bumps 40 are located on the first surface of the IPD wafer and on the side of the SCVR chip 20; the metal bumps 40 are in contact with and connected to the first metal lead 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51.

[0110] For the capacitive switching power converter packaging structure provided in this embodiment, the SCVR chip 20 and the DTC chip 10 are connected together by hybrid bonding. The metal bumps 40 are located on the first surface of the IPD wafer and on the side of the SCVR chip 20. The metal bumps 40 lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, which can simplify the packaging structure, reduce costs, and can shorten the power transmission path, reduce system power consumption, and thus improve the performance of the capacitive switching power converter.

[0111] In some alternative embodiments, such as Figure 2 and Figure 3 shown, the SCVR layer is the SCVR chip 20 or the SCVR wafer; the SCVR wafer includes at least one SCVR chip 20;

[0112] The SCVR layer is provided with an interconnection lead-out structure, and the interconnection lead-out structure includes a second metal lead 52 penetrating the SCVR layer and a third metal lead 53 located on the surface of the SCVR layer on the side facing away from the IPD wafer; the second metal lead 52 is in contact with and connected to the first metal lead 51, and the third metal lead 53 is in contact with and connected to the second metal lead 52;

[0113] The metal bump 40 is located on the surface of the SCVR layer on the side facing away from the IPD wafer, and the metal bump 40 is in contact with and connected to the third metal lead 53; the metal bump 40 is adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53.

[0114] For the capacitive switching power converter packaging structure provided by the present invention, the metal bump 40 is adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53, and the packaging structure can be mounted on the bottom of the substrate or integrated into a 2.5D package, so that there are multiple implementation methods for the capacitive switching power converter packaging structure, which can increase the application scenarios of the packaging structure and improve the application flexibility of the capacitive switching power converter packaging structure.

[0115] In some optional embodiments, as Figure 3 shown, the SCVR layer further includes a third dielectric layer 30, and the third dielectric layer 30 is located on the first surface of the IPD wafer and covers the surface and sides of the SCVR chip 20;

[0116] A first through hole 61 is further provided in the third dielectric layer 30, and the first through hole 61 penetrates the third dielectric layer 30; the second metal lead 52 is located on the inner wall of the first through hole 61.

[0117] In some optional embodiments, a via filling material 60 is further filled on the side of the second metal lead 52 facing away from the inner wall of the first through hole 61. The via filling material 60 is an organic polymer material, such as PI (polyimide), etc.

[0118] In some optional embodiments, the area of the SCVR chip 20 is smaller than the area of the IPD wafer;

[0119] When the SCVR layer is the SCVR chip 20, the material of the third dielectric layer 30 is silicon dioxide;

[0120] When the SCVR layer is the SCVR wafer, the material of the third dielectric layer 30 is silicon.

[0121] In specific implementation, when the SCVR layer is the SCVR chip 20, the third dielectric layer 30 is a silicon dioxide layer deposited on the side of the SCVR chip 20 after hybrid bonding the SCVR layer and the IPD wafer; when the SCVR layer is the SCVR wafer, the third dielectric layer 30 is the structure of the SCVR wafer itself, which is a silicon layer located between the SCVR chips 20.

[0122] In some alternative embodiments, as Figure 4 shown, the area of the SCVR chip 20 is greater than or equal to the area of the IPD wafer;

[0123] The SCVR chip 20 includes a functional area and an edge area surrounding the functional area; the second metal pad 21 is located in the functional area, and the functional area corresponds to the position of the DTC chip 10;

[0124] A second via hole 62 is also provided in the edge area, and the second via hole 62 penetrates the edge area; the second metal lead 52 is located on the inner wall of the second via hole 62.

[0125] In some alternative embodiments, a via hole filling material 60 is further filled on the side of the second metal lead 52 facing away from the inner wall of the second via hole 62. The via hole filling material 60 is an organic polymer material, such as PI, etc.

[0126] In some alternative embodiments, the materials of the first dielectric layer 12 and the second dielectric layer 22 are insulating materials;

[0127] The materials of the first metal pad 11 and the second metal pad 21 are conductive metal materials, including gold, silver, copper, tin, titanium, platinum, etc.;

[0128] The materials of the first metal lead 51, the second metal lead 52, and the third metal lead 53 are conductive metal materials, including gold, silver, copper, tin, titanium, platinum, etc.

[0129] The material of the metal bump 40 is a conductive metal material, including gold, silver, copper, tin, titanium, platinum, etc.

[0130] In some alternative embodiments, the material of the first dielectric layer 12 is silicon dioxide; the material of the second dielectric layer 22 is silicon dioxide;

[0131] The material of the first metal pad 11 is copper; the material of the second metal pad 21 is copper;

[0132] The material of the first metal lead 51 is copper; the material of the second metal lead 52 is copper; the material of the third metal lead 53 is copper;

[0133] The material of the metal bump 40 is copper, tin, or silver.

[0134] In other embodiments, the materials of the first dielectric layer 12 and the second dielectric layer 22 can also be other insulating materials; the materials of the first metal pad 11 and the second metal pad 21 can also be other conductive metal materials. The materials of the first metal lead 51, the second metal lead 52, the third metal lead 53, and the metal bump 40 can also be other conductive metal materials.

[0135] As Figure 4 shown, this embodiment provides a method for fabricating a capacitive switched-mode power converter package structure, and this fabrication method includes but is not limited to steps S101 to S103.

[0136] Step S101: Provide an IPD wafer; the IPD wafer includes a plurality of DTC chips 10 and a first dielectric layer 12 surrounding the DTC chips 10; the surface of each DTC chip 10 includes a plurality of first metal pads 11; the first metal pads 11 are exposed on the first surface of the IPD wafer, as Figure 7 shown.

[0137] Step S102: Provide an SCVR layer, the SCVR layer includes at least one SCVR chip 20; the SCVR chip 20 includes a plurality of second metal pads 21, and a second dielectric layer 22 located on the side of the second metal pads 21, and the second metal pads 21 and the second dielectric layer 22 are located on the side surface of the SCVR layer facing the IPD wafer.

[0138] In specific implementation, in some embodiments, the SCVR layer is an SCVR chip 20, as Figure 8 shown; in other embodiments, the SCVR layer is an SCVR wafer, as Figure 17 and Figure 23 shown, the SCVR wafer includes at least one SCVR chip 20. The form of the SCVR mainly affects the implementation manner of the capacitive switched-mode power converter package structure, but does not affect the final structure.

[0139] Step S103: Connect the IPD wafer and the SCVR layer into an integrated structure through hybrid bonding, wherein each SCVR chip 20 is connected to at least two DTC chips 10; the first dielectric layer 12 contacts and is bonded to the second dielectric layer 22, and the first metal pads 11 and the second metal pads 21 are in contact and bonded to each other one by one.

[0140] In specific implementation, connect the IPD wafer and the SCVR layer into an integrated structure through W2W (Wafer to Wafer) hybrid bonding or C2W (Chip to Wafer) hybrid bonding. When the SCVR layer is an SCVR chip 20, C2W hybrid bonding is performed between the SCVR chip 20 and the IPD wafer, as Figure 9As shown; when the SCVR layer is an SCVR wafer, the SCVR wafer includes at least one SCVR chip 20, and a W2W hybrid bonding is performed between the SCVR wafer and the IPD wafer, as Figure 18 and Figure 24 shown. In some embodiments, the IPD wafer and the SCVR layer are hybrid-bonded by thermocompression bonding.

[0141] The preparation method of the capacitive switching power converter packaging structure provided in this embodiment integrates the IPD wafer containing the DTC chip 10 and the SCVR layer containing the SCVR chip 20 through a hybrid bonding technology. On the one hand, it can reduce the occupied area of the DTC capacitor, thereby reducing the height and volume of the capacitive switching power converter packaging structure, improving the integration degree of the packaging structure, and at the same time, it can simplify the process flow and reduce the process cost; on the second hand, the bonding interface formed by hybrid bonding has strong bonding properties, which can improve the stability and reliability of the packaging structure, and can also shorten the power transmission path, reduce the system power consumption, thereby improving the performance of the capacitive switching power converter, and at the same time improving the application scenarios and application flexibility of the capacitive switching power converter packaging structure.

[0142] In some alternative embodiments, a first metal lead 51 is further provided on the first surface of the IPD wafer, and each first metal lead 51 is connected to a first metal pad 11 of a DTC chip 10;

[0143] After the step of connecting the IPD wafer and the SCVR layer into an integrated structure through hybrid bonding, the following steps are further included:

[0144] Forming a plurality of metal bumps 40 on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each metal bump 40 is connected to at least one first metal lead 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal leads 51.

[0145] In some alternative embodiments, the step of forming a plurality of metal bumps 40 includes:

[0146] Forming a plurality of metal bumps 40 on the first surface of the IPD wafer on the side of the SCVR chip 20; the metal bumps 40 are in contact with and connected to the first metal leads 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal leads 51.

[0147] In some alternative embodiments, the SCVR layer is an SCVR chip 20 or an SCVR wafer; the SCVR wafer includes at least one SCVR chip 20;

[0148] Before the step of forming a plurality of metal bumps 40, the following steps are further included:

[0149] Form an interconnection lead-out structure in the SCVR layer; the interconnection lead-out structure includes a second metal lead 52 penetrating the SCVR layer and a third metal lead 53 located on the surface of the side of the SCVR layer facing away from the IPD wafer; the second metal lead 52 contacts and connects with the first metal lead 51, and the third metal lead 53 contacts and connects with the second metal lead 52;

[0150] Form metal bumps 40 on the surface of the side of the SCVR layer facing away from the IPD wafer, and the metal bumps 40 contact and connect with the third metal lead 53; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53.

[0151] In some alternative embodiments, the SCVR layer further includes a third dielectric layer 30, and the third dielectric layer 30 is located on the first surface of the IPD wafer and covers the surface and sides of the SCVR chip 20;

[0152] Before the step of forming the interconnection lead-out structure, it further includes:

[0153] Form a first through hole 61 in the third dielectric layer 30, and the first through hole 61 penetrates the third dielectric layer 30;

[0154] The step of forming the interconnection lead-out structure includes:

[0155] Form a second metal lead 52 on the inner wall of the first through hole 61, and the second metal lead 52 contacts and connects with the first metal lead 51;

[0156] Form a third metal lead 53 on the surface of the side of the third dielectric layer 30 facing away from the IPD wafer, and the third metal lead 53 contacts and connects with the second metal lead 52.

[0157] In some alternative embodiments, the SCVR layer is the SCVR chip 20; the area of the SCVR chip 20 is smaller than the area of the IPD wafer;

[0158] Before the step of forming the first through hole 61 in the third dielectric layer 30, it further includes:

[0159] Form a third dielectric layer 30 on the first surface of the IPD wafer on the side of the SCVR chip 20; the third dielectric layer 30 covers the sides and surface of the SCVR chip 20;

[0160] The material of the third dielectric layer 30 is silicon dioxide.

[0161] In some alternative embodiments, the area of the SCVR chip 20 is greater than or equal to the area of the IPD wafer;

[0162] The SCVR chip 20 includes a functional area and an edge area; the second metal pad 21 is located in the functional area, and the functional area corresponds to the position of the DTC chip 10;

[0163] Before the step of forming the interconnection lead-out structure, it further includes:

[0164] Form a second through-hole 62 in the edge area, and the second through-hole 62 penetrates the edge area;

[0165] The step of forming the interconnection lead-out structure includes:

[0166] Form a second metal lead 52 on the inner wall of the second through-hole 62, and the second metal lead 52 contacts and connects with the first metal lead 51;

[0167] Form a third metal lead 53 on the surface of the edge area facing away from the IPD wafer, and the third metal lead 53 contacts and connects with the second metal lead 52.

[0168] As Figure 5 shown, the present invention also provides a specific process schematic diagram of a preparation method for a capacitive switching power converter packaging structure, including the following steps:

[0169] Step S201, provide an IPD wafer; the IPD wafer includes a plurality of DTC chips 10 and a first dielectric layer 12 surrounding the DTC chips 10; each DTC chip 10 surface includes a plurality of first metal pads 11; the first metal pads 11 are exposed on the first surface of the IPD wafer; a first metal lead 51 is also provided on the first surface of the IPD wafer, and each first metal lead 51 connects a first metal pad 11 of a DTC chip 10, as Figure 7 shown.

[0170] Step S202, provide an SCVR layer, the SCVR layer includes at least one SCVR chip 20; the SCVR chip 20 includes a plurality of second metal pads 21, and a second dielectric layer 22 located on the side of the second metal pads 21, the second metal pads 21 and the second dielectric layer 22 are located on the surface of the SCVR layer facing the IPD wafer, as Figure 8 、 Figure 17 and Figure 23 shown.

[0171] Step S203, connect the IPD wafer and the SCVR layer into an integrated structure by hybrid bonding, wherein each SCVR chip 20 is connected to at least two DTC chips 10; the first dielectric layer 12 contacts and is bonded to the second dielectric layer 22 together, and the first metal pads 11 and the second metal pads 21 contact and are bonded to each other one by one, as Figure 9 、 Figure 18 and Figure 24 shown.

[0172] Step S204, form a plurality of metal bumps 40 on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each metal bump 40 is connected to at least one first metal lead 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal leads 51, as Figure 10 , Figure 15 , Figure 21 and Figure 27 shown.

[0173] The present invention also provides two specific implementation manners of Example 1, Example 2, Example 3 and Example 4, respectively preparing and forming capacitive switching power converter packaging structures with different structural forms, which are suitable for different packaging application scenarios. Among them, the SCVR layer in Example 1 and Example 2 is the SCVR chip 20, and a C2W (Chip to Wafer) hybrid bonding is performed between the SCVR chip 20 and the IPD wafer; the SCVR layer in Example 3 and Example 4 is the SCVR wafer, the SCVR wafer includes at least one SCVR chip 20, and a W2W (Wafer to Wafer) hybrid bonding is performed between the SCVR wafer and the IPD wafer.

[0174] Figure 6 FIG. 17 is a schematic flow chart of a preparation method of the capacitive switching power converter packaging structure provided for Example 1, including but not limited to steps S301 to S304.

[0175] Step S301 is the same as step S201 and will not be described herein again.

[0176] Step S302, provide an SCVR layer, the SCVR layer is the SCVR chip 20; the SCVR chip 20 includes a plurality of second metal pads 21 and a second dielectric layer 22 located on the side of the second metal pads 21, and the second metal pads 21 and the second dielectric layer 22 are located on the surface of the SCVR layer facing the IPD wafer; the area of the SCVR chip 20 is smaller than the area of the IPD wafer, as Figure 8 shown.

[0177] Step S303, connect the IPD wafer and the SCVR chip 20 into an integrated structure through hybrid bonding, wherein each SCVR chip 20 is connected to at least two DTC chips 10; the first dielectric layer 12 and the second dielectric layer 22 are in contact and bonded together, and the first metal pads 11 and the second metal pads 21 are in contact and bonded together one by one, as Figure 9 shown.

[0178] Step S304, form a plurality of metal bumps 40 on the first surface of the IPD wafer on the side of the SCVR chip 20; the metal bumps 40 are in contact with and connected to the first metal lead 51; the metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, as Figure 10 shown.

[0179] For the manufacturing method of the capacitive switching power supply converter packaging structure provided in Example 1, the SCVR layer is the SCVR chip 20, and C2W hybrid bonding is performed between the SCVR chip 20 and the IPD wafer; after the hybrid bonding, a plurality of metal bumps 40 are formed on the first surface of the IPD wafer on the side of the SCVR chip 20, and the metal bumps 40 are in contact with and connected to the first metal lead 51. The packaging structure leads out the signals of the SCVR chip 20 and the DTC chip 10 through the metal bumps 40 and the first metal lead 51.

[0180] Figure 11 FIG. is a schematic flow chart of the manufacturing method of the capacitive switching power supply converter packaging structure provided in Example 2, including but not limited to steps S401 to S408.

[0181] Steps S401 to S403 are the same as steps S301 to S303, and will not be elaborated here.

[0182] Step S404, form a third dielectric layer 30 on the first surface of the IPD wafer on the side of the SCVR chip 20; the third dielectric layer 30 covers the side and surface of the SCVR chip 20; the material of the third dielectric layer 30 is silicon dioxide, as Figure 12 shown.

[0183] Specifically, the third dielectric layer 30 is formed on the first surface of the IPD wafer on the side of the SCVR chip 20 through a CVD (chemical vapor deposition) process.

[0184] Step S405, form a first through hole 61 in the third dielectric layer 30, and the first through hole 61 penetrates through the third dielectric layer 30, as Figure 13 shown.

[0185] Specifically, the first through hole 61 is formed in the third dielectric layer 30 through an etching process.

[0186] Step S406, form a second metal lead 52 on the inner wall of the first through hole 61, and the second metal lead 52 is in contact with and connected to the first metal lead 51; the second metal lead 52 penetrates through the third dielectric layer 30, as Figure 14 shown.

[0187] Step S407: Form a third metal lead 53 on the surface of the third dielectric layer 30 facing away from the IPD wafer. The third metal lead 53 contacts and connects with the second metal lead 52. The second metal lead 52 and the third metal lead 53 form an interconnection lead-out structure, as Figure 15 shown.

[0188] Step S408: Form metal bumps 40 on the surface of the SCVR layer facing away from the IPD wafer. The metal bumps 40 contact and connect with the third metal lead 53. The metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53, as Figure 15 shown.

[0189] For the manufacturing method of the capacitive switching power supply converter packaging structure provided in Example 2, the SCVR layer is the SCVR chip 20, and C2W hybrid bonding is performed between the SCVR chip 20 and the IPD wafer. After C2W hybrid bonding, first, form a third dielectric layer 30 on the first surface of the IPD wafer on the side of the SCVR chip 20 by CVD process, then form a first through-hole 61 in the third dielectric layer 30 by etching process, and form a second metal lead 52 in the first through-hole 61. At the same time, fill the first through-hole 61 with a via filling material 60, and finally form the third metal lead 53 and the metal bumps 40. The packaging structure leads out the signals of the SCVR chip 20 and the DTC chip 10 through the metal bumps 40, the first metal lead 51, the second metal lead 52, and the third metal lead 53.

[0190] Figure 16 FIG. is a schematic flow chart of the manufacturing method of the capacitive switching power supply converter packaging structure provided in Example 3, including but not limited to steps S501 to S507.

[0191] Step S501 is the same as step S201 and will not be elaborated here.

[0192] Step S502: Provide an SCVR layer. The SCVR layer is an SCVR wafer, which includes at least one SCVR chip 20 and a third dielectric layer 30. The third dielectric layer 30 covers the side and surface of the SCVR chip 20. The SCVR chip 20 includes a plurality of second metal pads 21 and a second dielectric layer 22 located on the side of the second metal pads 21. The second metal pads 21 and the second dielectric layer 22 are located on the surface of the SCVR layer facing the IPD wafer. The area of the SCVR chip 20 is smaller than the area of the IPD wafer. The material of the third dielectric layer 30 is silicon, as Figure 17 shown.

[0193] Step S503: Connect the IPD wafer and the SCVR wafer into an integrated structure through hybrid bonding. Each SCVR chip 20 is connected to at least two DTC chips 10. The first dielectric layer 12 contacts and is bonded to the second dielectric layer 22, and the first metal pad 11 and the second metal pad 21 contact and are bonded to each other one by one, as Figure 18 shown.

[0194] Step S504: Form a first through-hole 61 in the third dielectric layer 30. The first through-hole 61 penetrates the third dielectric layer 30, as Figure 19 shown.

[0195] Step S505: Form a second metal lead 52 on the inner wall of the first through-hole 61. The second metal lead 52 contacts and is connected to the first metal lead 51. The second metal lead 52 penetrates the SCVR wafer, as Figure 20 shown.

[0196] Step S506: Form a third metal lead 53 on the surface of the third dielectric layer 30 facing away from the IPD wafer. The third metal lead 53 contacts and is connected to the second metal lead 52. The second metal lead 52 and the third metal lead 53 form an interconnection lead-out structure, as Figure 21 shown.

[0197] Step S507: Form metal bumps 40 on the surface of the SCVR wafer facing away from the IPD wafer. The metal bumps 40 contact and are connected to the third metal lead 53. The metal bumps 40 are adapted to lead out the signals of the SCVR chips 20 and the DTC chips 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53, as Figure 21 shown.

[0198] For the manufacturing method of the capacitive switching power converter packaging structure provided in Example 3, the SCVR layer is the SCVR wafer. The SCVR wafer includes at least one SCVR chip 20 and a third dielectric layer 30 (silicon layer) located on the side of the SCVR chip 20. The area of the SCVR chip 20 is smaller than that of the IPD wafer. W2W hybrid bonding is performed between the SCVR wafer and the IPD wafer. After W2W hybrid bonding, first, a first through-hole 61 is formed in the third dielectric layer 30 of the SCVR wafer through a wet etching process, and a second metal lead 52 is formed in the first through-hole 61. At the same time, the first through-hole 61 is filled with a via filling material 60, and then the third metal lead 53 and the metal bumps 40 are formed. The packaging structure leads out the signals of the SCVR chips 20 and the DTC chips 10 through the metal bumps 40, the first metal lead 51, the second metal lead 52, and the third metal lead 53.

[0199] Figure 22Schematic diagram of the specific process for preparing the capacitive switching power supply converter package structure provided for Example 4, including but not limited to steps S601 to S607.

[0200] Step S601 is the same as step S201 and will not be elaborated here.

[0201] Step S602: Provide an SCVR layer. The SCVR layer is an SCVR wafer, and the SCVR wafer includes at least one SCVR chip 20. The SCVR chip 20 includes a plurality of second metal pads 21 and a second dielectric layer 22 located on the side of the second metal pads 21. The second metal pads 21 and the second dielectric layer 22 are located on one surface of the SCVR layer facing the IPD wafer. The area of the SCVR chip 20 is equal to the area of the IPD wafer. The SCVR chip 20 includes a functional area and an edge area. The second metal pads 21 are located in the functional area, and the functional area corresponds to the position of the DTC chip 10, as Figure 23 shown.

[0202] Step S603: Connect an IPD wafer and one SCVR chip 20 in the SCVR wafer into an integrated structure through hybrid bonding. Among them, the SCVR chip 20 is connected to at least two DTC chips 10. The first dielectric layer 12 and the second dielectric layer 22 are in contact and bonded together, and the first metal pads 11 and the second metal pads 21 are in one-to-one contact and bonded together, as Figure 24 shown.

[0203] Step S604: Form a second via hole 62 in the edge area of the SCVR chip 20. The second via hole 62 penetrates the edge area, as Figure 25 shown.

[0204] Step S605: Form a second metal lead 52 on the inner wall of the second via hole 62. The second metal lead 52 is in contact and connected with the first metal lead 51. The second metal lead 52 penetrates the edge area of the SCVR chip 20, as Figure 26 shown.

[0205] Step S606: Form a third metal lead 53 on the surface of the edge area of the SCVR chip 20 facing away from the IPD wafer. The third metal lead 53 is in contact and connected with the second metal lead 52. The second metal lead 52 and the third metal lead 53 form an interconnection lead-out structure, as Figure 26 shown.

[0206] Step S607: Form metal bumps 40 on the surface of the SCVR chip 20 facing away from the IPD wafer. The metal bumps 40 are in contact with and connected to the third metal lead 53. The metal bumps 40 are adapted to lead out the signals of the SCVR chip 20 and the DTC chip 10 through the first metal lead 51, the second metal lead 52, and the third metal lead 53, as Figure 27 shown.

[0207] For the method for preparing the capacitive switching power supply converter packaging structure provided in Example 4, the SCVR layer is an SCVR wafer, the SCVR wafer includes at least one SCVR chip 20, and the area of the SCVR chip 20 is equal to the area of the IPD wafer; the SCVR chip 20 includes a functional area and an edge area; the second metal pad 21 is located in the functional area, and the functional area corresponds to the position of the DTC chip 10, and W2W hybrid bonding is performed between the SCVR wafer and the IPD wafer. After W2W hybrid bonding, first use the VIA LAST (post-drilling) technology to form a second through-hole 62 at the reserved position in the edge area of the SCVR chip 20, and form a second metal lead 52 on the inner wall of the second through-hole 62. At the same time, fill the second through-hole 62 with a through-hole filling material 60, and then form a third metal lead 53 and metal bumps 40. The packaging structure leads out the signals of the SCVR chip 20 and the DTC chip 10 through the metal bumps 40, the first metal lead 51, the second metal lead 52, and the third metal lead 53.

[0208] In the description of this specification, the descriptions referring to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0209] In the above description, no detailed explanations are given for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shapes. Additionally, to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be advantageously combined and used.

[0210] The above are only the preferred embodiments of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the above specific embodiments, and various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the protection scope of the present invention is determined by the scope of the appended claims.

Claims

1. A capacitive switching power supply converter packaging structure, characterized in that, Comprising: An IPD wafer, including a plurality of DTC chips and a first dielectric layer surrounding the DTC chips; The surface of each of the DTC chips includes a plurality of first metal pads; the first metal pads are exposed on the first surface of the IPD wafer; An SCVR layer, located on the first surface of the IPD wafer, the SCVR layer includes at least one SCVR chip; the SCVR chip includes a plurality of second metal pads and a second dielectric layer located on the side of the second metal pads, the second metal pads and the second dielectric layer are located on the side surface of the SCVR layer facing the IPD wafer; The IPD wafer and the SCVR layer are connected into an integrated structure by hybrid bonding, wherein each SCVR chip is connected to at least two of the DTC chips; the first dielectric layer and the second dielectric layer are in contact and bonded together, and the first metal pads and the second metal pads are in one-to-one correspondence contact and bonded together.

2. The capacitive switching power converter packaging structure according to claim 1, wherein A first metal lead is further provided on the first surface of the IPD wafer, and each first metal lead is connected to the first metal pad of one of the DTC chips; The capacitive switching power converter packaging structure further includes: A plurality of metal bumps, located on the first surface of the IPD wafer or on the side surface of the SCVR layer facing away from the IPD wafer; each metal bump is connected to at least one of the first metal leads; the metal bumps are adapted to lead out the signals of the SCVR chips and the DTC chips through the first metal leads.

3. The capacitive switching power converter packaging structure according to claim 2, wherein The metal bumps are located on the first surface of the IPD wafer and on the side of the SCVR chip; the metal bumps are in contact and connected with the first metal leads; the metal bumps are adapted to lead out the signals of the SCVR chips and the DTC chips through the first metal leads.

4. The capacitive switching power converter packaging structure according to claim 2, wherein The SCVR layer is an SCVR chip or an SCVR wafer; the SCVR wafer includes at least one SCVR chip; The SCVR layer is provided with an interconnection lead-out structure, the interconnection lead-out structure includes a second metal lead penetrating through the SCVR layer and a third metal lead located on the side surface of the SCVR layer facing away from the IPD wafer; the second metal lead is in contact and connected with the first metal lead, and the third metal lead is in contact and connected with the second metal lead; The metal bumps are located on the side surface of the SCVR layer facing away from the IPD wafer, and the metal bumps are in contact and connected with the third metal leads; the metal bumps are adapted to lead out the signals of the SCVR chips and the DTC chips through the first metal leads, the second metal leads, and the third metal leads.

5. The capacitive switching power supply converter package structure according to claim 4, wherein the SCVR layer further includes a third dielectric layer, the third dielectric layer is located on the first surface of the IPD wafer and covers the surface and sides of the SCVR chip; a first through hole is further provided in the third dielectric layer, and the first through hole penetrates through the third dielectric layer; the second metal lead is located on the inner wall of the first through hole.

6. The capacitive switching power supply converter package structure according to claim 5, wherein the area of the SCVR chip is smaller than the area of the IPD wafer; when the SCVR layer is an SCVR chip, the material of the third dielectric layer is silicon dioxide; when the SCVR layer is an SCVR wafer, the material of the third dielectric layer is silicon.

7. The capacitive switching power supply converter package structure according to claim 4, wherein the area of the SCVR chip is greater than or equal to the area of the IPD wafer; the SCVR chip includes a functional area and an edge area surrounding the functional area; the second metal pad is located in the functional area, and the functional area corresponds to the position of the DTC chip; a second through hole is further provided in the edge area, and the second through hole penetrates through the edge area; the second metal lead is located on the inner wall of the second through hole.

8. The capacitive switching power supply converter package structure according to claim 2, wherein the material of the first dielectric layer is silicon dioxide; the material of the second dielectric layer is silicon dioxide; the material of the first metal pad is copper; the material of the second metal pad is copper; the material of the first metal lead is copper.

9. A preparation method of a capacitive switching power supply converter packaging structure, characterized in that, Comprising: providing an IPD wafer; the IPD wafer includes a plurality of DTC chips and a first dielectric layer surrounding the DTC chips; each surface of the DTC chip includes a plurality of first metal pads; the first metal pads are exposed on the first surface of the IPD wafer; providing an SCVR layer, the SCVR layer includes at least one SCVR chip; the SCVR chip includes a plurality of second metal pads and a second dielectric layer located on the side of the second metal pads, and the second metal pads and the second dielectric layer are located on one surface of the SCVR layer facing the IPD wafer; bonding the IPD wafer and the SCVR layer together into an integrated structure by hybrid bonding, wherein each SCVR chip is connected to at least two of the DTC chips; the first dielectric layer and the second dielectric layer are in contact and bonded together, and the first metal pads and the second metal pads are in one-to-one correspondence and bonded together.

10. The method for preparing the capacitive switching power supply converter package structure according to claim 9, wherein a first metal lead is further provided on the first surface of the IPD wafer, and each first metal lead is connected to the first metal pad of one DTC chip; after the step of bonding the IPD wafer and the SCVR layer together into an integrated structure by hybrid bonding, further includes: Form a plurality of metal bumps on the first surface of the IPD wafer or on the surface of the SCVR layer facing away from the IPD wafer; each of the metal bumps is connected to at least one of the first metal leads; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads.

11. The method for preparing a capacitive switching power supply converter packaging structure according to claim 10, wherein the step of forming a plurality of metal bumps includes: Form a plurality of the metal bumps on the first surface of the IPD wafer on the side of the SCVR chip; the metal bumps are in contact with and connected to the first metal leads; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads.

12. The method for preparing a capacitive switching power supply converter packaging structure according to claim 10, wherein the SCVR layer is an SCVR chip or an SCVR wafer; the SCVR wafer includes at least one SCVR chip; before the step of forming a plurality of metal bumps, further include: Form an interconnection lead-out structure in the SCVR layer; the interconnection lead-out structure includes a second metal lead penetrating through the SCVR layer and a third metal lead located on the surface of the SCVR layer facing away from the IPD wafer; the second metal lead is in contact with and connected to the first metal lead, and the third metal lead is in contact with and connected to the second metal lead; Form the metal bumps on the surface of the SCVR layer facing away from the IPD wafer, and the metal bumps are in contact with and connected to the third metal leads; the metal bumps are adapted to lead out the signals of the SCVR chip and the DTC chip through the first metal leads, the second metal leads, and the third metal leads.

13. The method for preparing a capacitive switching power supply converter packaging structure according to claim 12, wherein the SCVR layer further includes a third dielectric layer, which is located on the first surface of the IPD wafer and covers the surface and sides of the SCVR chip; before the step of forming the interconnection lead-out structure, further include: Form a first through hole in the third dielectric layer, and the first through hole penetrates through the third dielectric layer; the step of forming the interconnection lead-out structure includes: Form a second metal lead on the inner wall of the first through hole, and the second metal lead is in contact with and connected to the first metal lead; Form a third metal lead on the surface of the third dielectric layer facing away from the IPD wafer, and the third metal lead is in contact with and connected to the second metal lead.

14. The method for preparing a capacitive switching power supply converter packaging structure according to claim 13, wherein the SCVR layer is an SCVR chip; the area of the SCVR chip is smaller than the area of the IPD wafer; before the step of forming the first through hole in the third dielectric layer, further include: Form the third dielectric layer on the first surface of the IPD wafer on the side of the SCVR chip; the third dielectric layer covers the side and surface of the SCVR chip; The material of the third dielectric layer is silicon dioxide.

15. The method for manufacturing a capacitive switching power converter packaging structure according to claim 12, wherein, The area of the SCVR chip is greater than or equal to the area of the IPD wafer; The SCVR chip includes a functional area and an edge area; the second metal pad is located in the functional area, and the functional area corresponds to the position of the DTC chip; Before the step of forming the interconnecting lead-out structure, it further includes: Form a second through hole in the edge area, and the second through hole penetrates the edge area; The step of forming the interconnecting lead-out structure includes: Form a second metal lead on the inner wall of the second through hole, and the second metal lead contacts and connects with the first metal lead; Form a third metal lead on the surface of the edge area facing away from the IPD wafer, and the third metal lead contacts and connects with the second metal lead.

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