Vertical D-MOSFET with trench isolation and improved channel structure and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a vertical D-MOSFET with trench isolation and improved channel structure and a preparation method thereof. Background Art

[0002] Unlike the lateral current path of traditional planar MOSFET, the source, gate and drain of vertical D-MOSFET are stacked in the vertical direction, and the current flows longitudinally from the surface source to the bottom drain. Trench isolation is to etch deep trenches on the silicon substrate and fill them with insulating materials such as silicon dioxide (SiO2) or polysilicon.

[0003] The existing patent discloses an air gap isolation structure of a trench MOSFET and a manufacturing method thereof (publication number CN115966463A), the manufacturing method comprising: forming a trench extending from the upper surface of an epitaxial layer of a first doping type to the inside thereof; forming a second dielectric layer in the trench, the second dielectric layer comprising a first portion covering the top sidewall of the trench and a second portion located below the first portion; forming a gate conductor in a cavity formed by the second dielectric layer around the trench. In the technology disclosed in the patent, the electric field will gather at the edge due to the design of the gate, and the trench isolation structure does not adequately suppress the parasitic capacitance, and the carrier migration path is not fully optimized, which limits the voltage withstand capability and dynamic performance of the device. Summary of the invention

[0004] The present invention provides a vertical D-MOSFET with trench isolation and improved channel structure and a preparation method to solve the existing technical problems, and solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a vertical D-MOSFET with trench isolation and improved channel structure is provided, comprising a plurality of MOS cells arranged in parallel, wherein a single MOS cell comprises a drain, a source, a gate, a gate oxide layer and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer, wherein the cross-sectional profile of the gate is triangular, and a polysilicon capping layer is deposited at the junction of the gate and the gate oxide layer; and the cross-sectional profile of the gate oxide layer is semi-elliptical.

[0006] Furthermore, the cross-sectional profile of the polysilicon cover layer is triangular, wherein extension layers are deposited at the edges on both sides of the polysilicon cover layer.

[0007] Furthermore, the material of the extension layer is titanium nitride or tantalum nitride.

[0008] Further, the gate further includes a comb-shaped gate, where the comb-shaped gate includes seven longitudinal teeth and a transverse beam for connecting the seven longitudinal teeth.

[0009] Further, a lower convex gate is formed downward by ion implantation at the junction of the N substrate layer and the N diffusion layer, where the cross-sectional height of the lower convex gate in the middle of a single MOS cell is higher than that at both sides.

[0010] Further, an upper concave gate is formed upward by ion implantation at the junction of the N substrate layer and the N diffusion layer, where the cross-sectional height of the upper concave gate in the middle of a single MOS cell is lower than that at both sides.

[0011] Further, a field oxide layer is deposited at the junction of the drain and the N substrate layer in the middle of a single MOS cell.

[0012] Further, both the lower convex gate and the upper concave gate are formed into a P-type structure layer by implanting boron elements.

[0013] A preparation method of a vertical D-MOSFET with trench isolation and an improved channel structure, the specific steps include: S1. Based on the N substrate layer, an N diffusion layer, a P+ layer, a P well layer and an N well layer are sequentially formed by epitaxial growth technology; S2. Deep trenches are etched on the surface of the semiconductor epitaxial layer, and silicon dioxide is filled to form a trench isolation structure; S3. A gate with a triangular cross-sectional profile is formed in the gate region by photolithography and dry etching processes, and the cross-sectional shape of the gate oxide layer is controlled to be semi-elliptical; S4. A polysilicon overlay is deposited at the junction of the gate and the gate oxide layer, and its cross-sectional profile is made triangular by etching process; S5. Titanium nitride or tantalum nitride material is deposited on both side edges of the polysilicon overlay to form an extension layer; S6. An upper concave gate with a low middle and high sides is formed by tilting the ion implantation of boron elements upward; S7. In the middle region of a single MOS cell, a field oxide layer is deposited at the junction of the drain and the N substrate layer.

[0014] A vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method provided by the present invention. Compared with the prior art, the effects obtained by this method are: 1. By designing the cross-sectional profile of the gate as triangular and controlling the gate oxide layer to be semi-elliptical, the electric field distribution and the carrier migration path are optimized. The triangular gate can reduce the electric field concentration at the gate edge and reduce the breakdown risk.

[0015] 2. The present invention enhances the electric field uniformity in the channel region by designing a semi-elliptical gate oxide layer, thereby reducing the on-resistance and increasing the switching speed. Moreover, this structure significantly improves the current driving ability and reliability of the device.

[0016] 3. The present invention enhances the mechanical stability of the gate structure through a polysilicon capping layer. The high conductivity of the extension layer reduces the contact resistance, while the chemical inertness of the nitride inhibits interface oxidation, thereby reducing leakage current and improving the high-temperature stability of the device.

[0017] 4. The present invention forms a downwardly convex gate at the junction of the N substrate and the N diffusion layer by ion implantation, creating a gradient doping in the vertical direction, enhancing the longitudinal migration efficiency of carriers. Meanwhile, the middle high-convex region can disperse the electric field intensity, reducing the probability of local breakdown, thereby improving the breakdown voltage capability and on-conduction uniformity of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the first embodiment of the present invention; Figure 2 It is a schematic diagram of the second embodiment of the present invention; Figure 3 It is a schematic diagram of the third embodiment of the present invention; Figure 4 It is a schematic diagram of the fourth embodiment of the present invention; Figure 5 It is a schematic diagram of the fifth embodiment of the present invention; Figure 6 It is a schematic diagram of the sixth embodiment of the present invention.

[0019] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Polysilicon capping layer; 5. Gate oxide layer; 6. N substrate layer; 7. N diffusion layer; 8. P+ layer; 9. P well layer; 10. N well layer; 11. Extension layer; 12. Downwardly convex gate; 13. Upwardly concave gate; 14. Field oxide layer; 31. Comb-shaped gate. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0021] As Figure 1-6 shown, a preparation method of a vertical D-MOSFET with trench isolation and an improved channel structure specifically includes the following steps: Step 1: Based on the N substrate layer 6, sequentially form an N diffusion layer 7, a P+ layer 8, a P well layer 9, and an N well layer 10 through epitaxial growth technology; grow the N diffusion layer, P+ layer, P well layer, and N well layer layer by layer on the N-type substrate through epitaxial growth technology, precisely control the doping concentration and thickness of each layer, and form a multi-layer doped structure in the vertical direction. The N diffusion layer 7 is used to construct a low-resistance current path, the P+ layer 8 provides high-concentration hole injection, and the P well layer 9 and N well layer 10 form a PN junction to optimize the carrier migration path. And through layer-by-layer epitaxial growth, ensure the precise matching of each doped region, reduce the resistance of the vertical current path, improve the carrier migration efficiency, thereby enhancing the on-state ability and current density of the device.

[0022] Step 2: Etch deep trenches on the surface of the semiconductor epitaxial layer and fill them with silicon dioxide to form a trench isolation structure; use deep reactive ion etching (DRIE) technology to form deep trenches on the surface of the epitaxial layer, and then fill them with silicon dioxide insulating material to achieve physical isolation between adjacent MOS cells. The high insulation of silicon dioxide can effectively block the lateral leakage current. And the deep trench isolation greatly reduces the parasitic capacitance and crosstalk between cells, improves the breakdown voltage and device integration, and at the same time enhances the breakdown voltage stability, suitable for high-power application scenarios.

[0023] Step 3: Form a gate 3 with a triangular cross-sectional profile in the gate region through photolithography and dry etching processes, and control the cross-sectional shape of the gate oxide layer 5 to be semi-elliptical; use a photolithography mask to define the gate region, form a gate structure with a triangular cross-section through dry etching (such as plasma etching), and control the gate oxide layer 5 to be semi-elliptical through an oxidation process. The edge of the triangular gate 3 is smooth, and the thickness of the semi-elliptical oxide layer 5 has a gradient distribution. And the triangular gate 3 reduces the edge concentration of the electric field and reduces the breakdown risk; the semi-elliptical gate oxide layer 5 optimizes the electric field uniformity in the channel region, reduces the on-resistance and improves the switching speed, significantly enhancing the dynamic performance of the device.

[0024] Step 4: Deposit a polysilicon capping layer 4 at the junction of the gate 3 and the gate oxide layer 5, and make its cross-sectional profile triangular through an etching process; use chemical vapor deposition (CVD) to deposit a polysilicon layer at the interface between the gate 3 and the gate oxide layer 5, and form a triangular cross-section through anisotropic etching. The polysilicon capping layer 4 fills the interface gap and improves the interface contact. And enhance the mechanical stability of the gate structure, reduce the interface contact resistance; the triangular cross-section further optimizes the electric field distribution, suppresses the gate edge leakage current, and improves the high-temperature operation reliability.

[0025] Step Five: Deposit titanium nitride or tantalum nitride material on both side edges of the polysilicon capping layer 4 to form the extension layer 11; deposit highly conductive titanium nitride (TiN) or tantalum nitride (TaN) material on both side edges of the polysilicon capping layer 4 through physical vapor deposition (PVD) to form the extension layer 11. The nitride material has high chemical stability and low resistance characteristics. And the extension layer reduces the contact resistance between the gate and the source / drain, improving the current transmission efficiency; the chemical inertness of the nitride inhibits interface oxidation, reducing leakage current and enhancing the high-temperature tolerance of the device.

[0026] Step Six: Form an upper concave gate 13 with a low middle and high sides by ion-implanting boron element with an upward tilt; adopt the tilted ion-implantation technique to implant boron element at a specific angle at the junction of the N substrate layer 6 and the N diffusion layer 7 to form a P-type upper concave gate 13 structure with a low doping concentration in the middle and high concentrations on both sides. And the low-doped middle region alleviates the electric field crowding near the drain, reducing the leakage current; the high-doped regions on both sides enhance the control force of the gate on the channel, improving the switching response speed, and at the same time improving the dynamic characteristics and breakdown voltage ability.

[0027] Step Seven: Deposit a field oxide layer 14 at the junction of the drain 1 and the N substrate layer 6 in the middle region of a single MOS cell. Grow a field oxide layer 14 (SiO2) in the middle region at the junction of the drain and the N substrate layer 6 through local oxidation of silicon (LOCOS) to provide lateral isolation and cover the potential parasitic capacitance region. And the field oxide layer 14 inhibits the parasitic capacitance and leakage current between the drain and the substrate, optimizing the high-frequency performance; acting in cooperation with the upper concave gate 13 structure, dispersing the electric field intensity, improving the breakdown voltage stability and high-frequency response efficiency of the device.

[0028] Example 1 As Figure 1 shown, according to one aspect of the present invention, a vertical D-MOSFET with trench isolation and an improved channel structure is provided, which is composed of a plurality of juxtaposed MOS cells. A single MOS cell includes a drain 1, a source 2, a gate 3, a gate oxide layer 5, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 6, an N diffusion layer 7, a P+ layer 8, a P well layer 9, and an N well layer 10. The cross-sectional profile of the gate 3 is triangular, and a polysilicon capping layer 4 is deposited at the junction of the gate 3 and the gate oxide layer 5; the cross-sectional profile of the gate oxide layer 5 is semi-elliptical. By designing the cross-sectional profile of the gate 3 as triangular and controlling the gate oxide layer 5 to be semi-elliptical, the electric field distribution and the carrier migration path are optimized. The triangular gate 3 can reduce the electric field concentration at the edge of the gate 3, reducing the breakdown risk, while the semi-elliptical gate oxide layer 5 can enhance the electric field uniformity in the channel region, thereby reducing the on-resistance and increasing the switching speed. This structure significantly improves the current driving ability and reliability of the device.

[0029] Example 2 AsFigure 2 As shown, the cross-sectional profile of the polysilicon overlay 4 is triangular, and extension layers 11 are deposited on the two sides of the polysilicon overlay 4. The material of the extension layer 11 is one of titanium nitride or tantalum nitride. A polysilicon overlay 4 with a triangular cross-section is introduced at the junction of the gate 3 and the gate oxide layer 5, and titanium nitride / tantalum nitride extension layers 11 are deposited on its two side edges. The polysilicon overlay 4 enhances the mechanical stability of the gate structure, the high conductivity of the extension layer reduces the contact resistance, and the chemical inertness of the nitride inhibits the interface oxidation, thereby reducing the leakage current and improving the high-temperature stability of the device.

[0030] Example 3 As Figure 3 shown, the gate 3 further includes a comb-shaped gate 31, where the comb-shaped gate 31 includes seven longitudinal teeth and a transverse beam for connecting the seven longitudinal teeth. The comb-shaped gate structure includes seven longitudinal teeth and a transverse connecting beam, increasing the effective control area of the gate. The distribution of the longitudinal teeth optimizes the lateral diffusion of the current in the channel, reducing the hot spot effect caused by uneven current density, and the transverse beam improves the overall structural strength of the gate 3. This design significantly improves the current-carrying capacity and switching efficiency of the device.

[0031] Example 4 As Figure 4 shown, a lower convex gate 12 is formed downward by ion implantation at the junction of the N substrate layer 6 and the N diffusion layer 7. The cross-sectional height of the lower convex gate 12 in the middle of a single MOS cell is higher than that at the two sides, and the lower convex gate 12 is a P-type structure layer formed by implanting boron elements. The lower convex gate 12 is formed by ion implantation at the junction of the N substrate 6 and the N diffusion layer 7, and the cross-sectional height in the middle region is higher than that at the two sides. This structure forms a gradient doping in the vertical direction, enhancing the longitudinal migration efficiency of the carriers. At the same time, the middle high-convex region can disperse the electric field intensity, reducing the probability of local breakdown, thereby improving the breakdown voltage and conduction uniformity of the device.

[0032] Example 5 As Figure 5 shown, an upper concave gate 13 is formed upward by ion implantation at the junction of the N substrate layer 6 and the N diffusion layer 7. The cross-sectional height of the upper concave gate 13 in the middle of a single MOS cell is lower than that at the two sides, and the upper concave gate 13 is a P-type structure layer formed by implanting boron elements. The upper concave gate 13 structure with a lower middle and higher sides is formed by upward ion implantation. This design forms an asymmetric electric field distribution in the horizontal direction. The middle lower concave region relieves the electric field congestion near the drain 1, and the two higher regions on both sides enhance the control ability of the gate 3 over the channel, thereby reducing leakage and improving the dynamic response characteristics of the device.

[0033] Example 6 AsFigure 6 As shown, an upper concave gate 13 is formed upward by ion implantation at the junction of the N substrate layer 6 and the N diffusion layer 7. The cross-sectional height of the upper concave gate 13 in the middle of a single MOS cell is lower than that of the upper concave gate 13 on both sides, and a field oxide layer 14 is deposited at the junction of the drain 1 and the N substrate layer 6 in the middle of a single MOS cell. The field oxide layer 14 is deposited in the middle region at the junction of the drain 1 and the N substrate layer 6. Combining with the upper concave gate 13 structure, the field oxide layer 14 provides additional lateral isolation, suppressing the parasitic capacitance and leakage current between the drain 1 and the N substrate layer 6. At the same time, the middle-low concave upper concave gate 13 structure and the field oxide layer 13 cooperate to optimize the electric field distribution, significantly improving the high-frequency performance and breakdown voltage stability of the device.

[0034] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A vertical D-MOSFET with trench isolation and an improved channel structure, comprising a plurality of MOS cells arranged side by side. Each MOS cell includes a drain (1), a source (2), a gate (3), a gate oxide layer (5), and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer (6), an N diffusion layer (7), a P+ layer (8), a P well layer (9), and an N well layer (10), characterized in that: The cross-sectional profile of the gate (3) is triangular, and a polysilicon capping layer (4) is deposited at the junction of the gate (3) and the gate oxide layer (5); the cross-sectional profile of the gate oxide layer (5) is semi-elliptical.

2. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, wherein: The cross-sectional profile of the polysilicon capping layer (4) is triangular, and extension layers (11) are deposited and formed at the two sides of the polysilicon capping layer (4).

3. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 2, characterized in that: The material of the extension layer (11) is one of titanium nitride or tantalum nitride.

4. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, characterized in that: The gate (3) further includes a comb-shaped gate (31), and the comb-shaped gate (31) includes seven longitudinal teeth and a transverse beam for connecting the seven longitudinal teeth.

5. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1, characterized in that: At the junction of the N substrate layer (6) and the N diffusion layer (7), a downwardly protruding gate (12) is formed by ion implantation, and the cross-sectional height of the downwardly protruding gate (12) in the middle of a single MOS cell is higher than that at the two sides.

6. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 1 or 3, characterized in that: At the junction of the N substrate layer (6) and the N diffusion layer (7), an upwardly concave gate (13) is formed by ion implantation, and the cross-sectional height of the upwardly concave gate (13) in the middle of a single MOS cell is lower than that at the two sides.

7. The vertical D-MOSFET with trench isolation and improved channel structure according to claim 6, characterized in that: A field oxide layer (14) is deposited and formed at the junction of the drain (1) and the N substrate layer (6) in the middle of a single MOS cell.

8. The vertical D-MOSFE with trench isolation and improved channel structure according to claim 5 or 6, characterized in that: Both the downwardly protruding gate (12) and the upwardly concave gate (13) are formed into a P-type structure layer by implanting boron elements.

9. A preparation method of a vertical D-MOSFET with trench isolation and an improved channel structure, characterized in that, Applied to the vertical D-MOSFET with trench isolation and improved channel structure according to any one of claims 6-8, the preparation method of the vertical D-MOSFET with trench isolation and improved channel structure specifically includes the following steps: S1. Based on the N substrate layer (6), an N diffusion layer (7), a P+ layer (8), a P well layer (9), and an N well layer (10) are sequentially formed by epitaxial growth technology. S2. Deep trenches are etched on the surface of the semiconductor epitaxial layer, and silicon dioxide is filled to form a trench isolation structure. S3. A gate (3) with a triangular cross-sectional profile is formed in the gate region by photolithography and dry etching processes, and the cross-sectional shape of the gate oxide layer (5) is controlled to be semi-elliptical. S4. A polysilicon capping layer (4) is deposited at the junction of the gate (3) and the gate oxide layer (5), and its cross-sectional profile is made triangular by an etching process. S5. Titanium nitride or tantalum nitride material is deposited on the two side edges of the polysilicon capping layer (4) to form extension layers (11). S6. An upwardly concave gate (13) with a low middle and high sides is formed by tilting the ion implantation of boron elements upward. S7. In the middle region of a single MOS cell, a field oxide layer (14) is deposited at the junction of the drain (1) and the N substrate layer (6).

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