Chip scale package photodiode

Abstract

A chip scale package photodiode includes a first conductive layer on a first side of the chip scale package photodiode. The first contact is located on a second side of the chip scale package photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact, the dopant diffusion layer traveling from the first side of the chip scale package photodiode completely through a depletion region of the chip scale package photodiode to the second side of the chip scale package photodiode.

Description

Background Art

[0001] Conventional photodiodes include an anode on the top of the photodiode and a cathode on the bottom side of the photodiode. However, both the anode and the cathode must include contacts connected to a printed circuit board (PCB) in order to provide a signal for processing from the photodiode. Brief Description of the Drawings

[0002] A more detailed understanding can be obtained from the following description given by way of example in conjunction with the accompanying drawings, wherein:

[0003] Figure 1 is a cross-section of a conventional photodiode;

[0004] Figure 2 is a cross-section of an integrated circuit chip including through-silicon vias;

[0005] Figure 3 is a cross-section of a chip-scale packaged photodiode according to an exemplary embodiment; and

[0006] Figure 4 is a flowchart showing an exemplary method of forming a chip-scale packaged photodiode according to an exemplary embodiment. Detailed Description

[0007] Chip-scale packaging is a technology that allows a semiconductor die (chip) to be directly soldered to a printed circuit board (PCB). Compared to encapsulating the die into a package, chip-scale packaging generally has smaller dimensions in both lateral size and height. Additionally, the cost of manufacturing chip-scale packaging can be less than the cost of manufacturing a conventional die encapsulated into a package.

[0008] Typically in chip-scale packaging, solder contacts and active semiconductor structures are on the bottom side of the die, while the top side is used for marking. Thus, no electrical connection between the bottom side and the top side is required in chip-scale packaging.

[0009] Chip-scale packaging for a photodiode allows the photodiode to have smaller dimensions and height. This can be beneficial in all applications with space constraints, such as in the field of wearable devices (e.g., heart rate monitoring and pulse oximetry).

[0010] However, the active structure of a photodiode (e.g., a pn junction diode) cannot be located on the bottom side of the device without significant performance degradation. That is, most of the light absorption of the photodiode (especially for short-wavelength light) will occur outside the depletion region. This can lead to a decrease in sensitivity due to recombination losses and extremely slow rise and fall times caused by carrier diffusion.

[0011] Although further details will be provided briefly below, a chip-level photodiode is described. The chip-level photodiode can be attached to a printed circuit board via, for example, soldering.

[0012] The chip-level packaged photodiode includes a first conductive layer on a first side of the chip-level packaged photodiode. A first contact is located on a second side of the chip-level packaged photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact, and the dopant diffusion layer travels completely through the depletion region of the chip-level packaged photodiode from the first side of the chip-level packaged photodiode to the second side of the chip-level packaged photodiode.

[0013] A method of forming a chip-level packaged photodiode includes forming a first conductive layer on a first side of the chip-level packaged photodiode. Forming a first contact on a second side of the chip-level packaged photodiode. Forming a dopant diffusion layer between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact, and the dopant diffusion layer travels completely through the depletion region of the chip-level packaged photodiode from the first side of the chip-level packaged photodiode to the second side of the chip-level packaged photodiode.

[0014] Figure 1 is a cross-section of a conventional photodiode 100. For purposes of example, an n-substrate photodiode is shown. However, it should be noted that the opposite polarity, for example using a p-type substrate, can also be implemented.

[0015] Although the operation of the conventional photodiode is briefly described below, the conventional photodiode 100 includes an antireflection coating (e.g., nitride) 101, a front-side (front) electrical contact (e.g., anode) 102, an oxide cover 103 over the resulting pn junction 103, a p-type anode layer 104 on the top side (light-incident side) of the die, a depletion region 105, an n-substrate 106, and a back-side (back) electrical contact (e.g., cathode) 107.

[0016] Incident photons are absorbed by the semiconductor material of the photodiode and will generate electron-hole pairs. The penetration depth of the photons depends on their wavelength. Shorter wavelengths will have a lower penetration depth than longer wavelengths.

[0017] If this absorption occurs within the depletion region 105 of the pn junction, the electric field will immediately separate the two carriers, thereby generating a photocurrent. If this absorption occurs below the depletion region 105, the two carriers will exhibit random diffusion motion.

[0018] If one of the carriers diffuses into the depletion region, a photocurrent will also be generated. In this case, there are two possible drawbacks that interfere with the performance of the photodiode. In one case, the current will be delayed due to the duration of the diffusion process. Additionally, it is also possible that the generated carriers are lost through recombination before they can reach the depletion region. This results in a reduced sensitivity of the photodiode.

[0019] For these reasons, the performance of a photodiode with an active structure on the back side (such as a typical standard die-level packaging device) related to sensitivity and response time may be significantly reduced.

[0020] In Figure 1 In the example shown, the anode contact is on the top (light-incident) side of the die, and the cathode contact is on the back side of the die. Since both the anode and the cathode can be accessed from the top side, it is also possible to have two contacts on the top side. However, in order to create the two contacts necessary for attaching the die as a die-level package by, for example, SMD soldering on the bottom side, an additional electrical connection of the anode to the back side of the device will be necessary.

[0021] One way to make an electrical connection in a chip is to use through-silicon vias (TSVs). A TSV is an area where an electrical conductor is filled in a region that intersects (coincides) with conductors from layers above or below to provide an electrical connection between silicon layers.

[0022] Figure 2 is a cross-section of an integrated circuit chip 200 including TSVs. As Figure 2 shown, the integrated circuit chip 200 includes a wafer front side 201 and a wafer back side 202. A silicon layer 203 exists between the wafer front side 201 and the wafer back side 202.

[0023] To connect the wafer front side to the wafer back side, through-silicon vias can be used. The TSV includes a conductive material 204 and an isolation region 205. In this way, the conductive material 204 provides a connection between the wafer front side 201 and the wafer back side 202 while being isolated from the silicon layer 203.

[0024] Conventional means of fabricating TSVs are based on a vertical etching process (e.g., Bosch process), followed by sidewall passivation and filling the holes with a conductive material (e.g., polysilicon). The residues of the passivation and filling materials are removed from the top and bottom surfaces of the wafer formed in the chip. Therefore, this process can be an expensive process and significantly increases the cost of the die.

[0025] Figure 3Is a cross-section of a chip-scale packaged photodiode 300 according to an exemplary embodiment. The chip-scale packaged photodiode includes a first conductive layer (e.g., anode) 301, a depletion region (zone) 302, a second conductive layer (e.g., n-substrate layer) 303, a first p-diffusion layer 304, a second p-diffusion layer 305, a solder contact anode 306, and a solder contact cathode 307.

[0026] As Figure 3 shown, instead of using a TSV to connect the first conductive layer 301 to the underlying contact anode 306, a deep diffusion layer is used to connect the first conductive layer 301 to the underlying contact anode 306. That is, the first p-diffusion layer 304 formed by using aluminum as a dopant in silicon can diffuse downward from the anode 301. The second p-diffusion layer 305 formed by using aluminum as a dopant in silicon can also be formed upward from the solder contact anode 306 toward the first p-diffusion layer 304.

[0027] The connection of the two diffusion layers (304 and 305) provides an electrical connection between the first conductive layer 301 and the contact anode 306. In this way, the first conductive layer 301 can be formed on the first side (e.g., top side) of the chip-scale packaged photodiode 300, while the contact anode 306 can be formed on the second side (e.g., bottom side) of the chip-scale packaged photodiode 300.

[0028] Alternatively, the electrical connection can also be created by only one diffusion layer starting from the bottom side or the top side of the wafer. In this case, the diffusion time will be longer.

[0029] Figure 4 Is a flowchart showing an exemplary method 400 for forming a chip-scale packaged photodiode according to an exemplary embodiment.

[0030] In a first step (step 410), a dopant diffusion layer is formed for the connection between the first conductive layer and the first contact (e.g., solder contact anode 306). As described above in Figure 3 it, the dopant diffusion layer can include a first p-diffusion layer formed from the first side of the chip-scale packaged photodiode toward the second side of the chip-scale packaged photodiode.

[0031] A second dopant diffusion layer (e.g., Figure 3 the second p-diffusion layer) can be formed upward from the first contact on the bottom of the chip-scale packaged photodiode toward the top of the chip-scale packaged photodiode.

[0032] The first dopant diffusion layer is connected to the second dopant diffusion layer to complete the electrical connection between the first conductive layer at the top of the chip-scale packaged photodiode and the anode contact at the bottom of the chip-scale packaged photodiode.

[0033] In a second step, a photodiode structure is created on the top side of the chip. That is, a first conductive layer is formed on the first side of the chip-level packaged photodiode (step 420).

[0034] In a third step, solder contacts are created on the bottom side of the chip. For example, a first contact layer is formed on the second side of the photodiode (step 430).

[0035] Although these steps may be performed in any order and additional steps may be utilized, such as to form a second conductive layer (e.g., Figure 3 the n-substrate 303), it may be desirable to perform step 410 before any other step of method 400 and any other steps that may be performed. If step 410 is performed after, for example, steps 420 and 430, the processes of performing steps 420 and 430 may result in the destruction of one or more doped diffusion layers.

[0036] It should be understood that many variations are possible based on the disclosure herein. Although the features and elements are described above in specific combinations, each feature or element may be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0037] For example, as described above, the described photodiode is shown as having a p-layer anode conductive layer and an n-substrate layer as the cathode. However, the opposite embodiment may also be used. Additionally, the doped diffusion layer may be an aluminum-doped diffusion layer or another type of metallization diffusion layer.

[0038] The above-described photodiode may be formed of silicon or any other suitable material. Additionally, the above-described photodiode may include a blue-enhanced photodiode.

[0039] By providing contacts on a single side of the photodiode, the photodiode can be made into a smaller package that can be implemented in a smaller device. For example, a wearable photodiode can be manufactured by allowing the light-incident side to be connected to a contact on the side where the photodiode is mounted or worn.

Claims

1. A chip - level packaged photodiode, comprising: A first conductive layer located on a first side of the chip - level packaged photodiode; A first contact located on a second side of the chip - level packaged photodiode; And A dopant diffusion layer formed between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact, the dopant diffusion layer traveling from the first side of the chip - level packaged photodiode completely through the depletion region of the chip - level packaged photodiode to the second side of the chip - level packaged photodiode.

2. The chip - level packaged photodiode according to claim 1, further comprising: A second conductive layer located on the second side of the chip - level packaged photodiode; And A second contact located on the second side of the chip - level packaged photodiode, the second contact being in electrical communication with the second conductive layer.

3. The chip-scale packaged photodiode according to claim 2, wherein, The first conductive layer is a p - type substrate layer.

4. The chip-scale packaged photodiode according to claim 3, wherein, The first contact is an anode.

5. The chip-scale packaged photodiode according to claim 3, wherein, The second conductive layer is an n - type substrate layer.

6. The chip-scale packaged photodiode according to claim 5, wherein, The second contact is a cathode.

7. The chip-scale packaged photodiode according to claim 1, wherein, The dopant diffusion layer is aluminum.

8. The chip-scale packaged photodiode according to claim 1, wherein, The dopant diffusion layer is formed from the first side to the second side.

9. The chip-level packaged photodiode according to claim 1, wherein, The dopant diffusion layer includes a first dopant diffusion portion formed from the first side to the second side and a second dopant diffusion portion formed from the second side to the first side and connected to the first dopant diffusion portion.

10. The chip-level packaged photodiode according to claim 1, wherein, The chip - level packaged photodiode is a blue - enhanced photodiode.

11. A method of forming a chip - level packaged photodiode, comprising: Forming a first conductive layer on a first side of the chip - level packaged photodiode; Forming a first contact on a second side of the chip - level packaged photodiode; And Forming a dopant diffusion layer formed between the first conductive layer and the first contact, the dopant diffusion layer electrically connecting the first conductive layer to the first contact, the dopant diffusion layer traveling from the first side of the chip - level packaged photodiode completely through the depletion region of the chip - level packaged photodiode to the second side of the chip - level packaged photodiode.

12. The method according to claim 11, further comprising: Forming a second conductive layer on the second side of the chip - level packaged photodiode; And Forming a second contact on the second side of the chip - level packaged photodiode, the second contact being in electrical communication with the second conductive layer.

13. The method according to claim 12, wherein, The first conductive layer is a p - type substrate layer.

14. The method according to claim 13, wherein, The first contact is an anode.

15. The method according to claim 13, wherein, The second conductive layer is an n - type substrate layer.

16. The method according to claim 15, wherein, The second contact is a cathode.

17. The method according to claim 11, wherein, The dopant diffusion layer is aluminum.

18. The method according to claim 11, further comprising forming the dopant diffusion layer from the first side to the second side.

19. The method according to claim 11, wherein, Forming the dopant diffusion layer includes forming a first dopant diffusion portion from the first side to the second side and forming a second dopant diffusion portion from the second side to the first side and connected to the first dopant diffusion portion.

20. The method according to claim 11, wherein, The chip - level packaged photodiode is a blue - enhanced photodiode.

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