Multi-platform television box at computer end, mobile phone end and television end

Abstract

The invention discloses a computer end, mobile phone end and television end multi-platform television box which comprises a main control module, a multi-platform adaptation module, an intelligent recommendation module, a cloud synchronization module, a user interface module, an interface module, a wireless communication module and a power module. The server is electrically connected with the multi-platform adaptation module, the intelligent recommendation module and the cloud synchronization module through a PCIe 4.0 data bus; the multi-platform adaptation module comprises a computer end adaptation sub-module, a mobile phone end adaptation sub-module and a television end adaptation sub-module. Therefore, x86 instruction conversion, multi-system protocol compatibility and ultra-high-definition video encryption transmission are realized by adopting a three-platform adaptation sub-module of a parallel architecture, seamless joint of multiple systems is supported, GPU hardware acceleration and a DMA data channel are combined, the processing speed of a recommendation algorithm is improved, a dual-power architecture adapts to a mobile scene, and high-load stable operation is guaranteed by three-dimensional heat dissipation; the equipment life is prolonged.

Description

Technical Field

[0001] This application relates to the technical field of intelligent terminal devices, and particularly to multi-platform TV boxes for computer, mobile phone, and TV terminals. Background Art

[0002] With the popularization of 5G and AI technologies, users' cross-platform interaction requirements for intelligent terminal devices are increasing day by day. Traditional TV boxes have the following technical bottlenecks:

[0003] 1. Insufficient multi-platform compatibility: Existing devices are usually designed only for the TV terminal, and there are compatibility barriers in protocol adaptation for computer terminals (such as Windows / macOS systems) and mobile phone terminals (iOS / Android systems), making it impossible to achieve seamless cross-device connection.

[0004] 2. Low efficiency of intelligent recommendation: Traditional recommendation algorithms rely on single-core processing of the central processing unit (CPU), resulting in delays when processing large-scale user behavior data and lacking a hardware acceleration mechanism, leading to insufficient real-time recommendation.

[0005] 3. Rigid hardware architecture: There is insufficient modular design, and the adaptation module and the main control module mostly use serial connections, resulting in limited data throughput and unable to support cross-platform transfer of 4K / 8K ultra-high-definition content.

[0006] In response to the above problems, although some improvement solutions have been proposed in the prior art, such as adding a general interface or integrating a simple protocol conversion chip, no systematic hardware architecture innovation and functional module coordination have been formed, making it difficult to meet the technical requirements of multi-platform in-depth interaction. Therefore, there is an urgent need for a multi-platform intelligent TV box with a parallel adaptation architecture, hardware-accelerated recommendation, and distributed security verification. Summary of the Invention

[0007] This application aims to solve at least one of the technical problems in the related art to some extent.

[0008] To this end, the first objective of this application is to provide a multi-platform TV box for computer, mobile phone, and TV terminals, which can achieve x86 instruction conversion, dual-system protocol compatibility, and ultra-high-definition video encrypted transmission through a three-platform adaptation sub-module with a parallel architecture, and support seamless docking of multiple systems such as Windows, macOS, iOS, Android, and TVOS.

[0009] The second objective of this application is to provide a multi-platform TV box for computer, mobile phone, and TV terminals, which combines GPU hardware acceleration and DMA data channels to greatly improve the processing speed of the recommendation algorithm.

[0010] The third object of the present application is to provide a multi-platform TV box for computer, mobile phone and TV terminals, with a dual-power architecture to support mobile scenarios, a three-dimensional heat dissipation design to ensure stable operation under high load, and an extended device life.

[0011] To achieve the above object, the first aspect embodiment of the present application proposes a multi-platform TV box for computer, mobile phone and TV terminals, including a main control module, a multi-platform adaptation module, an intelligent recommendation module, a cloud synchronization module, a user interface module, an interface module, a wireless communication module and a power module. Among them, the main control module is fixedly installed on the central substrate of the device housing and is electrically connected to the multi-platform adaptation module, the intelligent recommendation module and the cloud synchronization module through a PCIe 4.0 data bus respectively; the multi-platform adaptation module includes a computer terminal adaptation sub-module, a mobile phone terminal adaptation sub-module and a TV terminal adaptation sub-module, and each adaptation sub-module is integrated on a multi-layer PCB substrate in a parallel architecture, and the PCB substrate is vertically plugged into the main control module; the interface module includes an HDMI interface, a USB3.0 interface and a Type-C composite interface, which are linearly arranged along the rear side wall of the device housing, and the distance between adjacent interfaces is 8-10 mm; the wireless communication module is embedded under the heat dissipation grille at the top of the device housing and includes a WiFi6 chipset and a Bluetooth 5.2 chipset, and the two adopt a stacked packaging structure.

[0012] The multi-platform TV box for computer, mobile phone and TV terminals in the embodiment of the present application adopts a three-platform adaptation sub-module with a parallel architecture to realize x86 instruction conversion, multi-system protocol compatibility and ultra-high-definition video encrypted transmission, support seamless docking of multiple systems, combine GPU hardware acceleration and DMA data channels to improve the processing speed of the recommendation algorithm, a dual-power architecture to adapt to mobile scenarios, and three-dimensional heat dissipation to ensure stable operation under high load, and extend the device life.

[0013] In addition, the multi-platform TV box for computer, mobile phone and TV terminals proposed above according to the present application may also have the following additional technical features:

[0014] In an embodiment of the present application, the intelligent recommendation module includes a user behavior feature register and a recommendation result buffer. The user behavior feature register is connected to the main control module through a DMA channel, and the recommendation result buffer is provided with a GPU acceleration chip, and the surface of the GPU acceleration chip is covered with a heat-conducting graphite sheet and is thermally connected to the heat dissipation module.

[0015] In an embodiment of the present application, the cloud synchronization module includes a physical encryption chip and a distributed verification node array. The physical encryption chip is integrated in an independent security isolation area, and the distributed verification node array is composed of at least three verification node circuits, and each node circuit is arranged in a ring topology on the second layer of the PCB.

[0016] In one embodiment of the present application, the user interface module includes a display driver chip and a touch control circuit board. The display driver chip is connected to the main control module through an LVDS interface. The surface of the touch control circuit board is provided with capacitive touch sensors, and the electrode arrays are arranged in a staggered pattern with a pitch of 0.5 mm.

[0017] In one embodiment of the present application, the computer-side adaptation sub-module includes an FPGA chip and a drive virtualization circuit. The x86 instruction set conversion logic is burned into the FPGA chip. The mobile phone-side adaptation sub-module integrates a protocol conversion chip, and the surface of the chip is provided with iOS / Android dual-protocol antennas. The TV-side adaptation sub-module includes an HDCP2.3 encryption chip and a resolution scaling chip, and the two are three-dimensionally stacked and packaged through through-silicon via (TSV) technology.

[0018] In one embodiment of the present application, the power supply module includes a lithium battery pack and a PoE power supply circuit. The lithium battery pack is located in the bottom chamber of the device housing and is detachably installed through a buckle. The PoE power supply circuit integrates an intelligent switching relay, and the coil contacts of the relay are directly connected to the GPIO pins of the main control module.

[0019] In one embodiment of the present application, the heat-conducting graphite sheet of the GPU acceleration chip extends to the side wall of the device housing, and the edge is provided with wavy heat dissipation teeth with a height of 2 mm and a pitch of 1.5 mm.

[0020] In one embodiment of the present application, the iOS / Android dual-protocol antenna adopts a serpentine trace layout with a line width of 0.2 mm and a line pitch of 0.15 mm, and the operating frequency covers the dual frequency bands of 2.4 GHz / 5.8 GHz.

[0021] The advantages of the present application compared with the existing technology are as follows:

[0022] (1) Through the three-platform adaptation sub-module with a parallel architecture, x86 instruction conversion, dual-system protocol compatibility, and ultra-high-definition video encrypted transmission are realized, supporting seamless docking of multiple systems such as Windows, macOS, iOS, Android, and TVOS.

[0023] (2) The combination of GPU hardware acceleration and the DMA data channel greatly improves the processing speed of the recommendation algorithm.

[0024] (3) The dual-power architecture supports use in mobile scenarios, and the three-dimensional heat dissipation design ensures stable operation under high loads and extends the device life.

[0025] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Description of the Drawings

[0026] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, where:

[0027] Figure 1 is a perspective view of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0028] Figure 2 is a schematic diagram of the internal structure of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0029] Figure 3 is a schematic diagram showing the connection between the main control module and the multi-platform adaptation module of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0030] Figure 4 is a detailed schematic diagram of the intelligent recommendation module of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0031] Figure 5 is a schematic diagram of the composition of the cloud synchronization module of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0032] Figure 6 is a schematic diagram of the connection of the user interface module of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application;

[0033] Figure 7 is a schematic diagram of the interface, wireless communication, and power module of a multi-platform TV box for computer, mobile phone, and TV terminals according to an embodiment of the present application.

[0034] As shown in the figure: 1. Main control module;

[0035] 2. Multi-platform adaptation module; 21. Computer terminal adaptation sub-module; 211. FPGA chip; 212. Drive virtualization circuit; 22. Mobile phone terminal adaptation sub-module; 221. Protocol conversion chip; 222. iOS / Android dual-protocol antenna; 23. TV terminal adaptation sub-module; 231. HDCP2.3 encryption chip; 232. Resolution scaling chip;

[0036] 3. Intelligent recommendation module; 31. User behavior feature register; 32. Recommendation result buffer; 33. GPU acceleration chip; 34. Thermal conductive graphite sheet;

[0037] 4. Cloud synchronization module; 41. Physical encryption chip; 42. Distributed verification node array; 421. Verification node circuit;

[0038] 5. User Interface Module; 51. Display Driver Chip; 52. Touch Control Circuit Board; 521. Capacitive Touch Sensor; 522. Electrode Array;

[0039] 6. Interface Module; 61. HDMI Interface; 62. USB3.0 Interface; 63. Type-C Composite Interface;

[0040] 7. Wireless Communication Module; 71. WiFi6 Chipset; 72. Bluetooth 5.2 Chipset;

[0041] 8. Power Module; 81. Lithium Battery Pack; 82. PoE Power Supply Circuit; 821. Intelligent Switching Relay; 822. Coil Contact. Detailed Implementation Manner

[0042] The following describes the multi-platform TV box for computer, mobile phone, and TV of the embodiments of the present application with reference to the accompanying drawings.

[0043] As Figures 1-7 shown, the multi-platform TV box for computer, mobile phone, and TV of the embodiments of the present application may include a main control module 1, a multi-platform adaptation module 2, an intelligent recommendation module 3, a cloud synchronization module 4, a user interface module 5, an interface module 6, a wireless communication module 7, and a power module 8.

[0044] It can be understood that the main control module 1 is fixedly installed on the central substrate inside the device housing. As the system core computing unit, it realizes electrical connection with the peripheral function modules through the PCIe 4.0 data bus (high-speed serial bus, bandwidth up to 16GB / s). The multi-platform adaptation module 2 adopts a multi-layer PCB substrate design, integrating a computer-end adaptation sub-module 21, a mobile-phone-end adaptation sub-module 22, and a TV-end adaptation sub-module 23. The three are distributed in different areas of the PCB substrate in a parallel architecture (signals are processed independently and do not interfere with each other). The substrate is vertically plugged into the PCIe interface of the main control module 1 through the edge gold finger slot (plugging angle 90°, number of gold finger contact points ≥ 500, contact impedance ≤ 50mΩ), realizing hardware hot plugging and high-speed data interaction.

[0045] The interface module 6 is arranged on the rear side wall of the device housing and includes:

[0046] HDMI interface 61 (compliant with HDMI 2.1 standard): used to connect the TV-end display device, support 8K@60Hz ultra-high-definition video transmission, be compatible with the HDCP2.3 encryption protocol, and realize high-definition output and copyright protection of TV-end signals;

[0047] USB3.0 interface 62 (transmission rate 10Gbps): supports the access of peripherals such as U disks, keyboards, and mice, and provides a physical channel for data storage and interaction between the computer end / mobile phone end;

[0048] The Type-C composite interface 63: Supports USB PD 3.0 power supply (up to 100W) and DisplayPort 1.4 video output, and can be directly connected to a computer-side monitor or a mobile phone-side docking station to achieve two-way transmission of audio and video signals between multiple devices.

[0049] The above interfaces are linearly arranged along the rear side wall, and the distance between adjacent interfaces is strictly controlled within 8 - 10 mm (meeting the EMC electromagnetic compatibility design to avoid signal crosstalk). The surface of the interfaces is covered with a metal shielding cover (shielding effectiveness ≥ 40 dB) to enhance the anti-interference ability.

[0050] The wireless communication module 7 is embedded under the heat dissipation grille at the top of the housing (the grille aperture is 2 mm, and the opening rate ≥ 30%). It uses a WiFi6 chipset 71 (supporting the IEEE 802.11ax protocol, with a theoretical rate of 3.6 Gbps) and a Bluetooth 5.2 chipset 72 in a stacked package (the chip spacing ≤ 0.5 mm, vertically interconnected through bottom solder joints). Among them:

[0051] The WiFi6 chipset directly radiates signals to the outside through the top heat dissipation grille, supports the 2.4 GHz / 5 GHz dual bands, and realizes high-speed wireless connection with the computer side and the mobile phone side (the signal coverage radius ≥ 10 meters);

[0052] The Bluetooth 5.2 chipset supports low-power Bluetooth (BLE) and classic Bluetooth protocols, and can establish a stable connection with mobile phone-side peripherals such as headphones and remote controls (the connection delay ≤ 10 ms).

[0053] The stacked package structure effectively saves PCB space (the occupied area is reduced by 40% compared with the traditional parallel package), and at the same time uses the metal frame of the top heat dissipation grille as an auxiliary antenna to enhance the signal transmission stability.

[0054] Cross-platform data interaction process:

[0055] Wired connection scenario:

[0056] Computer-side devices are connected through the Type-C composite interface 63 or the USB3.0 interface 62. The data is transmitted to the main control module 1 through the interface module 6, and then sent to the computer-side adapter sub-module 21 through the PCIe 4.0 bus to realize the protocol conversion between the x86 instruction set and the ARM architecture, and support the operation of Windows / macOS system software;

[0057] TV-side devices are connected through the HDMI interface 61. The TV-side adapter sub-module 23 performs resolution scaling and HDCP encryption on the video signal, transmits it to the main control module 1 through the PCIe bus, and finally outputs it to the TV-side display.

[0058] Wireless connection scenario:

[0059] The mobile device establishes a connection with the wireless communication module 7 through the WiFi6 chipset 71 or the Bluetooth 5.2 chipset 72. The signal is processed by the RF front-end and then transmitted to the main control module 1. The mobile device adapter sub-module 22 then identifies the iOS / Android system protocol to enable functions such as mobile mirroring screen projection and file sharing.

[0060] Module cooperation mechanism:

[0061] Each adapter sub-module (21 / 22 / 23) independently processes the corresponding platform signal through a parallel architecture to avoid resource contention. The data is aggregated to the main control module 1 via the PCIe 4.0 bus for cross-platform scheduling and finally output to the target device through the interface module 6 or the wireless communication module 7, achieving seamless multi-platform docking (signal processing latency ≤ 20ms).

[0062] The main control module 1 is built with a cross-platform scheduling engine that dynamically allocates the PCIe 4.0 bus bandwidth based on task priority and resource occupancy. The specific mechanism is as follows:

[0063] 1. Priority classification strategy:

[0064] Define three levels of task priority:

[0065] High priority (real-time tasks): 8K video encoding / decoding, touch input response (scheduling period ≤ 10μs);

[0066] Medium priority (data interaction tasks): x86 instruction conversion, iOS / Android protocol parsing (scheduling period ≤ 50μs);

[0067] Low priority (background tasks): cloud synchronization data verification, recommendation model parameter update (scheduling period ≤ 200μs).

[0068] 2. Concurrent processing mechanism:

[0069] Adopt time-division multiplexing (TDM) combined with dynamic caching technology:

[0070] Allocate independent data buffers (each with a capacity of 2MB) for the multi-platform adapter module 2, the intelligent recommendation module 3, and the cloud synchronization module 4 respectively;

[0071] When multiple tasks are concurrent, the main control module 1 activates the PCIe channels of the corresponding modules in priority order through the arbiter to ensure unblocked transmission of high-priority tasks (latency ≤ 20μs), and low-priority tasks enter the queue for waiting (queue depth ≤ 8).

[0072] 3. Load balancing strategy:

[0073] Real-time monitor the temperature and computing power occupancy of each module (read chip sensor data through the I2C bus):

[0074] If the temperature of the GPU acceleration chip 33 ≥ 70°C, automatically reduce the computing power allocation of the recommended tasks to 80%, and temporarily increase the resolution scaling computing power of the TV-side adaptation sub-module 23;

[0075] When the logical resource occupancy rate of the FPGA chip 211 of the computer-side adaptation sub-module 21 > 90%, trigger the x86 instruction cache mechanism (temporarily store high-frequency instructions in the main control module memory) to avoid system jamming.

[0076] In an embodiment of the present application, as Figures 1-7 shown, the intelligent recommendation module 3 includes a user behavior feature register 31 and a recommendation result buffer 32. The user behavior feature register 31 is connected to the main control module 1 through a DMA channel. The recommendation result buffer 32 is provided with a GPU acceleration chip 33, and the surface of the GPU acceleration chip 33 is covered with a thermal graphite sheet 34 and is thermally connected to the heat dissipation module.

[0077] It can be understood that the intelligent recommendation module 3 is integrated on the device motherboard, adjacent to the main control module 1 in layout, and includes two core components: the user behavior feature register 31 and the recommendation result buffer 32. Among them:

[0078] The user behavior feature register 31 adopts a high-speed register array (storage capacity 128KB, access latency ≤ 5ns), and is directly connected to the memory controller of the main control module 1 through a DMA channel (direct memory access channel) to achieve zero-copy transmission of user operation data;

[0079] The recommendation result buffer 32 is built-in with a GPU acceleration chip 33 (model NVIDIA T4, computing power up to 130TOPS). The surface of the chip is covered with a thermal graphite sheet 34 (thickness 0.3mm, thermal conductivity ≥ 1500W / m·K). The edge of the graphite sheet is thermally connected to the device heat dissipation module (aluminum alloy frame of the housing) through a silicon-based thermal conductive adhesive to form an efficient heat dissipation path.

[0080] User Behavior Data Acquisition and Transmission

[0081] 1. Real-time data acquisition:

[0082] The user behavior feature register 31 monitors user operations in real time, including but not limited to:

[0083] TV side: video playback progress, pause / rewind frequency, channel switching record;

[0084] Mobile side: APP click duration, screen mirroring operation instruction, favorite / ratings behavior;

[0085] Computer side: file transfer record, external device control instruction, multitasking switching log.

[0086] The register samples data at a period of 500 μs to form a feature data packet containing a timestamp, an operation type, and a target object ID (the single-packet data volume ≤ 128 bytes).

[0087] 2. High-efficiency transmission through the DMA channel:

[0088] The feature data packet is directly written into the system memory of the main control module 1 through the DMA channel, bypassing CPU intervention (the traditional CPU transmission delay is about 100 ns, and DMA only requires 20 ns). The specific process is as follows:

[0089] Register 31 sends a DMA request signal to the main control module 1;

[0090] The main control module 1 allocates a memory address and returns an acknowledgment;

[0091] The data is directly written into the target memory area through the PCIe 4.0 bus at a rate of 2 GB / s, and no CPU interruption processing is required throughout the process.

[0092] Recommended algorithm acceleration processing mechanism

[0093] 1. Parallel computing by the GPU acceleration chip 33:

[0094] The recommended result buffer 32 receives the user feature data and system status parameters (such as the current time, device platform type) sent by the main control module 1, and the following processing is performed by the GPU acceleration chip 33:

[0095] Feature preprocessing: Normalize and deduplicate the user behavior data to generate a feature vector with a dimension of 1024;

[0096] Model inference calculation: Run deep learning recommendation models (such as Wide&Deep, Neural Collaborative Filtering), and use 256 CUDA cores of the GPU to perform parallel matrix multiplication calculations. The single-batch processing time ≤ 1 ms (the traditional CPU processing requires 20 ms);

[0097] Result screening and sorting: According to the recommendation scores output by the model, perform Top-N sorting (N = 20) on the candidate content (such as videos, applications, files) to generate a recommendation list.

[0098] 2. Caching and output mechanism:

[0099] The processed recommendation list is temporarily stored in the high-speed cache of the recommended result buffer 32 (with a capacity of 2 MB and an access speed of 5 GB / s), and is output in the following two ways:

[0100] Real-time push: Send an interrupt signal to the main control module 1 through the PCIe bus to trigger the real-time update of the recommended content in the user interface module 5;

[0101] Asynchronous storage: Back up to the device storage module through a low-speed bus.

[0102] Thermal management system design and reliability assurance

[0103] 1. Heat conduction path of the thermal graphite sheet 34:

[0104] The surface of the GPU acceleration chip 33 is coated with a 50-μm-thick high thermal conductivity silicone grease (thermal resistance ≤ 0.1 °C·cm 2 / W), which is closely attached to the thermal graphite sheet 34. The graphite sheet dissipates heat through the following path:

[0105] Chip heat → silicone grease → graphite sheet → aluminum alloy frame of the device housing → air convection (when the surface temperature of the housing ≤ 45 °C and the room temperature is 25 °C);

[0106] The graphite sheet horizontally covers the entire surface of the chip and longitudinally extends to the edge of the module, indirectly contacting the heat dissipation copper foil layer below the main board to form a three-dimensional heat dissipation network.

[0107] 2. Temperature threshold control:

[0108] The main control module 1 reads the temperature sensor data of the GPU acceleration chip 33 in real time through the I2C bus. When the chip temperature exceeds 75 °C:

[0109] Reduce the GPU operating frequency to 80% (computing power drops to 104 TOPS);

[0110] Send an enhanced heat dissipation instruction to the heat dissipation module.

[0111] In an embodiment of the present application, as Figures 1-7 shown, the cloud synchronization module 4 includes a physical encryption chip 41 and a distributed verification node array 42. The physical encryption chip 41 is integrated in an independent security isolation area. The distributed verification node array 42 is composed of at least three verification node circuits 421, and each node circuit 421 is arranged in a ring topology on the second layer of the PCB.

[0112] It can be understood that the cloud synchronization module 4 is integrated in the edge area of the device main board and includes two core components:

[0113] Physical encryption chip 41: Adopts an independent package (size 8mm × 8mm × 1.2mm), integrated in a security isolation area wrapped by a metal shielding cover (shielding cover thickness 0.5mm, electromagnetic shielding effectiveness ≥ 60dB), and is connected to the main control module 1 through a dedicated SPI bus (rate 10Mbps) to ensure that the data transmission process is not affected by external electromagnetic interference;

[0114] Distributed verification node array 42: It consists of at least three verification node circuits 421. Each node circuit is arranged in a ring topology on the second layer of the PCB (300μm away from the PCB surface). Adjacent nodes are connected by equal-length differential signal lines (line length error ≤ 5mil) to form a ring communication link (signal delay ≤ 2ns / node).

[0115] Secure isolation area and physical encryption mechanism

[0116] 1. Data encryption processing flow:

[0117] Data to be synchronized (such as user configuration, recommendation records, file data) is transmitted to the physical encryption chip 41 through the main control module 1 via the SPI bus;

[0118] The chip is built-in with an AES-256 encryption engine to perform hardware-level encryption on the data (encryption rate 1.2GB / s). The key is stored in the on-chip one-time programmable (OTP) memory and cannot be read through external interfaces;

[0119] The encrypted data generates a 128-bit check code, which is encapsulated together with the original data hash value to form a secure data frame (format: [check code][encrypted data][timestamp]).

[0120] Supplement to the key management of the physical encryption chip - Key generation: A true random number generator based on PUF (Physical Unclonable Function) is adopted. The main key MK is updated every 24 hours, and the session key SK = HKDF(MK, Salt, Info) is derived through the HKDF algorithm, where Salt is the hash value of the chip serial number and Info is the timestamp.

[0121] Secure storage: The key is stored in the internal fuse memory (OTP area) of the chip. External access requires challenge-response authentication in the secure isolation area (SHA-256 hash chain verification, response time ≤ 10μs).

[0122] Prevention of side-channel attacks: Random delays (0 - 50ns) and pseudo-operation instructions are introduced during the encryption operation to confuse the power consumption characteristics.

[0123] 2. Design details of the secure isolation area:

[0124] The shielding cover and the PCB substrate are bonded by conductive adhesive (contact resistance ≤ 10mΩ) to form a Faraday cage structure to block external electromagnetic coupling;

[0125] The chip pins adopt a via design with magnetic bead filtering (magnetic bead impedance 50Ω@1GHz) to suppress high-frequency noise interference.

[0126] Operating principle of the distributed verification node array

[0127] 1. Hardware composition of the node circuit:

[0128] Each verification node circuit 421 integrates a microcontroller (model STM32L476), a SHA-256 hash operation unit, and a 512KB cache, and communicates bidirectionally with adjacent nodes through a ring link (the communication protocol is custom-defined, and CRC-32 checksum is used to ensure data integrity).

[0129] 2. Ring topology verification process:

[0130] Data sharding: The encrypted data frame is divided into 3 equal-length data segments (each segment ≤ 1KB) by the main control module 1 and sent to 3 verification node circuits 421 respectively;

[0131] Parallel verification: Each node independently calculates the SHA-256 hash value of the data segment (the calculation time ≤ 10μs) and broadcasts it to other nodes through the ring link;

[0132] Consensus reached: When the hash values of at least 2 nodes are consistent (majority consensus mechanism), a global verification result (verification passed / failed) is generated and fed back to the main control module 1 through the ring link;

[0133] Exception handling: If the hash values between nodes are inconsistent, a retransmission mechanism is triggered (retry up to 3 times), and if it still fails, the data frame is marked as invalid.

[0134] Module collaborative work process

[0135] 1. Data upload to the cloud:

[0136] The main control module 1 sends the data to be synchronized to the physical encryption chip 41 to complete AES-256 encryption and checksum generation;

[0137] The encrypted data frame is distributed to the verification node circuit 421 through the ring link to start parallel hash verification;

[0138] After verification passes, the data is transmitted to the cloud server through the wireless communication module 7 or the interface module 6, along with the verification signature generated by the node (including the timestamp and hash value of each node).

[0139] 2. Data download to the local:

[0140] The data frame received from the cloud is first subjected to hash verification by the verification node circuit 421 to confirm that it is consistent with the original checksum stored locally;

[0141] After verification passes, it is decrypted by the physical encryption chip 41 and output to the main control module 1 for subsequent processing.

[0142] It should be noted that the distributed verification node consensus algorithm supplement:

[0143] Byzantine Fault Tolerance Protocol:

[0144] 1. Pre - prepare Phase: The primary node (randomly elected) broadcasts a verification request to all nodes, along with the data hash value H(D) and timestamp T;

[0145] 2. Prepare Phase: Each node calculates H(D) and compares it with the received value. If they are consistent, it broadcasts "Ready";

[0146] 3. Confirm Phase: After a node receives signals of "Ready" from ≥ 2 / 3 of the nodes, it submits the local verification result;

[0147] 4. Fault Tolerance Handling: If a node does not respond within 200ms, it is marked as a faulty node, and the remaining nodes re - elect the primary node and restart the process.

[0148] The fault recovery process of the distributed verification node array 42 is as follows:

[0149] 1. Fault Detection Mechanism:

[0150] The main control module 1 monitors the heartbeat signal of the verification node circuit 421 in real - time through the ring - shaped link (transmission period: 100ms):

[0151] If a node does not respond to the heartbeat for 3 consecutive times (within 300ms), it is marked as a "faulty node", and the redundant node replacement process is triggered.

[0152] 2. Redundant Node Configuration:

[0153] One spare verification node circuit is preset, which is in a dormant state usually (power consumption ≤ 0.1W), and its hardware configuration is the same as that of the primary node;

[0154] The spare node stores the latest global verification log (achieved by periodically synchronizing the data of the primary node).

[0155] 3. Node Replacement Process:

[0156] The main control module 1 broadcasts a "node fault" signal to the ring - shaped link and pauses the current verification task;

[0157] Disconnect the faulty node from the adjacent nodes, and connect the spare node to the original ring - shaped topology (physical connection is achieved through the switching relay preset on the PCB);

[0158] After the new node is connected, it restores the verification state through the fast synchronization protocol (only transmits the last 10 verification records), and the time consumption ≤ 50ms;

[0159] Restart the distributed verification process and reach a consensus using the Byzantine Fault Tolerance Protocol (BFT) (≥ 2 / 3 nodes need to respond normally).

[0160] 4. Fault Node Repair:

[0161] When the device is idle (e.g., without data synchronization tasks), the main control module 1 attempts to reset the faulty node:

[0162] If the reset is successful, it is re-incorporated into the node array as a standby node;

[0163] If the reset fails, the user interface module 5 prompts "Please contact maintenance" through the user interface and disables the node.

[0164] In an embodiment of the present application, as Figures 1-7 shown, the user interface module 5 includes a display driver chip 51 and a touch control circuit board 52. The display driver chip 51 is connected to the main control module 1 through an LVDS interface. The surface of the touch control circuit board 52 is provided with a capacitive touch sensor 521, and its electrode array 522 is arranged staggered at a pitch of 0.5 mm.

[0165] It can be understood that the user interface module 5 is integrated inside the front panel of the device and includes two core components:

[0166] Display Driver Chip 51: Adopts BGA packaging (with 240 pins), is connected to the main control module 1 through an LVDS interface (low-voltage differential signal interface), supports a video data transmission rate of 10.2 Gbps, and has a built-in 2K / 4K resolution rendering engine;

[0167] Touch Control Circuit Board 52: Its size fits the front panel of the device. The surface is covered with a capacitive touch sensor 521, and the electrode array 522 is arranged below it, staggered at a pitch of 0.5 mm (the horizontal electrodes and vertical electrodes cross at 90° to form a sensing matrix of 200×300 pixels).

[0168] Working Process of Display Driver Chip 51

[0169] 1. Video Data Reception and Processing:

[0170] The main control module 1 sends RGB format video data (resolution supports 1920×1080 to 3840×2160) to the display driver chip 51 through the LVDS interface;

[0171] The chip has a built-in image scaling engine that dynamically adjusts the picture ratio according to the resolution of the target display device (e.g., adapting 16:9 content to a 21:9 screen), and at the same time performs color space conversion (RGB→YUV420) to reduce the transmission bandwidth.

[0172] 2. LVDS Signal Conversion and Output:

[0173] The processed video data is encoded into LVDS differential signals (a total of 4 pairs of data differential pairs + 1 pair of clock differential pairs) and transmitted to an external display terminal of the device (such as a TV, computer monitor, or touch display screen) through shielded twisted pair cables;

[0174] During the signal transmission process, a 1.2V low voltage swing is adopted, combined with a 50Ω termination resistor, to suppress electromagnetic interference (EMI) below 30dBμV / m (in the 30 - 1000MHz frequency band).

[0175] Working principle of the touch control circuit board 52

[0176] 1. Capacitive touch detection mechanism:

[0177] High - frequency alternating currents (frequency 100kHz) are respectively applied to the horizontal and vertical electrodes of the electrode array 522 to form a capacitive coupling field;

[0178] When the user's finger touches the surface of the touch sensor 521, the parasitic capacitance between the finger and the electrode causes a change in the coupling field. The touch position is located by detecting the capacitance change amount (ΔC≥0.1pF) of each electrode.

[0179] 2. Touch coordinate calculation process:

[0180] The touch control circuit board 52 is built - in with a microcontroller (model STM32G071), which scans the electrode array 522 at a frequency of 100Hz to obtain the capacitance value matrix of the horizontal / vertical electrodes;

[0181] The row - by - row scanning method is used to identify the touch point: when the capacitance change of a certain row and a certain column of electrodes exceeds the threshold, the row number (X - axis) and column number (Y - axis) are recorded, and the actual touch coordinates (accuracy ±0.8mm) are calculated in combination with the 0.5mm electrode pitch;

[0182] Supports single - point touch and two - point touch (realized by detecting two independent capacitance change regions), and the output coordinate data format is (X, Y, number of touch points).

[0183] Module cooperation working process

[0184] 1. Display output path:

[0185] Main control module 1→LVDS interface→display driver chip 51 (data processing)→LVDS differential signal→external display device (such as TV screen, computer monitor).

[0186] 2. Touch control input path:

[0187] Touch operation → Capacitive touch sensor 521 → Capacitance change in electrode array 522 → Touch control circuit board 52 → Microcontroller calculates coordinates → Transmits to the main control module (1) via the I2C bus (rate 400 kHz) → Triggers corresponding functions (such as interface switching, parameter adjustment).

[0188] 3. Timing synchronization mechanism:

[0189] The display driver chip 51 is synchronized with the main control module 1 through the LVDS clock signal to ensure that the video frame refresh rate is consistent with the touch control scan frequency (typical value 60 Hz);

[0190] After each scan, the touch control circuit board 52 sends an interrupt signal to the main control module 1 to avoid operation response lag caused by data transmission delay (touch control response time ≤ 30 ms).

[0191] In an embodiment of the present application, as Figures 1-7 shown, the computer-side adapter sub-module 21 includes an FPGA chip 211 and a drive virtualization circuit 212. The FPGA chip 211 is programmed with x86 instruction set conversion logic. The mobile phone-side adapter sub-module 22 integrates a protocol conversion chip 221, and the surface of the chip is provided with iOS / Android dual-protocol antennas 222. The TV-side adapter sub-module 23 includes an HDCP2.3 encryption chip 231 and a resolution scaling chip 232, and the two are three-dimensionally stacked and packaged through through-silicon via (TSV) technology.

[0192] It can be understood that the computer-side adapter sub-module 21 is integrated in the left area of the PCB substrate of the multi-platform adapter module 2 and includes:

[0193] FPGA chip 211 (model Xilinx Zynq UltraScale+): Soldered to the PCB through BGA packaging, programmed with x86 instruction set conversion logic inside, supporting dynamic binary translation technology to convert x86 instructions of Windows / macOS systems into ARM architecture executable code in real time;

[0194] Supplement to the instruction mapping table update mechanism: Online update process:

[0195] 1. When the main control module 1 detects a new x86 instruction (such as AVX512), it sends an interrupt signal to the FPGA via the PCIe bus;

[0196] 2. The FPGA pauses the current task and downloads the update package (including the ARM mapping code of the new instruction) from the cloud synchronization module 4;

[0197] 3. After verifying the digital signature of the update package (ECDSA-256 algorithm), it is written into the configuration memory of the FPGA (BankSwitching mechanism to ensure seamless switching);

[0198] 4. Restart the FPGA logic unit and load the new instruction set.

[0199] Compatibility guarantee: Reserve the rollback area of the old version mapping table. If the new instruction runs abnormally, it will automatically recover to the previous stable version within 30 seconds.

[0200] Drive virtualization circuit 212: Composed of a CPLD chip (model Lattice ECP5) and peripheral resistive-capacitive components, it simulates the hardware drive environment on the computer side (such as graphics card, sound card, network card drivers) to achieve seamless operation of x86 programs.

[0201] Workflow:

[0202] 1. Instruction conversion mechanism:

[0203] The main control module 1 transmits the x86 instruction stream of the computer-side application program to the FPGA chip 211 through the PCIe 4.0 bus;

[0204] The internal logic unit of the FPGA parses the instructions in real time, performs binary translation through a predefined mapping table (storing more than 2000 x86 instructions corresponding to ARM instructions), and generates intermediate code (such as LLVM IR);

[0205] The drive virtualization circuit 212 intercepts system calls (syscall), simulates the response of the x86 device driver, and ensures compatibility when the program calls hardware resources (such as USB device enumeration, display resolution configuration).

[0206] 2. Data interaction path:

[0207] Computer-side peripherals (such as keyboards, mice, USB flash drives) → USB3.0 interface 62 / Type-C interface 63 → main control module 1 → PCIe4.0 bus → FPGA chip 211 instruction conversion → drive virtualization circuit 212 hardware simulation → main control module 1 schedules to the target platform for output.

[0208] Technical solution of the mobile phone-side adaptation sub-module 22

[0209] The mobile phone-side adaptation sub-module 22 is located in the central area of the PCB substrate, and its core components are:

[0210] Protocol conversion chip 221 (model Qualcomm QCA6574): Supports UART / USB dual interfaces, and has an iOS / iPadOS / Android protocol parsing engine built-in to identify the mobile phone-side device type in real time;

[0211] iOS / Android Dual-Protocol Antenna 222: Adopts a serpentine trace layout (line width 0.2mm, line spacing 0.15mm), covers the 2.4GHz / 5.8GHz frequency bands, and is coated with a nano-conductive coating on the surface (thickness 5μm) to enhance signal reception sensitivity.

[0212] Workflow:

[0213] 1. Device Connection and Protocol Identification:

[0214] The mobile device connects to the wireless communication module 7 via Bluetooth 5.2 or Wi-Fi 6, and the signal is transmitted to the protocol conversion chip 221 through the WiFi6 chipset 71 / Bluetooth 5.2 chipset 72;

[0215] The chip analyzes the device handshake packet (such as the Bonjour protocol for iOS and the ADB protocol for Android), and automatically switches to the corresponding communication mode:

[0216] iOS device: Enables the MTP protocol (Media Transfer Protocol), supports two-way transmission of photo and video files, and simultaneously performs screen mirroring via AirPlay;

[0217] Android device: Enables the ADB debugging protocol, supports application installation, screen mirroring, and device control (such as power on / off instructions).

[0218] 2. Data Format Conversion:

[0219] The APK / IPA installation package transmitted from the mobile device → protocol conversion chip 221 → analyzes the file format and encapsulates it into an installation package format recognizable by the TV box (such as DEB / RPM), and is sent to the main control module 1 via the PCIe 4.0 bus for installation and deployment.

[0220] Technical Solution of the TV-Side Adaptation Submodule 23

[0221] The TV-side adaptation submodule 23 is located on the right side of the PCB substrate and is three-dimensionally stacked and packaged using the Through-Silicon Via (TSV) technology:

[0222] HDCP2.3 Encryption Chip 231 (Model Renesas R8J7795): Complies with the HDMI Forum HDCP 2.3 standard, supports an encrypted transmission rate of 10Gbps, has a built-in 128-bit key generator, and performs AES-128 encryption on the video stream in real time;

[0223] Resolution Scaling Chip 232 (Model Pixelworks PNX8000): Supports intelligent upscaling from 4K to 8K and downscaling from 8K to 4K, and uses the Edge-Adaptive Scaling algorithm to avoid picture quality loss caused by scaling.

[0224] Workflow:

[0225] 1. Ultra-high-definition video processing link:

[0226] The original video stream output by the main control module 1 (resolution range from 1080p to 8K) → PCIe 4.0 bus → resolution scaling chip 232;

[0227] The chip analyzes the video content (such as human edges, text areas), dynamically adjusts the scaling factor (supporting 1:1 to 4:1 pixel interpolation), and generates a video stream with the target resolution (for example, when upgrading 1080p content to 4K, the missing pixels are predicted through AI algorithms);

[0228] The processed video stream enters the HDCP2.3 encryption chip 231, negotiates keys with the display device (KSS handshake process ≤ 50ms), and is output to the TV end through the HDMI interface 61 after encryption.

[0229] 2. Copyright protection and compatibility:

[0230] The encryption chip 231 has a built-in device key database (supporting more than 500 HDMI device IDs) to ensure HDCP compatibility with mainstream TVs and monitors;

[0231] When an unauthorized device is detected, the video stream resolution is automatically reduced to 480p and a watermark is added to protect the content copyright.

[0232] Module coordination and hardware design

[0233] 1. PCB substrate layout:

[0234] The three-platform adaptation sub-modules (21 / 22 / 23) are distributed on the PCB substrate in a parallel architecture, isolated by an insulating layer with a thickness of 2mm (dielectric constant ε = 4.4) to reduce signal crosstalk; the distance between the FPGA chip 211 and the protocol conversion chip 221 is 15mm to avoid mutual influence of high-heat components.

[0235] 2. High-speed data transmission:

[0236] Each adaptation sub-module is connected to the main control module 1 through PCIe 4.0x4 channels (unidirectional bandwidth 4GB / s), supporting simultaneous processing of three types of tasks: running x86 programs on the computer side, file transfer on the mobile phone side, and 8K video decoding on the TV side, with a resource scheduling delay ≤ 10μs.

[0237] 3. Three-dimensional packaging advantages:

[0238] The TSV technology of the TV - side adaptation sub - module 23 realizes vertical inter - connection between chips (via - hole diameter 50μm, aspect ratio 5:1), reducing the PCB occupied area by 60% compared with traditional planar packaging, and at the same time reducing the signal transmission delay (20% reduction year - on - year).

[0239] In an embodiment of the present application, as Figures 1-7 shown, the power supply module 8 includes a lithium - battery pack 81 and a PoE power - supply circuit 82. The lithium - battery pack 81 is located in the bottom chamber of the device housing and is detachably installed by a buckle. The PoE power - supply circuit 82 is integrated with an intelligent switching relay 821, and the coil contact 822 of the relay 821 is directly connected to the GPIO pin of the main control module 1.

[0240] It can be understood that the power supply module 8 is the energy guarantee for the stable operation of the multi - platform TV box. It includes a lithium - battery pack 81 and a PoE power - supply circuit 82. The lithium - battery pack 81 is placed in the bottom chamber of the device housing and is detachably installed by a buckle, which facilitates battery replacement and maintenance. The PoE power - supply circuit 82 is integrated in a specific area of the main board. The intelligent switching relay 821 in it plays a key role in power switching, and its coil contact 822 is directly connected to the GPIO pin of the main control module 1 to achieve precise control of power switching by the main control module 1.

[0241] PoE power - supply working process

[0242] When the device is connected to a network switch or router that supports the PoE function, the PoE power - supply circuit 82 starts to work.

[0243] The specific process is as follows:

[0244] 1. Power - supply detection: The PoE power - supply circuit 82 first detects the presence and validity of the external PoE power supply. It will identify parameters such as the voltage and power of the PoE power supply to ensure that they meet the power - supply requirements of the device.

[0245] 2. Power - supply access: After confirming that the PoE power supply is normal, the PoE power - supply circuit 82 introduces the PoE power supply into the device. At this time, the intelligent switching relay 821 is in a specific state, enabling the PoE power supply to provide power support for each module of the device.

[0246] 3. Power distribution: After the PoE power supply enters the device, it will be distributed to different modules, such as the main control module 1, the multi - platform adaptation module 2, etc., to ensure the normal operation of these modules. At the same time, the PoE power - supply circuit 82 will also manage the charging of the lithium - battery pack 81. When the power of the lithium - battery pack 81 is insufficient, it will automatically charge it.

[0247] Lithium - battery - pack power - supply working process

[0248] When the device is not connected to the PoE power supply or the PoE power supply fails, the lithium battery pack 81 starts to supply power to the device.

[0249] The specific process is as follows:

[0250] 1. Power switch: The main control module 1 determines whether the PoE power supply is working properly by monitoring the state of the PoE power supply circuit 82. When the PoE power supply is detected to be abnormal, the main control module 1 sends a control signal to the coil contact 822 of the intelligent switching relay 821 to change the state of the relay 821, thereby switching the power supply from the PoE power supply to the lithium battery pack 81 for power supply.

[0251] 2. Battery power monitoring: During the power supply process of the lithium battery pack 81, the main control module 1 monitors the power of the lithium battery pack 81 in real time. When the power is lower than a certain threshold, the main control module 1 will send a prompt message to remind the user to connect the PoE power supply to charge the lithium battery pack 81 in time.

[0252] 3. Low power protection: If the power of the lithium battery pack 81 continues to drop to an extremely low level, in order to protect the safety of the battery and the device, the main control module 1 will take further measures, such as turning off some non-critical function modules to reduce power consumption and extend the usage time of the device until it is connected to the PoE power supply for charging.

[0253] Intelligent switching mechanism

[0254] The intelligent switching relay 821 plays a core role in power switching in the power module 8. Its working principle is as follows:

[0255] Normal PoE power supply state: When the PoE power supply is working properly, the main control module 1 sends a specific signal to the coil contact 822 of the intelligent switching relay 821 through the GPIO pin, so that the relay 821 is in the state of conducting the PoE power supply, ensuring that the PoE power supply can smoothly supply power to the device and charge the lithium battery pack 81.

[0256] Switch to the lithium battery power supply state: When the PoE power supply fails or is not connected, after the main control module 1 detects this situation, it will change the signal sent to the coil contact 822, so that the relay 821 switches its state, disconnects the PoE power supply path, and at the same time conducts the power supply path of the lithium battery pack 81, realizing seamless switching of the power supply and ensuring the continuous operation of the device.

[0257] In an embodiment of the present application, as Figures 1-7 shown, the heat-conducting graphite sheet 34 of the GPU acceleration chip 33 extends to the side wall of the device housing, and its edge is provided with wavy heat dissipation teeth with a tooth height of 2 mm and a tooth pitch of 1.5 mm.

[0258] It can be understood that a heat-conducting graphite sheet 34 is closely attached to the surface of the GPU acceleration chip 33. The graphite sheet is made of high-purity carbon material (thermal conductivity ≥ 1500 W / m·K), with a thickness of 0.3 mm, covering the entire surface of the chip and extending to the side wall of the device housing (the extension length is 15 mm). The edge of the graphite sheet is processed with wavy heat dissipation teeth, with a tooth height of 2 mm, a tooth pitch of 1.5 mm, arranged periodically (the number of heat dissipation teeth corresponding to a single chip is ≥ 20), and the distance between the tooth top and the inner side of the housing side wall is ≤ 0.5 mm, forming a direct heat conduction path.

[0259] Heat Conduction Path and Heat Dissipation Mechanism

[0260] 1. Chip-level Heat Export:

[0261] The heat generated during the operation of the GPU acceleration chip 33 (typical power consumption 15 W) is transferred to the heat-conducting graphite sheet 34 through a silicon-based thermal conductive adhesive (thermal resistance ≤ 0.1 °C·cm 2 / W). The graphite sheet utilizes the anisotropic heat conduction characteristics (in-plane heat conduction rate > 1000 W / m·K, in the thickness direction > 50 W / m·K) to quickly diffuse the heat to the entire sheet body.

[0262] 2. Heat Dissipation Tooth Strengthens Convective Heat Dissipation:

[0263] The wavy heat dissipation teeth extending to the side wall of the housing increase the contact area between the graphite sheet and the air (40% increase compared to the planar structure). The tooth shape design optimizes the air flow path: when the device is operating, the natural wind outside the housing or the air flow generated by the built-in fan (components not involved in this paragraph) flows along the gaps between the teeth (tooth pitch 1.5 mm), forming forced convection;

[0264] The tooth height of 2 mm ensures that the heat dissipation teeth penetrate the ventilation holes (hole diameter 3 mm) on the side wall of the housing, directly exporting the heat to the external environment and avoiding accumulation inside the housing (the temperature rise inside the housing ≤ 10 °C when the room temperature is 25 °C).

[0265] In an embodiment of the present application, as Figures 1-7 shown, the iOS / Android dual-protocol antenna 222 adopts a serpentine trace layout, with a line width of 0.2 mm and a line pitch of 0.15 mm, and the operating frequency covers the dual bands of 2.4 GHz / 5.8 GHz.

[0266] It can be understood that the iOS / Android dual-protocol antenna 222 is integrated on the surface of the protocol conversion chip 221 of the mobile phone-side adapter sub-module 22, adopting PCB printed antenna technology, and covering the area above the chip (area 15 mm × 10 mm) with a serpentine trace layout. The trace parameters are:

[0267] The line width is 0.2 mm (meeting the PCB manufacturing process accuracy to ensure stable characteristic impedance);

[0268] The line pitch is 0.15 mm (the adjacent trace pitch, to avoid signal crosstalk and meet the EMC design requirements).

[0269] The antenna is connected to the RF pin of the protocol conversion chip 221 through a gold-plated pad (contact impedance ≤ 50 mΩ), supporting the transceiver of 2.4 GHz / 5.8 GHz dual-band signals.

[0270] Dual-band signal transceiver mechanism

[0271] 1. Frequency band coverage principle:

[0272] For the 2.4 GHz frequency band (wavelength 120 mm): The total length of the serpentine trace is designed as an integer multiple of 1 / 4 wavelength (about 30 mm). The antenna length is equivalently extended in a limited space through a folded serpentine structure to achieve effective radiation and reception of signals in this frequency band;

[0273] For the 5.8 GHz frequency band (wavelength 52 mm): Utilize the segmented resonance characteristics of the serpentine trace. Different line segments are combined to form a 1 / 4 wavelength resonance unit (about 13 mm) to cover the high-frequency band signal transmission.

[0274] 2. Protocol adaptive switching:

[0275] When an iOS device is connected through the Bluetooth / Bonjour protocol, after the protocol conversion chip 221 identifies the device type, it controls the antenna to switch to the 5.8 GHz frequency band (prioritizing high-speed transmission);

[0276] When an Android device is connected through the ADB / MTP protocol, it automatically selects the 2.4 GHz (long distance) or 5.8 GHz (high rate) frequency band according to the signal strength. The antenna adjusts the impedance through a built-in matching circuit (matching accuracy ±5%).

[0277] Advantages of the serpentine trace design

[0278] 1. Optimization of space efficiency:

[0279] The serpentine layout reduces the PCB occupied area by 60% compared with the straight-line antenna, adapting to the compact design of the mobile phone end adapter module 22 (module size 30 mm × 20 mm). At the same time, the current path length is increased through multiple folded lines to improve the radiation efficiency (gain ≥ 2 dBi at 2.4 GHz, gain ≥ 3 dBi at 5.8 GHz).

[0280] 2. Anti-interference design:

[0281] A complete grounding plane (copper foil thickness 35 μm) is laid under the trace, forming electromagnetic isolation with the shield of the protocol conversion chip 221, suppressing the stray radiation below -20 dBm;

[0282] The line pitch is 0.15mm combined with a line width of 0.2mm to ensure that the characteristic impedance is stable at 50Ω (deviation ±2Ω), reducing the signal reflection loss (return loss ≤ -15dB).

[0283] Summary of the work process

[0284] 1. Signal reception process:

[0285] Wireless signal on the mobile phone side (2.4GHz / 5.8GHz) → The dual-protocol antenna 222 senses the electromagnetic signal through serpentine traces → Filtered by the matching circuit → The protocol conversion chip 221 analyzes the iOS / Android protocol → Converted into a data stream recognizable by the device → Transmitted to the main control module 1 through the PCIe bus.

[0286] 2. Signal transmission process:

[0287] The main control module 1 outputs a control signal → The protocol conversion chip 221 encodes it into the corresponding protocol format → The dual-protocol antenna 222 activates the corresponding serpentine trace segment according to the frequency band requirement → The modulated high-frequency signal is radiated to the mobile phone side device through the antenna (transmission distance ≥ 10 meters, bit error rate ≤ 10^-6).

[0288] It should be added that the matching circuit structure: A π-type matching network is added between the RF pin of the protocol conversion chip 221 and the dual-protocol antenna 222, which consists of 2 parallel capacitors (C1 = 1pF, C2 = 2.2pF) and 1 series inductor (L = 3.3nH), adjusting the antenna impedance from 50Ω to the chip input impedance (35 + j10Ω), achieving a standing wave ratio ≤ 1.5 for the 2.4GHz / 5.8GHz dual frequency bands.

[0289] Dynamic tuning mechanism: The chip is built-in with an impedance detection circuit to monitor the antenna reflection coefficient (|S11| ≤ -10dB) in real time, and automatically compensates for the frequency offset by controlling the adjustable capacitor (capacitance range 0.5 - 5pF) through the I 2 C bus.

[0290] It should be noted that the control method of this application can be automatically controlled by a controller. The control method of the controller can be realized by simple programming of those skilled in the art, which belongs to the common knowledge in the art. And this application is mainly used to protect the mechanical structure, so the control method and circuit connection of this application will not be explained in detail.

[0291] Specifically, taking the example that the user uses the device through the computer side, mobile phone side, and TV side at the same time, the specific work process is as follows:

[0292] 1. Device connection and power supply

[0293] TV side: Connect to a 4K TV through the HDMI interface 61. The resolution scaling chip 232 of the TV-side adaptation sub-module 23 automatically detects the TV resolution (such as 3840×2160), and cooperates with the HDCP2.3 encryption chip 231 through the TSV technology to complete signal format adaptation and encryption;

[0294] Computer side: Connect to a Windows laptop through the Type-C composite interface 63. The FPGA chip 211 of the computer-side adaptation sub-module 21 converts x86 instructions into ARM code in real time, and drives the virtualization circuit 212 to simulate the graphics card driver, supporting the computer-side software to be cast to the TV;

[0295] Mobile phone side: Connect to the device through the WiFi6 chipset 71. The AirPlay signal of the iOS mobile phone is received by the dual-protocol antenna 222, and after being parsed by the protocol conversion chip 221, it is transmitted to the main control module 1 through the PCIe bus;

[0296] Power module: The PoE power supply circuit 82 obtains power through the network cable. The intelligent switching relay 821 keeps the PoE power supply path conducting, and the lithium battery pack 81 is in the charging state (if PoE is not connected, it will automatically switch to battery power supply).

[0297] 2. Cross-platform data interaction

[0298] File transfer: The computer side inserts a USB flash drive through the USB3.0 interface 62. The data is transmitted to the main control module 1 through the interface module 6, and then sent to the computer-side adaptation sub-module 21 through the PCIe bus. The virtualization circuit 212 is driven to simulate the USB flash drive driver to realize the file system reading, and finally the file list is displayed on the TV through the TV-side HDMI interface 61;

[0299] Mobile phone screen mirroring: The Android mobile phone sends a video file through the MTP protocol. After being parsed by the protocol conversion chip 221, it is encapsulated into a device-compatible format and transmitted to the main control module 1 through the mobile phone-side adaptation sub-module 22. The GPU acceleration chip 33 of the intelligent recommendation module 3 is called for real-time transcoding (such as upscaling a 1080p video to 4K), and then encrypted by the TV-side adaptation sub-module 23 and output to the TV.

[0300] 3. Intelligent recommendation and user interaction

[0301] Behavior collection: Operations such as the user fast-forwarding a video on the TV side, favoriting content on the mobile phone side, and switching files on the computer side are sampled by the user behavior feature register 31 at a cycle of 500 μs and directly transmitted to the main control module 1 memory through the DMA channel;

[0302] Recommended calculation: The main control module 1 sends the feature data to the recommended result buffer 32. The GPU acceleration chip 33 uses 256 CUDA cores to run the recommendation model in parallel, generates a Top-20 video list, returns it to the main control module 1 via the PCIe bus, and updates it in real time on the TV-side user interface module 5;

[0303] Touch operation: The user adjusts the volume through the capacitive touch sensor 521 at the front end of the device. The electrode array 522 detects the capacitance change. After calculating the coordinates, the touch control circuit board 52 sends them to the main control module 1 via the I2C bus, triggers the volume adjustment instruction, and synchronizes it to the mobile phone side APP for display.

[0304] 4. Cloud synchronization and security verification

[0305] Data upload: The video list collected by the user is sent to the cloud synchronization module 4 via the main control module 1. The physical encryption chip 41 performs AES-256 hardware encryption. Three verification node circuits 421 of the distributed verification node array 42 calculate the SHA-256 hash value in parallel. After reaching a consensus, it is uploaded to the cloud via the WiFi6 chipset 71;

[0306] Data download: The encrypted configuration file obtained from the cloud is first verified for the hash value by the verification node circuit 421, and then decrypted by the physical encryption chip 41 and output to the main control module 1 to update the device settings to ensure that the data has not been tampered with.

[0307] 5. Heat dissipation and power management

[0308] Heat dissipation mechanism: The heat generated during the operation of the GPU acceleration chip 33 is transferred to the thermal graphite sheet 34 through the silicon-based thermal conductive adhesive, and is exported to the ventilation holes on the side wall of the housing through the wavy heat dissipation teeth (tooth height 2mm, tooth pitch 1.5mm) to maintain the chip temperature ≤ 75°C;

[0309] Power switching: If the PoE power supply is abnormal, the main control module 1 controls the intelligent switching relay 821 through the GPIO pin, disconnects the PoE path and conducts the lithium battery pack 81 to ensure the continuous operation of the device, and at the same time displays a low battery warning on the user interface module 5.

[0310] Process summary:

[0311] User operation → Input through the interface module 6 / wireless communication module 7 → Protocol conversion by the multi-platform adaptation module 2 → Scheduling by the main control module 1 → Processing by the intelligent recommendation / cloud synchronization module → Output by the user interface module 5. The whole process is highly interactive through the PCIe 4.0 bus. Each module operates in parallel and cooperates to achieve seamless linkage between the computer side, mobile phone side, and TV side. The signal processing delay ≤ 20ms, meeting the high-efficiency interaction requirements of multiple scenarios.

[0312] In summary, the multi-platform TV box for computer, mobile phone and TV in the embodiments of the present application adopts a three-platform adaptation sub-module with a parallel architecture, realizes x86 instruction conversion, multi-system protocol compatibility and ultra-high-definition video encrypted transmission, supports seamless docking of multiple systems, combines GPU hardware acceleration and DMA data channels to improve the processing speed of the recommendation algorithm, has a dual-power architecture adapted to mobile scenarios, and has a three-dimensional heat dissipation to ensure stable operation under high load, thereby extending the device life.

Claims

1. A multi-platform TV box for computer, mobile phone and TV terminal, characterized in that, It includes a main control module (1), a multi-platform adaptation module (2), an intelligent recommendation module (3), a cloud synchronization module (4), a user interface module (5), an interface module (6), a wireless communication module (7) and a power module (8). Among them, the main control module (1) is fixedly installed on the central substrate of the device housing and is electrically connected to the multi-platform adaptation module (2), the intelligent recommendation module (3), and the cloud synchronization module (4) respectively through a PCIe 4.0 data bus; the multi-platform adaptation module (2) includes a computer-side adaptation sub-module (21), a mobile phone-side adaptation sub-module (22), and a TV-side adaptation sub-module (23). Each adaptation sub-module is integrated on a multi-layer PCB substrate in a parallel architecture, and the PCB substrate is vertically plugged into the main control module (1); the interface module (6) includes an HDMI interface (61), a USB3.0 interface (62), and a Type-C composite interface (63), which are linearly arranged along the rear side wall of the device housing, and the distance between adjacent interfaces is 8-10 mm; the wireless communication module (7) is embedded under the heat dissipation grille at the top of the device housing and includes a WiFi6 chipset (71) and a Bluetooth 5.2 chipset (72), and the two adopt a stacked packaging structure.

2. The multi-platform TV box for computer, mobile phone and TV according to claim 1, characterized in that, the intelligent recommendation module (3) includes a user behavior feature register (31) and a recommendation result buffer (32). The user behavior feature register (31) is connected to the main control module (1) through a DMA channel. The recommendation result buffer (32) is provided with a GPU acceleration chip (33), and the surface of the GPU acceleration chip (33) is covered with a heat-conducting graphite sheet (34) and is thermally connected to the heat dissipation module.

3. The multi-platform TV box for computer, mobile phone and TV according to claim 1, characterized in that the cloud synchronization module (4) includes a physical encryption chip (41) and a distributed verification node array (42). The physical encryption chip (41) is integrated in an independent security isolation area. The distributed verification node array (42) is composed of at least three verification node circuits (421), and each node circuit (421) is arranged in a ring topology on the second layer of the PCB.

4. The multi-platform TV box for computer, mobile phone and TV according to claim 1, characterized in that, the user interface module (5) includes a display driver chip (51) and a touch control circuit board (52). The display driver chip (51) is connected to the main control module (1) through an LVDS interface. The surface of the touch control circuit board (52) is provided with a capacitive touch sensor (521), and its electrode array (522) is staggered at a pitch of 0.5 mm.

5. The multi-platform TV box for computer, mobile phone and TV according to claim 1, characterized in that, the computer-side adaptation sub-module (21) includes an FPGA chip (211) and a drive virtualization circuit (212), and the FPGA chip (211) is programmed with x86 instruction set conversion logic; the mobile phone-side adaptation sub-module (22) integrates a protocol conversion chip (221), and the surface of the chip is provided with an iOS / Android dual-protocol antenna (222); the TV-side adaptation sub-module (23) includes an HDCP2.3 encryption chip (231) and a resolution scaling chip (232), and the two are three-dimensionally stacked and packaged through through-silicon via (TSV) technology.

6. The multi-platform TV box for computer, mobile phone and TV according to claim 1, characterized in that The power supply module (8) includes a lithium battery pack (81) and a PoE power supply circuit (82). The lithium battery pack (81) is located in the bottom chamber of the device housing and is detachably installed by a buckle. The PoE power supply circuit (82) is integrated with an intelligent switching relay (821), and the coil contact (822) of the relay (821) is directly connected to the GPIO pin of the main control module (1).

7. The multi-platform TV box for computer, mobile phone and TV according to claim 2, characterized in that, The heat-conducting graphite sheet (34) of the GPU acceleration chip (33) extends to the side wall of the device housing, and wavy heat dissipation teeth are provided at its edge, with a tooth height of 2 mm and a tooth pitch of 1.5 mm.

8. The multi-platform TV box for computer, mobile phone and TV according to claim 5, characterized in that, The iOS / Android dual-protocol antenna (222) adopts a serpentine trace layout, with a line width of 0.2 mm and a line pitch of 0.15 mm, and the operating frequency covers the dual frequency bands of 2.4 GHz / 5.8 GHz.

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