Low-driving-voltage trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a low-driving-voltage trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a masking layer, a P-type well region, a P-type base region, a P-type source region and an N-type source region; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the N-type source region, metal is deposited, and a source electrode metal layer is formed; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side surface of the masking layer, and depositing to form an insulating dielectric layer; and forming a barrier layer again, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, forming a gate metal layer, removing the barrier layer, completing preparation, reducing the driving voltage of the device, and reducing the driving loss of the device. The device reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a low-drive-voltage trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices inherently have the characteristics of low gate charge and high switching speed compared with Si VDMOS devices. However, due to the relationship between its bandgap width and the bandgap of the insulating medium silicon dioxide, generally speaking, when the gate drive voltage reaches 15V, the silicon carbide VDMOS device can achieve full conduction and achieve the lowest on-resistance. However, due to the poor quality of the insulating medium silicon dioxide, the gate breakdown voltage of the device is small, and the high drive voltage easily leads to gate reliability problems of the device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a low-drive-voltage trench-gate silicon carbide VDMOS and a preparation method thereof, which can achieve full conduction of the device at a gate drive voltage of 12V, reduce the device drive voltage, reduce the device drive loss, and improve the device reliability.

[0004] In a first aspect, the present invention provides a preparation method of a low-drive-voltage trench-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form a through hole, and perform ion implantation to form a masking layer; Step 3: Remove the barrier layer in Step 2, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form a P-type well region; Step 4: Remove the barrier layer in Step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form a P-type base region; Step 5: Remove the barrier layer in Step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form a P-type source region; Step 6: Remove the barrier layer in Step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation to form an N-type source region; Step 7: Remove the barrier layer in Step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the N-type source region, and deposit metal to form a source metal layer; Step 8: Remove the barrier layer in Step 7, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the masking layer, and deposit to form an insulating dielectric layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a via hole, etch the insulating dielectric layer to form a trench, deposit metal to form a gate metal layer, and remove the blocking layer to complete the preparation.

[0005] In a second aspect, the present invention provides a low-drive-voltage trench-gate silicon carbide VDMOS, which is prepared by using the preparation method of a low-drive-voltage trench-gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are as follows: 1. The present invention constructs a P-type base region and a P-type well region with gradually decreasing concentration gradients. The highly doped P-type base region ensures that the space charge region formed between the N-type source region and it does not affect the lateral diffusion of the space charge region towards the device gate in the longitudinal direction, ensuring the gate-controlled turn-off characteristics of the device. The P-type base region shields the space charge region of the N-type source region. The low-doped P-type well region forms a space charge region at the bottom of the P-type base region to ensure the gate turn-off characteristics of the device. When the device withstands reverse voltage, the two-layer P-type doping structure can form a structure with gradually increasing electric field near the N-type source region of the device, improving the withstand voltage ability of the source region of the device. 2. The N-type source region, the P-type base region, and the P-type well region are not directly connected to the insulating dielectric layer. There is a drift layer in between. Space charge regions are formed through the P-type well region and the P-type base region and the drift layer to achieve turn-off during reverse voltage withstand. The gap structure can reduce the drive voltage for inversion, thereby reducing the drive voltage of the device. 3. In order to ensure the gate reliability of the device, a masking layer with the same width as the insulating dielectric is constructed directly below the insulating dielectric layer of the device to avoid the influence on the gate structure of the device during reverse voltage withstand. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0008] Figure 1 It is a schematic diagram of a low-drive-voltage trench-gate silicon carbide VDMOS of the present invention.

[0009] Figure 2 It is a process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 It is a process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS of the present invention Figure 2 .

[0011] Figure 4 It is a process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS of the present invention Figure 3 .

[0012] Figure 5 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 4 .

[0013] Figure 6 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 5 .

[0014] Figure 7 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 6 .

[0015] Figure 8 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 7 .

[0016] Figure 9 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 8 .

[0017] Figure 10 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 9 .

[0018] Figure 11 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 10 .

[0019] Figure 12 Process cross-section of a low-drive-voltage trench-gate silicon carbide VDMOS according to the present invention Figure 10 I. Specific embodiments

[0020] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0023] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0024] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" or the like specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0025] As Figures 1 to 12 shown, an embodiment of the present application provides a method for preparing a low-drive-voltage trench-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: Form a blocking layer 100 above the drift layer 102, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a masking layer 107; Step 3: Remove the blocking layer 100 in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type well region 103; Step 4: Remove the blocking layer 100 in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type base region 104; Step 5: Remove the blocking layer 100 in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type source region 105; Step 6: Remove the blocking layer 100 in Step 5, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 106; Step 7: Remove the blocking layer 100 in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the N-type source region 106, and deposit metal to form a source metal layer 110; Step 8: Remove the blocking layer 100 in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the masking layer 107, and deposit to form an insulating dielectric layer 108; Step 9: Remove the blocking layer 100 in Step 8, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and etch the insulating dielectric layer 108 to form a trench 1081, deposit metal to form a gate metal layer 109, and remove the blocking layer 100 to complete the preparation.

[0026] In this embodiment, preferably, the distance between the inner side of the P-type well region 103 and the outer side of the insulating dielectric layer 108 is greater than the distance between the inner side of the P-type base region 104 and the outer side of the insulating dielectric layer 108.

[0027] In this embodiment, preferably, the lower side of the gate metal layer 109 and the lower side of the P-type well region 103 are in the same plane.

[0028] In this embodiment, preferably, the doping concentration of the P-type base region 104 is greater than the doping concentration of the P-type well region 103.

[0029] In this embodiment, preferably, the doping concentration of the P-type well region 103 is greater than the doping concentration of the drift layer 102.

[0030] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than that of the N-type source region 106.

[0031] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: A silicon carbide substrate 101, A drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101; a protrusion 1021 is provided on the drift layer 102, and a groove (not shown in the figure) is provided in the protrusion 1021; A P-type well region 103, the lower side of the P-type well region 103 is connected to the upper side of the drift layer 102, and the inner side of the P-type well region 103 is connected to the outer side of the protrusion 1021; A P-type base region 104, the lower side of the P-type base region 104 is connected to the upper side of the P-type well region 103, and the inner side of the P-type base region 104 is connected to the outer side of the protrusion 1021; A P-type source region 105, the lower side of the P-type source region 105 is connected to the upper side of the P-type base region 104; An N-type source region 106, the lower side of the N-type source region 106 is connected to the upper side of the P-type base region 104, the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 105, and the inner side of the N-type source region 106 is connected to the outer side of the protrusion 1021; A masking layer 107, the masking layer 107 is disposed in the groove; An insulating dielectric layer 108, the insulating dielectric layer 108 is disposed in the groove, and the lower side of the insulating dielectric layer 108 is connected to the upper side of the masking layer 107; the insulating dielectric layer 108 protrudes from the groove, and a trench 1081 is provided in the insulating dielectric layer 108; A gate metal layer 109, the gate metal layer 109 is disposed in the trench 1081; A source metal layer 110, the source metal layer 110 is respectively connected to the upper side of the protrusion 1021, the upper side of the P-type source region 105, and the upper side of the N-type source region 106; And a drain metal layer 111, the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101.

[0032] In another embodiment of the present invention, the silicon carbide substrate 101 and the drift layer 102 are N-type, and the masking layer 107 is P-type; the doping concentration of the silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentration of the drift layer 102 is 6 - 10e15 cm -3 , and the doping concentration of the masking layer 107 is 1 - 5e16 cm-3 ,The doping concentration of the P-type well region 103 is 1 - 5e17 cm -3 ,The doping concentration of the P-type base region 104 is 1 - 5e18 cm -3 ,The doping concentration of the P-type source region 105 is 1 - 5e19 cm -3 ,The doping concentration of the N-type source region 106 is 2 - 8e18 cm -3 ,The material of the insulating dielectric layer 108 can be silicon dioxide; The doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 111 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration of the masking layer 107 is to improve the reliability of the bottom of the insulating dielectric layer 108 of the device, ensure that the leakage current is small enough when the device is under reverse breakdown voltage, shield the capacitance from the gate to the drain of the device, and reduce the Miller capacitance of the device; the doping concentration design of the P-type well region 103 is to protect the source of the device and ensure the low drive voltage characteristic of the gate control region of the device; the doping concentration of the P-type base region 104 is to reduce the downward extension of the space charge region formed between the N-type source region 106 of the device and it, and ensure the turn-off characteristic of the device; the doping concentration design of the P-type source region 105 is to reduce the loss of the parasitic pn junction body diode of the device; the doping concentration design of the N-type source region 106 and the P-type source region 105 is to reduce the contact resistance of the device, and thus reduce the on-resistance of the device; The thickness of the silicon carbide substrate 101 of the device is 1 μm, which is to ensure the support during the device fabrication process. The thickness of the drift layer 102 is 50 - 100 μm and can be adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the source metal layer 110 of the device is 300 nm, the thickness of the P-type well region 103 is 500 nm, the width is 1.12 μm, the thickness of the P-type base region 104 is 300 nm, the width is 1.15 μm, the thickness of the P-type source region 105 is 200 nm, the width is 600 nm, the thickness of the N-type source region 106 is 200 nm, the width is 550 nm, the width of the device insulating dielectric layer 108 is 1.2 μm, the width of the gate metal layer 109 is 1.1 μm, the thickness of the gate metal layer 109 is 1.4 μm, the thickness of the insulating dielectric at the bottom of the gate metal layer 109 is 100 nm, the width of the insulating dielectric on both the left and right sides of the gate metal layer 109 is 50 nm, the width of the masking layer 107 is 1.2 μm, the thickness is 200 nm. The tops of the N-type source region 106 and the P-type source region 105 are in direct contact with the source metal layer 110. The top of the P-type base region 104 is in direct contact with the N-type source region 106 and the P-type source region 105. The top of the P-type well region 103 is in direct contact with the top of the P-type base region 104. The P-type source region 105, the P-type base region 104, and the P-type well region 103 are aligned on the side away from the device gate. The device masking layer 107 is in direct contact with the bottom of the device insulating dielectric layer 108. The widths, thicknesses, and relative relationships of the above structures are to construct a low drive voltage structure for the device, and their cooperation with the doping concentration can achieve a low drive voltage under low reverse leakage conditions of the device, improving the performance and reliability of the device.

[0033] The present invention constructs a P-type base region 104 and a P-type well region 103 with a gradually decreasing concentration gradient. The highly doped P-type base region 104 ensures longitudinally that the space charge region formed between it and the N-type source region 106 does not affect the lateral space charge region from diffusing towards the device gate, ensuring the gate-controlled turn-off characteristics of the device. The P-type base region 104 shields the space charge region of the N-type source region 106. The space charge region formed by the low-doped P-type well region 103 at the bottom of the P-type base region 104 ensures the gate turn-off characteristics of the device. The P-type base region 104 and the P-type well region 103 with a gradually decreasing concentration gradient can form a structure with a gradually increasing electric field near the N-type source region 106 of the device when the device is reverse biased, improving the breakdown voltage ability of the source region of the device. N-type source regions 106 and P-type base regions 104 are formed on the left and right sides of the device, with a distance of 50 nm from the insulating dielectric layer 108. This part is the drift layer 102. A trapezoidal structure with an increased gap is formed in the P-type well region 103 below the P-type base region 104, with a distance of 80 nm from the insulating dielectric layer 108. This structure forms a space charge region through the P-type well region 103 and the P-type base region 104 with the drift layer 102 in the gap to achieve turn-off during reverse voltage withstand. The gap structure can reduce the drive voltage of the inversion, thereby reducing the drive voltage of the device. This structure is to reduce the drive charge in the part far from the N-type source region 106 and reduce the switching loss; To ensure the gate reliability of the device, a masking layer 107 with a thickness of 200 nm and the same width as the insulating dielectric is constructed directly below the insulating dielectric layer 108 of the device to avoid the influence on the gate structure of the device during reverse voltage withstand.

[0034] Although the specific implementation manners of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a low-drive-voltage trench-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a masking layer; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form a P-type well region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form a P-type base region; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form a P-type source region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form an N-type source region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to the upper side of the N-type source region, deposit metal to form a source metal layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to the upper side of the masking layer, deposit to form an insulating dielectric layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and etch the insulating dielectric layer to form a trench, deposit metal to form a gate metal layer, remove the blocking layer to complete the preparation.

2. The manufacturing method of a low drive voltage trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The distance between the inner side of the P-type well region and the outer side of the insulating dielectric layer is greater than the distance between the inner side of the P-type base region and the outer side of the insulating dielectric layer.

3. The manufacturing method of a low drive voltage trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side of the gate metal layer and the lower side of the P-type well region are in the same plane.

4. The manufacturing method of a low drive voltage trench gate silicon carbide VDMOS as described in claim 1, wherein: The doping concentration of the P-type base region is greater than that of the P-type well region.

5. The manufacturing method of a low-drive-voltage trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is greater than that of the drift layer.

6. The manufacturing method of a low driving voltage trench-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the P-type source region is greater than that of the N-type source region.

7. A low-drive-voltage trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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