Interrupt processing method and device, electronic equipment and storage medium
By introducing fast memory and independent bus optimization interrupt processing flow into the processor, the problem of excessive interrupt response delay is solved, and more efficient interrupt processing and task recovery is achieved.
Patent Information
- Application Number
- CN202510319796.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2025-07-11
AI Technical Summary
Existing processor interrupt response delays are too large, which affects the real-time nature of interrupt processing, especially due to the high read and write delay of DRAM and the additional instruction overhead of register state storage and recovery.
Fast memory (such as SRAM) is used to store interrupt vector tables, interrupt processing functions and interrupt stacks, and priority access is made through independent buses, combined with an extended instruction unit to execute multi-register storage and loading instructions, optimizing the interrupt processing process.
Significantly reduce interrupt response delay, improve interrupt processing efficiency, ensure fast memory critical data access is not disturbed by system bus, and improve interrupt processing real-time and task recovery speed.
Smart Images
Figure CN120295666A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of computer technologies, and in particular, to an interrupt processing method, apparatus, electronic device, and storage medium. Background Art
[0002] Currently, in modern processor architectures, the interrupt mechanism is a key function for the interaction between the processor and peripherals. When the status of a peripheral changes and the processor needs to intervene, an interrupt signal is triggered. After the processor responds to the interrupt, it jumps to the corresponding interrupt handling function for execution according to the configuration of the interrupt vector table. This process involves the generation of the interrupt signal to the execution of the interrupt handling function, including stages such as the search of the interrupt vector table, the reading and execution of the interrupt handling function, and the saving and restoration of the register status.
[0003] In related technologies, the processor usually uses DRAM (Dynamic Random Access Memory) as the main memory. Although DRAM has a large bandwidth, its read and write latency is relatively high, which affects the real-time performance of interrupt processing. In particular, the storage locations of the interrupt vector table and the interrupt handling function in DRAM increase the latency of interrupt response. In addition, when handling interrupts, the registers in the RISC (Reduced Instruction Set Computer) processor need to be saved to the stack, thereby increasing additional instruction overhead and time latency, which further increases the latency of interrupt response. Summary of the Invention
[0004] Embodiments of the present application provide an interrupt processing method, apparatus, electronic device, and storage medium, which can reduce the interrupt response latency of the processor, improve the interrupt processing efficiency, and solve the technical problem of excessive interrupt response latency of the processor.
[0005] In a first aspect, embodiments of the present application provide an interrupt processing method, which is applied to a chip. The chip is configured with a fast memory connected through a bus, and the fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack;
[0006] The method includes:
[0007] When an interrupt signal of the current task is detected, access the fast memory based on the independent bus to obtain the interrupt vector table, obtain a function address based on the interrupt type of the interrupt signal, and obtain the corresponding interrupt handling function as a target function based on the function address;
[0008] Execute a register save instruction, and save the register content of the current task to the interrupt stack based on the register save instruction;
[0009] Execute the target function, and after the execution of the target function is completed, execute a register load instruction to restore the register content saved in the interrupt stack based on the register load instruction.
[0010] Further, the fast memory is a static random access memory, the bus is an independent bus, and the access priority of the independent bus during the interrupt response cycle is higher than that of the system bus.
[0011] Further, the execution of the register save instruction includes:
[0012] Execute the register save instruction based on a preset extended instruction unit;
[0013] The execution of the register load instruction includes:
[0014] Execute the register load instruction based on the extended instruction unit.
[0015] Further, the execution of the register save instruction, which saves the register content of the current task to the interrupt stack based on the register save instruction, includes:
[0016] Execute a multi-register save instruction to save the register content of the current task to the interrupt stack based on the multi-register save instruction;
[0017] The execution of the register load instruction, which restores the register content saved in the interrupt stack based on the register load instruction, includes:
[0018] Execute a multi-register load instruction to restore the register content saved in the interrupt stack based on the multi-register load instruction.
[0019] Further, the execution of the register save instruction, which saves the register content of the current task to the interrupt stack based on the register save instruction, includes:
[0020] Execute a multi-register save instruction based on a preset extended instruction unit to save the register content of the current task to the interrupt stack based on the multi-register save instruction;
[0021] The execution of the target function, and after the execution of the target function is completed, execute a register load instruction to restore the register content saved in the interrupt stack based on the register load instruction, includes:
[0022] Execute the target function, and after the execution of the target function is completed, execute a multi-register load instruction based on the extended instruction unit to restore the register content saved in the interrupt stack based on the multi-register load instruction.
[0023] Further, saving the register content of the current task to the interrupt stack based on the multi-register save instruction includes:
[0024] Performing a register stack save operation on the register content of the current task within a single instruction cycle to save the register content of the current task to the interrupt stack;
[0025] Restoring the register content saved in the interrupt stack based on the multi-register load instruction includes:
[0026] Performing a register stack restore operation on the register content of the current task within a single instruction cycle to restore the register content saved in the interrupt stack.
[0027] Further, the interrupt handling function is a linear instruction sequence without a loop structure. The interrupt handling function is pre-burned into a fixed address segment of the fast memory during compilation, and the storage location of the interrupt vector table points to the fast memory.
[0028] Further, before executing the target function, it further includes:
[0029] Judging whether the task instruction of the current task is a multi-cycle instruction based on a preset instruction execution status detection unit;
[0030] When it is detected that the task instruction of the current task is a multi-cycle instruction and the interrupt priority of the interrupt signal is higher than a set level, enter the execution process of the target function.
[0031] Further, the processor includes a multi-core scheduling module and multiple processor cores;
[0032] Executing the target function includes:
[0033] Selecting a corresponding processor core from multiple processor cores to execute the target function based on the multi-core scheduling module, and the multi-core scheduling module is used to select a processor core based on a load balancing rule or an interrupt type allocation rule.
[0034] Further, the method further includes:
[0035] When no interrupt signal is detected within a set time window, switch the fast memory to run in a set low-power mode, and after detecting an interrupt signal, send a wake-up pulse to the fast memory based on the independent bus to wake up the fast memory.
[0036] In a second aspect, an embodiment of the present application provides another interrupt handling method, including:
[0037] In the case of detecting an interrupt signal of the current task, query the local interrupt vector table, obtain a function address based on the interrupt type of the interrupt signal, and obtain a corresponding interrupt handling function as a target function locally based on the function address;
[0038] Execute a multi-register save instruction, and save the register content of the current task to the local interrupt stack based on the multi-register save instruction;
[0039] Execute the target function, and after the target function is executed, execute a multi-register load instruction, and restore the register content saved in the interrupt stack based on the multi-register load instruction.
[0040] Further, the execution of the multi-register save instruction includes:
[0041] Execute the multi-register save instruction based on a preset extended instruction unit;
[0042] The execution of the multi-register load instruction includes:
[0043] Execute the multi-register load instruction based on the extended instruction unit.
[0044] In a third aspect, an embodiment of the present application provides an interrupt handling device, which is applied to a chip. The chip is configured with a fast memory connected through a bus, and the fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack;
[0045] The device includes:
[0046] An acquisition module, configured to, in the case of detecting an interrupt signal of the current task, access the fast memory based on the independent bus to obtain the interrupt vector table, obtain a function address based on the interrupt type of the interrupt signal, and obtain a corresponding interrupt handling function as a target function based on the function address;
[0047] A save module, configured to execute a register save instruction, and save the register content of the current task to the interrupt stack based on the register save instruction;
[0048] A restore module, configured to execute the target function, and after the target function is executed, execute a register load instruction, and restore the register content saved in the interrupt stack based on the register load instruction.
[0049] In a third aspect, an embodiment of the present application provides an electronic device, including:
[0050] A memory and one or more processors;
[0051] The memory is used to store one or more programs;
[0052] When the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt handling method as described in the first aspect.
[0053] In a fourth aspect, an embodiment of the present application provides a storage medium containing computer-executable instructions, and the computer-executable instructions are used to execute the interrupt handling method as described in the first aspect when executed by a computer processor.
[0054] In the embodiment of the present application, when an interrupt signal of the current task is detected, the interrupt vector table is obtained based on a bus access to a fast memory, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt handling function is obtained based on the function address as the target function; a register save instruction is executed, and based on the register save instruction, the register content of the current task is saved to the interrupt stack; the target function is executed, and after the target function is executed, a register load instruction is executed, and based on the register load instruction, the register content saved in the interrupt stack is restored. By adopting the above technical means, the interrupt vector table and the interrupt handling function can be quickly accessed through the fast memory, which can reduce the initial delay of interrupt response, speed up the task recovery speed after interrupt processing, and improve the interrupt handling efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] Figure 1 is a flowchart of an interrupt handling method provided in Embodiment 1 of the present application;
[0056] Figure 2 is a schematic connection diagram of a processor in Embodiment 1 of the present application;
[0057] Figure 3 is a trigger flowchart for the execution of the target function in Embodiment 1 of the present application;
[0058] Figure 4 is a schematic structural diagram of an interrupt handling device provided in Embodiment 2 of the present application;
[0059] Figure 5 is a schematic structural diagram of an electronic device provided in Embodiment 3 of the present application. DETAILED DESCRIPTION
[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following provides a more detailed description of specific embodiments of this application with reference to the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Additionally, it should be noted that for ease of description, only parts related to this application rather than all content are shown in the drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.
[0061] Embodiment 1:
[0062] Figure 1 The flowchart of an interrupt handling method provided in Embodiment 1 of this application is given. The interrupt handling method provided in this embodiment can be executed by an interrupt handling device, which can be implemented in software and / or hardware. The interrupt handling device can be composed of two or more physical entities or one physical entity. Generally speaking, the interrupt handling device can be a device related to a configured processor.
[0063] The following takes this interrupt handling device as the main body for executing the interrupt handling method for description. Refer to Figure 1 , the processor is connected to the fast memory through a bus, and the fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack;
[0064] This interrupt handling method is applied to a chip and specifically includes:
[0065] S110. When an interrupt signal of the current task is detected, obtain the interrupt vector table by accessing the fast memory based on the bus, obtain the function address based on the interrupt type of the interrupt signal, and obtain the corresponding interrupt handling function as the target function based on the function address;
[0066] S120. Execute a register save instruction, and save the register content of the current task to the interrupt stack based on the register save instruction;
[0067] S130. Execute the target function, and after the target function is executed, execute a register load instruction, and restore the register content saved in the interrupt stack based on the register load instruction.
[0068] This application provides a method for optimizing processor interrupt handling. By introducing a fast memory (such as SRAM, Static Random - Access Memory), it reduces the interrupt response latency and improves the interrupt handling efficiency.
[0069] Specifically, the processor can be connected to the fast memory not only through the system bus but also through an independent bus. The independent bus is designed specifically for the fast memory to avoid sharing the bus bandwidth with the main memory (such as DRAM), thus reducing the access latency. The fast memory is used to store the interrupt vector table, interrupt handling functions, and the interrupt stack. These key data are placed in the fast memory to ensure rapid access when an interrupt occurs. By using the fast memory, the latency of accessing the interrupt vector table, interrupt handling functions, and the interrupt stack is reduced, thereby improving the real - time performance of interrupt handling.
[0070] When the processor detects an interrupt signal for the current task, it first accesses the interrupt vector table in the fast memory through the independent bus. Based on the interrupt type of the interrupt signal, the processor looks up the corresponding function address in the interrupt vector table. Then, the processor obtains the corresponding interrupt handling function as the target function from the fast memory according to the found function address. By quickly accessing the interrupt vector table and the interrupt handling function, the initial latency of interrupt response is reduced.
[0071] Before executing the interrupt handling function, the processor executes a register save instruction to save the register contents of the current task to the interrupt stack. This ensures that the state of the current task can be restored after the interrupt handling is completed. The processor then executes the interrupt handling function (the target function) to handle the interrupt event. This function will perform corresponding operations according to the interrupt type, such as reading data from external devices, updating device status, etc. After the interrupt handling function is executed, the processor executes a register load instruction to restore the previously saved register contents from the interrupt stack. In this way, the processor can continue to execute the interrupted task.
[0072] Optionally, executing the register save instruction includes:
[0073] Executing the register save instruction based on a preset extended instruction unit;
[0074] Executing the register load instruction includes:
[0075] Executing the register load instruction based on the extended instruction unit.
[0076] When the processor detects an interrupt signal and is ready to respond to the interrupt, it will execute the register save instruction through the extended instruction unit. By executing this instruction through the extended instruction unit, it can ensure that the register contents can be quickly and accurately saved to the interrupt stack, reducing the latency of interrupt response.
[0077] Similarly, after the execution of the interrupt handling function, the processor needs to execute a register load instruction through the extended instruction unit. This instruction restores the previously saved register contents from the interrupt stack so that the processor can continue to execute the interrupted task. Executing this instruction through the extended instruction unit can ensure that the register contents can be quickly and accurately restored from the interrupt stack, reducing the restoration latency after interrupt handling. The extended instruction unit is optimized for executing register load and save instructions, so it can execute register save and load instructions more efficiently than the general instruction unit, thereby improving the instruction execution efficiency during the interrupt handling process and further reducing the latency of interrupt response.
[0078] The extended instruction unit can be a processing unit allocated within the processor or a processing module external to the processor for quickly accessing the fast memory, thereby enhancing the interrupt handling efficiency. The present application does not impose a fixed limit on the setting type of the extended instruction unit, so it will not be elaborated here.
[0079] Optionally, executing a register save instruction and saving the register contents of the current task to the interrupt stack based on the register save instruction includes:
[0080] Executing a multi-register save instruction and saving the register contents of the current task to the interrupt stack based on the multi-register save instruction;
[0081] Executing a register load instruction and restoring the register contents saved in the interrupt stack based on the register load instruction includes:
[0082] Executing a multi-register load instruction and restoring the register contents saved in the interrupt stack based on the multi-register load instruction.
[0083] The multi-register save instruction is a special instruction that can save the contents of multiple registers in one operation. During the interrupt handling process, when the processor detects an interrupt signal and is ready to respond to the interrupt, it executes the multi-register save instruction. This instruction saves all the register contents that need to be saved in the current task (such as the program counter, status register, general registers, etc.) to the interrupt stack at once. By executing the multi-register save instruction, the number of instructions and execution time required to save the register contents can be significantly reduced, thereby reducing the latency of interrupt response.
[0084] The interrupt stack is a specific area in the fast memory used to store the register contents that need to be saved during the interrupt handling process. The interrupt stack adopts a multiple register storage structure for storing the register contents.
[0085] When a multi-register save instruction is executed, the contents of all registers to be saved are pushed onto the interrupt stack so that they can be restored after the interrupt handling is completed. The multi-register load instruction is a special instruction that can load the contents of multiple registers from memory in a single operation. After the interrupt handling function has finished executing, the processor needs to restore the previously saved register contents to continue the interrupted task. At this time, the processor executes the multi-register load instruction to load all the register contents to be restored from the interrupt stack at once. By executing the multi-register load instruction, the number of instructions and the execution time required to restore the register contents can be significantly reduced, thereby reducing the restoration latency after interrupt handling.
[0086] By introducing the multi-register save instruction and the multi-register load instruction, the design of the instruction set can be simplified. Thus, fewer instructions can be designed to achieve the same function, reducing the complexity and implementation difficulty of the instruction set.
[0087] Optionally, further, execute the register save instruction, and save the register contents of the current task to the interrupt stack based on the register save instruction, including:
[0088] Execute the multi-register save instruction based on a preset extended instruction unit, and save the register contents of the current task to the interrupt stack based on the multi-register save instruction;
[0089] Execute the target function, and after the target function has finished executing, execute the register load instruction, and restore the register contents saved in the interrupt stack based on the register load instruction, including:
[0090] Execute the target function, and after the target function has finished executing, execute the multi-register load instruction based on the extended instruction unit, and restore the register contents saved in the interrupt stack based on the multi-register load instruction.
[0091] Different from the above method of separately using the extended instruction unit and the multi-register instruction, the present application can also execute the above multi-register load and save instructions based on the extended instruction unit, thereby further improving the interrupt handling efficiency.
[0092] Among them, the chip includes a processor and a fast memory. Refer to Figure 2, the processor 11 is configured with an independent bus 111, an extended instruction unit 112, and a system bus 113. The processor 11 is connected to the fast memory 12 through the independent bus 111, and combined with the extended instruction unit 12 to implement the interrupt handling method of the present application. For other regular operations of the processor, they are executed by connecting to a dynamic random access memory (such as DRAM) 13 through the system bus 113. Optionally, the processor may generally be a CPU (Central Processing Unit), an MCU (Microcontroller Unit), etc. Generally speaking, a CPU does not include a memory inside, so there are a memory and a fast memory in the peripherals. Regular operations are implemented based on the memory, and interrupt handling is performed based on the fast memory. For an MCU, interrupt handling is performed through the fast memory of the peripherals, and its regular operations are implemented through local storage.
[0093] Before preparing to execute the target function, the processor uses a preset extended instruction unit to execute a multi-register save instruction. The multi-register save instruction saves the contents of multiple registers of the current task into the interrupt stack in the fast memory at one time. By using the multi-register save instruction, the number of instructions and time required to save the register contents are reduced, thereby reducing the additional overhead of interrupt handling.
[0094] After that, the processor starts to execute the target function (i.e., the interrupt handling function) obtained from the interrupt vector table. The execution of the target function solves the problem caused by the change in the peripheral state, thereby restoring the normal operation of the system. After the target function is executed, the processor uses the extended instruction unit again to execute a multi-register load instruction. The multi-register load instruction restores the previously saved register contents from the interrupt stack at one time. By using the multi-register load instruction, the number of instructions and time required to restore the register contents are reduced, thereby accelerating the task recovery speed after interrupt handling.
[0095] Based on the above interrupt handling method, the processor can significantly reduce the interrupt response latency and improve the interrupt handling efficiency. The use of the fast memory reduces the access latency of critical data, while the multi-register save and load instructions of the extended instruction unit reduce the additional overhead during the interrupt handling process. Thus, they jointly enhance the interrupt handling ability, enabling it to respond and handle interrupts more efficiently.
[0096] Exemplarily, based on the above method, in the application of an anti-lock braking system (ABS) in an automobile, the emergency stop accuracy of the automobile can be greatly improved through a lower interrupt response latency, thereby avoiding traffic accidents; in the emergency stop scenario of an industrial robot, by reducing the interrupt response latency, it is possible to avoid the situation where the displacement error of the robotic arm exceeds the limit during shutdown due to excessive latency, thereby avoiding production accidents.
[0097] Based on the above embodiments, optionally, the fast memory is a static random access memory, the bus is an independent bus, and the access priority of the independent bus during the interrupt response cycle is higher than that of the system bus.
[0098] This application uses SRAM as the fast memory, which has faster read and write speeds compared to DRAM. In the interrupt handling scenario, this speed advantage is particularly important. The high speed of SRAM ensures fast access to the interrupt vector table, interrupt handling functions, and interrupt stack, further reducing the interrupt response latency. In addition, the fast memory can also be a phase change memory (PCM), a magnetic random access memory (MRAM), or other storage devices with fast storage functions. This application does not impose a fixed limit on the selected type of fast memory and will not elaborate further here.
[0099] In addition, during the interrupt response cycle, the independent bus is given a higher access priority than the system bus. This means that when an interrupt occurs, the processor can access the SRAM through the independent bus faster. The high priority ensures that the access to critical data during the interrupt handling process will not be blocked by other system tasks, thereby improving the real-time performance of the interrupt handling.
[0100] Optionally, based on the multi-register save instruction, saving the register content of the current task to the interrupt stack includes:
[0101] Performing a register stack save operation on the register content of the current task within a single instruction cycle to save the register content of the current task to the interrupt stack;
[0102] Based on the multi-register load instruction, restoring the register content saved in the interrupt stack includes:
[0103] Performing a register stack restore operation on the register content of the current task within a single instruction cycle to restore the register content saved in the interrupt stack.
[0104] By designing the multi-register save instruction and load instruction to complete all register save and restore operations within a single instruction cycle, the context switch time during the interrupt handling process is further reduced, and the efficiency of the interrupt handling is further improved.
[0105] Optionally, the interrupt handling function is a linear instruction sequence without a loop structure. The interrupt handling function is pre-burned into a fixed address segment of the fast memory during compilation, and the storage location of the interrupt vector table points to the fast memory.
[0106] The interrupt handling function is compiled into a linear instruction sequence without loops and pre-burned into a fixed address segment of the SRAM, and the interrupt vector table directly points to these addresses. The linear instruction sequence without loops simplifies the interrupt handling process, reduces potential branch prediction failures and pipeline stalls, and at the same time, pre-burning into fixed addresses also speeds up the access speed of the interrupt handling function.
[0107] Optionally, referring to Figure 3 , before executing the target function, it further includes:
[0108] S1001. Based on a preset instruction execution status detection unit, determine whether the task instruction of the current task is a multi-cycle instruction;
[0109] S1002. When it is detected that the task instruction of the current task is a multi-cycle instruction and the interrupt priority of the interrupt signal is higher than the set level, enter the execution process of the target function.
[0110] The processor includes a preset instruction execution status detection unit for determining whether the task instruction of the current task is a multi-cycle instruction. If the task instruction of the current task is a multi-cycle instruction and the interrupt priority of the interrupt signal is higher than the set level, the processor will interrupt the current task and enter the execution process of the target function. Thus, through the priority mechanism, it is ensured that high-priority interrupts can be responded to in a timely manner, even when the current task is executing a multi-cycle instruction.
[0111] In one embodiment, the processor includes a multi-core scheduling module and multiple processor cores;
[0112] Executing the target function includes:
[0113] Based on the multi-core scheduling module, select the corresponding processor core from multiple processor cores to execute the target function. The multi-core scheduling module is used to select the processor core based on the load balancing rule or the interrupt type allocation rule.
[0114] In the architecture of the processor, the multi-core scheduling module and multiple processor cores cooperate together to improve the computing efficiency and performance. Among them, the multi-core scheduling module: is responsible for managing and scheduling the allocation of tasks or threads among multiple processor cores. To optimize system performance, ensure load balancing, reduce waiting time, and improve response speed. The processor core is an independent computing unit in the processor, and each core can execute instructions and process data. A multi-core processor can process multiple tasks simultaneously, improving the overall computing efficiency.
[0115] When a target function needs to be executed, the multi-core scheduling module will select the most suitable processor core to execute the function according to certain rules. These rules include the load balancing rule and the interrupt type allocation rule.
[0116] For load balancing rules, it can ensure that the workloads of all processor cores are relatively balanced, avoiding overloading of some cores while other cores are idle. The scheduling module monitors the current load conditions of each processor core and allocates new tasks or threads to the cores with lighter loads based on this information.
[0117] For interrupt type allocation rules, the interrupt handling tasks can be allocated to the most suitable processor core according to the type and priority of the interrupt. Some interrupts may require quick response, while other interrupts may not be so urgent. The scheduling module can allocate the interrupt handling tasks to the core that can respond the fastest according to the priority and type of the interrupt, or allocate them to the core dedicated to handling specific types of interrupts.
[0118] When there is a new task (i.e., the objective function) to be executed, the task is submitted to the multi-core scheduling module. The multi-core scheduling module selects the most suitable core from multiple processor cores to execute the task according to the load balancing rules or interrupt type allocation rules. The selected processor core starts to execute the objective function, processes the relevant data, and generates results. After the execution is completed, the results are returned to the entity that requested the execution of the task (which may be another function, process, or thread).
[0119] Through this mechanism, the multi-core processor can efficiently manage multiple tasks, ensuring that the system performance is maximally utilized. At the same time, this flexibility also enables the system to adapt to different workloads and interrupt types, thus providing more stable and reliable services.
[0120] In one embodiment, the above interrupt handling method further includes:
[0121] In the case where no interrupt signal is detected within a set time window, switch the fast memory to the set low-power mode for operation, and after detecting the interrupt signal, send a wake-up pulse to the fast memory based on an independent bus to wake up the fast memory.
[0122] It can be understood that in order to optimize energy consumption, the processor can adopt an intelligent power management strategy. Within a set time window, if the system does not detect any interrupt signals, the processor will automatically switch the fast memory (such as SRAM) to the low-power mode to reduce unnecessary energy consumption. The low-power mode is very beneficial for extending the device battery life or reducing the overall energy consumption. Once an interrupt signal is detected, the processor will respond quickly and send a wake-up pulse to the fast memory through an independent bus to ensure that it can immediately recover from the low-power mode and be ready to handle the upcoming interrupt tasks. Through this mechanism, it can be ensured that the processor achieves a balance between energy saving and real-time response.
[0123] Optionally, the above extended instruction unit includes:
[0124] The NMI-specific context saving instruction set automatically skips the regular register saving process when a non-maskable interrupt is triggered, directly uses a reduced register set to execute the emergency handler, and after the processing is completed, the skipped register states are automatically restored by the hardware.
[0125] The NMI-specific context saving instruction set is designed specifically for non-maskable interrupts (NMIs). When triggered, it skips the regular register saving process and directly uses a reduced register set to execute the emergency handler. This significantly reduces the response time of NMIs and avoids the cumbersome register saving steps. After the processing is completed, the hardware automatically restores the skipped register states to ensure system stability.
[0126] Optionally, the present application also implements a priority dynamic adjustment mechanism through the interrupt management unit. According to the interrupt history response delay data, the priority weights of each interrupt source are dynamically adjusted through a machine learning model, and the priority levels of the interrupt types with consecutive timeout responses are automatically increased by 2 priority levels.
[0127] Through the interrupt management unit and the machine learning model, the priority weights of each interrupt source are dynamically adjusted according to the interrupt history response delay data. The priority levels of the interrupt types with consecutive timeout responses are automatically increased, thus optimizing the interrupt handling order, reducing the waiting time of high-priority interrupts, and improving the overall response speed and real-time performance of the system.
[0128] Optionally, integration of a fast memory module:
[0129] An MSI (message-based interrupt) dedicated buffer. After receiving the interrupt message packet from the PCIe device, it directly parses and generates a virtual interrupt vector, avoiding the forwarding delay of more than 3 levels caused by the participation of the traditional interrupt controller.
[0130] Through the MSI dedicated buffer integrated in the fast memory module, after receiving the interrupt message packet from the PCIe device, it directly parses and generates a virtual interrupt vector, which can avoid the multi-level forwarding delay of the traditional interrupt controller, reduce the interrupt handling delay, and improve the response speed of the system.
[0131] In addition, before executing the interrupt handling function, the present application also includes:
[0132] The instruction prefetch unit preloads the interrupt service routine instructions at adjacent addresses into the instruction buffer of the fast memory to ensure that the instruction hit rate of the interrupt handling process is not less than 98%.
[0133] After the interrupt handling is completed, it also includes:
[0134] The activation state of the fast memory is maintained for an additional 2 - 5 clock cycles through the delayed return mechanism to ensure that the subsequent possible nested interrupts can directly reuse the current storage context.
[0135] Before executing the interrupt handling function, the instruction prefetch unit preloads the interrupt service routine instructions at adjacent addresses into the instruction buffer of the fast memory, which can improve the instruction hit rate of the interrupt handling process, reduce the situation of instruction cache misses, and thus speed up the interrupt handling speed.
[0136] After the interrupt handling is completed, the activation state of the fast memory is maintained for an additional 2 - 5 clock cycles through the delayed return mechanism. This ensures that subsequent possible nested interrupts can directly reuse the current storage context, avoiding the additional time required for re - activating and loading the context. Thereby, the processing efficiency of nested interrupts is improved, and the overall system response delay is reduced.
[0137] As described above, when an interrupt signal of the current task is detected, the interrupt vector table is obtained by accessing the fast memory based on an independent bus, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt handling function is obtained based on the function address as the target function; the register save instruction is executed, and based on the register save instruction, the register content of the current task is saved to the interrupt stack; the target function is executed, and after the target function is executed, the register load instruction is executed, and based on the register load instruction, the register content saved in the interrupt stack is restored. By adopting the above technical means, the fast memory can quickly access the interrupt vector table and the interrupt handling function, which can reduce the initial delay of interrupt response, and by using multi - register save and load instructions to save the register content to the interrupt stack of the fast memory and restore it from the interrupt stack, the number of instructions and time required to save and restore the register content are reduced, the additional overhead of interrupt handling is reduced, the task recovery speed after interrupt handling is accelerated, and the interrupt handling efficiency is improved.
[0138] Based on the above - mentioned embodiment, the present application also provides another interrupt handling method. When an interrupt signal of the current task is detected, the local interrupt vector table is queried, the function address is obtained based on the interrupt type of the interrupt signal, and the corresponding interrupt handling function is obtained locally based on the function address as the target function;
[0139] The multi - register save instruction is executed, and based on the multi - register save instruction, the register content of the current task is saved to the local interrupt stack;
[0140] The target function is executed, and after the target function is executed, the multi - register load instruction is executed, and based on the multi - register load instruction, the register content saved in the interrupt stack is restored.
[0141] Different from the above-mentioned interruption handling method, the present application can also use local storage (i.e., main memory, such as DRAM) to store the interrupt vector table, interrupt handling function, and interrupt stack. At the same time, in order to improve the interrupt handling efficiency, multi-register save instructions and multi-register load instructions are adopted to save and load the content of the current task registers, so as to simplify the design of the instruction set by introducing multi-register save instructions and multi-register load instructions, and to achieve the same function by designing fewer instructions, reducing the complexity and implementation difficulty of the instruction set.
[0142] Further, executing the multi-register save instruction includes:
[0143] Executing the multi-register save instruction based on a preset extended instruction unit;
[0144] Executing the multi-register load instruction includes:
[0145] Executing the multi-register load instruction based on the extended instruction unit.
[0146] On this basis, by executing the multi-register save instruction and multi-register load instruction through the extended instruction unit, it can be ensured that the register content can be quickly and accurately restored from the interrupt stack, reducing the recovery delay after interruption handling. The extended instruction unit is optimized for executing register load and save instruction operations, so it can execute register save and load instructions more efficiently than the general instruction unit, thereby improving the execution efficiency of instructions during the interrupt handling process and further reducing the delay of interrupt response.
[0147] Embodiment 2:
[0148] Based on the above embodiment, Figure 4 This is a schematic structural diagram of an interrupt handling device provided in Embodiment 2 of the present application. Among them, the device is applied to a chip, and the chip is configured with a fast memory connected through a bus. The fast memory is used to store the interrupt vector table, interrupt handling function, and interrupt stack; referring to Figure 5 This embodiment provides an interrupt handling device specifically including:
[0149] An acquisition module 21, configured to, when detecting an interrupt signal of the current task, access the fast memory based on an independent bus to obtain the interrupt vector table, obtain the function address based on the interrupt type of the interrupt signal, and obtain the corresponding interrupt handling function as the target function;
[0150] A save module 22, configured to execute a register save instruction, and save the content of the current task registers to the interrupt stack based on the register save instruction;
[0151] The restoration module 23 is configured to execute the target function, and after the target function is executed, execute a register loading instruction to restore the register content saved in the interrupt stack based on the register loading instruction.
[0152] Specifically, the fast memory is a static random access memory, and the bus is an independent bus. The access priority of the independent bus is higher than that of the system bus during the interrupt response cycle.
[0153] Specifically, executing the register save instruction includes:
[0154] Executing the register save instruction based on a preset extended instruction unit;
[0155] Executing the register loading instruction includes:
[0156] Executing the register loading instruction based on the extended instruction unit.
[0157] Specifically, executing the register save instruction to save the register content of the current task to the interrupt stack based on the register save instruction includes:
[0158] Executing a multi-register save instruction to save the register content of the current task to the interrupt stack based on the multi-register save instruction;
[0159] Executing the register loading instruction to restore the register content saved in the interrupt stack based on the register loading instruction includes:
[0160] Executing a multi-register loading instruction to restore the register content saved in the interrupt stack based on the multi-register loading instruction.
[0161] Specifically, executing the register save instruction to save the register content of the current task to the interrupt stack based on the register save instruction includes:
[0162] Executing a multi-register save instruction based on a preset extended instruction unit to save the register content of the current task to the interrupt stack based on the multi-register save instruction;
[0163] Executing the target function, and after the target function is executed, execute a register loading instruction to restore the register content saved in the interrupt stack based on the register loading instruction includes:
[0164] Executing the target function, and after the target function is executed, executing a multi-register loading instruction based on the extended instruction unit to restore the register content saved in the interrupt stack based on the multi-register loading instruction.
[0165] Specifically, saving the register content of the current task to the interrupt stack based on the multi-register save instruction includes:
[0166] Perform a register stack save operation on the register contents of the current task within a single instruction cycle, and save the register contents of the current task to the interrupt stack;
[0167] Restore the register contents saved in the interrupt stack based on a multi-register load instruction, including:
[0168] Perform a register stack restore operation on the register contents of the current task within a single instruction cycle to restore the register contents saved in the interrupt stack.
[0169] Specifically, the interrupt handling function is a linear instruction sequence without a loop structure. The interrupt handling function is pre-burned into a fixed address segment of the fast memory during compilation, and the storage location of the interrupt vector table points to the fast memory.
[0170] Specifically, before executing the target function, it further includes:
[0171] Based on a preset instruction execution status detection unit, determine whether the task instruction of the current task is a multi-cycle instruction;
[0172] When it is detected that the task instruction of the current task is a multi-cycle instruction and the interrupt priority of the interrupt signal is higher than the set level, enter the execution process of the target function.
[0173] Specifically, the processor includes a multi-core scheduling module and multiple processor cores;
[0174] Executing the target function includes:
[0175] Based on the multi-core scheduling module, select the corresponding processor core from multiple processor cores to execute the target function. The multi-core scheduling module is used to select the processor core based on the load balancing rule or the interrupt type allocation rule.
[0176] Specifically, the method further includes:
[0177] When no interrupt signal is detected within the set time window, switch the fast memory to run in the set low-power mode, and after detecting the interrupt signal, send a wake-up pulse to the fast memory based on the independent bus to wake up the fast memory.
[0178] As described above, when an interrupt signal of the current task is detected, an interrupt vector table is obtained by accessing a fast memory based on an independent bus, a function address is obtained based on the interrupt type of the interrupt signal, and a corresponding interrupt handling function is obtained based on the function address as the target function; a register save instruction is executed, and based on the register save instruction, the register content of the current task is saved to the interrupt stack; the target function is executed, and after the execution of the target function is completed, a register load instruction is executed, and based on the register load instruction, the register content saved in the interrupt stack is restored. By adopting the above technical means, the interrupt vector table and the interrupt handling function can be quickly accessed through the fast memory, so as to reduce the initial delay of interrupt response, and by using multiple register save and load instructions to save the register content to the interrupt stack of the fast memory and restore it from the interrupt stack, the number of instructions and time required to save and restore the register content are reduced, the additional overhead of interrupt handling is reduced, the task recovery speed after interrupt handling is accelerated, and the interrupt handling efficiency is improved.
[0179] The interrupt handling device provided in the second embodiment of the present application can be used to execute the interrupt handling method provided in the first embodiment, and has corresponding functions and beneficial effects.
[0180] Embodiment Three:
[0181] The third embodiment of the present application provides an electronic device. Referring to Figure 5 , the electronic device includes: a processor 31, a memory 32, a communication module 33, an input device 34, and an output device 35. The number of processors in the electronic device can be one or more, and the number of memories in the electronic device can be one or more. The processor, memory, communication module, input device, and output device of the electronic device can be connected through a bus or other means.
[0182] As a computer-readable storage medium, the memory can be used to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the interrupt handling method described in any embodiment of the present application (for example, the acquisition module, save module, and restore module in the interrupt handling device). The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the device. In addition, the memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some instances, the memory can further include a memory remotely set relative to the processor, and these remote memories can be connected to the device through a network. Examples of the above network include, but are not limited to, the Internet, an enterprise internal network, a local area network, a mobile communication network, and combinations thereof.
[0183] The communication module is used for data transmission.
[0184] The processor executes various functional applications and data processing of the device by running software programs, instructions, and modules stored in the memory, that is, the above-mentioned interrupt processing method is implemented.
[0185] The input device can be used to receive input digital or character information, and generate key signal inputs related to the user settings and function control of the device. The output device may include display devices such as a display screen.
[0186] The above-provided electronic device can be used to execute the interrupt processing method provided in the first embodiment, and has corresponding functions and beneficial effects.
[0187] Embodiment 4:
[0188] The embodiment of the present application further provides a storage medium containing computer-executable instructions. The computer-executable instructions are used to execute an interrupt processing method when executed by a computer processor. This method is applied to a chip, and the chip is configured with a fast memory connected by a bus. The fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack;
[0189] The interrupt processing method includes: when an interrupt signal of the current task is detected, obtaining the interrupt vector table by accessing the fast memory based on an independent bus, obtaining the function address based on the interrupt type of the interrupt signal, and obtaining the corresponding interrupt handling function as the target function based on the function address; executing a register save instruction, and saving the register content of the current task to the interrupt stack based on the register save instruction; executing the target function, and after the target function is executed, executing a register load instruction, and restoring the register content saved in the interrupt stack based on the register load instruction.
[0190] Storage medium - Any of various types of memory devices or storage devices. The term "storage medium" is intended to include: installation media such as CD-ROM, floppy disk or magnetic tape devices; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media (such as hard disks or optical storage); registers or other similar types of memory elements, etc. The storage medium may also include other types of memory or combinations thereof. Additionally, the storage medium may be located in the first computer system in which the program is executed, or may be located in a different second computer system that is connected to the first computer system via a network (such as the Internet). The second computer system may provide program instructions to the first computer for execution. The term "storage medium" may include two or more storage media residing in different locations (e.g., in different computer systems connected via a network). The storage medium may store program instructions executable by one or more processors (e.g., embodied as a computer program).
[0191] Of course, for a storage medium containing computer-executable instructions provided in an embodiment of the present application, the computer-executable instructions are not limited to the interruption processing method described above, and may also execute related operations in the interruption processing method provided in any embodiment of the present application.
[0192] The interruption processing device, storage medium, and electronic device provided in the above embodiments can execute the interruption processing method provided in any embodiment of the present application. For technical details not described in detail in the above embodiments, reference can be made to the interruption processing method provided in any embodiment of the present application.
[0193] The above is only the preferred embodiment of the present application and the technical principles applied. The present application is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions that can be made by those skilled in the art will not depart from the protection scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments. Without departing from the concept of the present application, it may include more other equivalent embodiments, and the scope of the present application is determined by the scope of the claims.
Claims
1. An interrupt handling method, which is applied to a chip, characterized in that, The chip is configured with a fast memory connected by a bus, and the fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack; The method includes: When an interrupt signal of the current task is detected, accessing the fast memory based on the independent bus to obtain the interrupt vector table, obtaining a function address based on the interrupt type of the interrupt signal, and obtaining the corresponding interrupt handling function as a target function based on the function address; Execute a register save instruction, and save the register content of the current task to the interrupt stack based on the register save instruction; Execute the target function, and after the target function is executed, execute a register load instruction, and restore the register content saved in the interrupt stack based on the register load instruction.
2. The interruption processing method according to claim 1, wherein The fast memory is a static random access memory, the bus is an independent bus, and the access priority of the independent bus during the interrupt response cycle is higher than that of the system bus.
3. The interruption processing method according to claim 1, characterized in that, The execution of the register save instruction includes: Executing a register save instruction based on a preset extended instruction unit; The execution of the register load instruction includes: Executing a register load instruction based on the extended instruction unit.
4. The interruption handling method according to claim 1, wherein The execution of the register save instruction, and saving the register content of the current task to the interrupt stack based on the register save instruction, includes: Executing a multi-register save instruction, and saving the register content of the current task to the interrupt stack based on the multi-register save instruction; The execution of the register load instruction, and restoring the register content saved in the interrupt stack based on the register load instruction, includes: Executing a multi-register load instruction, and restoring the register content saved in the interrupt stack based on the multi-register load instruction.
5. The interruption handling method according to claim 1, wherein, The execution of the register save instruction, and saving the register content of the current task to the interrupt stack based on the register save instruction, includes: Executing a multi-register save instruction based on a preset extended instruction unit, and saving the register content of the current task to the interrupt stack based on the multi-register save instruction; The execution of the target function, and after the target function is executed, executing a register load instruction, and restoring the register content saved in the interrupt stack based on the register load instruction, includes: Executing the target function, and after the target function is executed, executing a multi-register load instruction based on the extended instruction unit, and restoring the register content saved in the interrupt stack based on the multi-register load instruction.
6. The interrupt handling method according to claim 4 or 5, characterized in that The saving of the register content of the current task to the interrupt stack based on the multi-register save instruction includes: Performing a register stack save operation on the register content of the current task within a single instruction cycle, and saving the register content of the current task to the interrupt stack; The restoring of the register content saved in the interrupt stack based on the multi-register load instruction includes: Performing a register stack restore operation on the register content of the current task within a single instruction cycle, and restoring the register content saved in the interrupt stack.
7. The interruption handling method according to claim 1, characterized in that The interrupt handling function is a linear instruction sequence without a loop structure. The interrupt handling function is pre-burned into a fixed address segment of the fast memory during compilation, and the storage location of the interrupt vector table points to the fast memory.
8. The interrupt handling method according to claim 1, wherein Before executing the target function, it further includes: Based on a preset instruction execution status detection unit, determining whether the task instruction of the current task is a multi-cycle instruction; When it is detected that the task instruction of the current task is a multi-cycle instruction and the interrupt priority of the interrupt signal is higher than a set level, entering the execution process of the target function.
9. The interrupt handling method according to claim 1, wherein The processor includes a multi-core scheduling module and multiple processor cores; Executing the target function includes: Based on the multi-core scheduling module, selecting a corresponding processor core from multiple processor cores to execute the target function, and the multi-core scheduling module is used to select a processor core based on a load balancing rule or an interrupt type allocation rule.
10. The interrupt handling method according to claim 1, characterized in that, The method further includes: When no interrupt signal is detected within a set time window, switching the fast memory to a set low-power mode for operation, and after detecting an interrupt signal, sending a wake-up pulse to the fast memory based on the independent bus to wake up the fast memory.
11. An interrupt handling method, characterized in that, Includes: When detecting an interrupt signal of the current task, querying the local interrupt vector table, obtaining a function address based on the interrupt type of the interrupt signal, and obtaining a corresponding interrupt handling function as the target function locally based on the function address; Executing a multi-register save instruction, and saving the register content of the current task to the local interrupt stack based on the multi-register save instruction; Executing the target function, and after the target function is executed, executing a multi-register load instruction, and restoring the register content saved in the interrupt stack based on the multi-register load instruction.
12. The interrupt handling method according to claim 11, wherein Executing the multi-register save instruction includes: Executing a multi-register save instruction based on a preset extended instruction unit; Executing the multi-register load instruction includes: Executing a multi-register load instruction based on the extended instruction unit.
13. An interrupt handling device, characterized in that The device is applied to a chip, and the chip is configured with a fast memory connected through a bus. The fast memory is used to store an interrupt vector table, an interrupt handling function, and an interrupt stack; The device includes: An acquisition module, configured to, when detecting an interrupt signal of the current task, access the fast memory based on the independent bus to obtain the interrupt vector table, obtain a function address based on the interrupt type of the interrupt signal, and obtain a corresponding interrupt handling function as the target function based on the function address; A saving module, configured to execute a register save instruction, and save the register content of the current task to the interrupt stack based on the register save instruction; A restoring module, configured to execute the target function, and after the target function is executed, execute a register load instruction, and restore the register content saved in the interrupt stack based on the register load instruction.
14. An electronic device, characterized in that, Includes: A memory and one or more processors; The memory is used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt handling method according to any one of claims 1-12.
15. A storage medium containing computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the interrupt handling method according to any one of claims 1-12 when executed by a computer processor.