P-channel heterojunction field effect transistor of groove gate structure 3C / 4H-SiC and preparation method of P-channel heterojunction field effect transistor
By using groove gate structure and heterojunction to form a high-concentration two-dimensional hole gas conductive channel in SiC devices, the problem of low mobility caused by gate oxide layer defects in SiC devices is solved, and the preparation of high-performance P-channel SiC devices is realized.
Patent Information
- Application Number
- CN202510437684.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2025-07-11
AI Technical Summary
The defects in the gate oxide layer of existing SiC devices lead to a reduced channel carrier density and low mobility, limiting the development of SiC devices.
A P-channel heterojunction field effect transistor with groove gate structure 3C/4H-SiC is used to form a high-concentration two-dimensional hole gas as a conductive channel by using 3C-SiC and 4H-SiC heterojunctions. The interfacial charge trap is reduced by forming a groove gate structure in the epitaxial layer, and hole mobility is improved.
It improves hole mobility, enhances the gate control ability to channel current, reduces the damage to the device by the process, and improves device performance.
Smart Images
Figure CN120302670A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor devices, and particularly to a P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC and a method for manufacturing the same. Background Art
[0002] Silicon carbide (SiC) materials have the advantages of a large bandgap, high electron mobility, and high thermal conductivity, and have currently become the focus of attention in the fields of new energy, power electronic devices, etc. However, due to the problem of gate oxide layer defects in the device structure, the interface state charge trap capturing charges may reduce the carrier density in the device channel and cause Coulomb scattering to the carriers, resulting in a low carrier mobility in the channel, and also restricting the development of SiC devices. Summary of the Invention
[0003] In view of the above problems, the present disclosure provides a P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC for improving hole mobility and a method for manufacturing the same.
[0004] One aspect of the present disclosure provides a P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC, characterized in that the transistor includes: a substrate, the material of the substrate including 4H-SiC; an epitaxial layer formed on the upper surface of the substrate, the material of the epitaxial layer including 3C-SiC; a source electrode and a drain electrode formed on the upper surface of the epitaxial layer; a passivation layer covering the upper surfaces of the source electrode and the drain electrode; a grooved gate, the top of the grooved gate being formed on the upper surface of the passivation layer, the bottom of the grooved gate being formed inside the epitaxial layer, the bottom of the grooved gate being electrically isolated from the epitaxial layer by a gate oxide layer, and the orthographic projection area of the top of the grooved gate on the substrate covering the orthographic projection area of the bottom of the grooved gate on the substrate.
[0005] According to an embodiment of the present disclosure, the groove depth of the grooved gate is between 30 nm and 400 nm.
[0006] According to an embodiment of the present disclosure, the thickness of the epitaxial layer is between 100 nm and 500 nm.
[0007] According to an embodiment of the present disclosure, the thickness of the gate oxide layer is between 20 nm and 100 nm.
[0008] According to an embodiment of the present disclosure, device isolation grooves are provided on both sides of the epitaxial layer, the top of the device isolation grooves being flush with the upper surface of the epitaxial layer, and the bottom of the device isolation grooves being provided inside the substrate.
[0009] According to an embodiment of the present disclosure, the device isolation trench depth from the top to the bottom of the above-mentioned device isolation trench is between 700 nm and 1200 nm.
[0010] Another aspect of the present disclosure also provides a method for manufacturing a P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC, characterized in that the method includes: forming an epitaxial layer on a substrate, the material of the substrate includes 4H-SiC, and the material of the epitaxial layer includes 3C-SiC; forming a source electrode, a drain electrode and a passivation layer on the epitaxial layer, and covering the upper surfaces of the source electrode and the drain electrode with the passivation layer; forming a grooved gate on the passivation layer and the epitaxial layer, the top of the grooved gate is formed on the upper surface of the passivation layer, the bottom of the grooved gate is formed inside the epitaxial layer, the bottom of the grooved gate is electrically isolated from the epitaxial layer by a gate oxide dielectric layer, and the orthographic projection area of the top of the grooved gate on the substrate covers the orthographic projection area of the bottom of the grooved gate on the substrate; etching the passivation layer on the upper surfaces of the source electrode and the drain electrode so that the upper surfaces of the source electrode and the drain electrode are exposed.
[0011] According to an embodiment of the present disclosure, forming the grooved gate on the passivation layer and the epitaxial layer includes: etching from the upper surface of the passivation layer towards the epitaxial layer to obtain a groove, the bottom of the groove is inside the epitaxial layer; forming the gate oxide dielectric layer inside the groove by thermal oxidation; filling the groove formed with the gate oxide dielectric layer with polysilicon to form the grooved gate structure.
[0012] According to an embodiment of the present disclosure, the doping concentration of the above-mentioned epitaxial layer is between 1.0×10 14 cm -3 ~5.0×10 16 cm -3 .
[0013] According to an embodiment of the present disclosure, the horizontal distance between the source electrode and the top of the grooved gate is between 1 μm and 3 μm, and the horizontal distance between the drain electrode and the top of the grooved gate is between 2 μm and 9 μm.
[0014] The P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC provided by the embodiments of the present disclosure uses 4H-SiC as the substrate material and 3C-SiC as the epitaxial layer material. When a heterojunction is formed between 3C-SiC and 4H-SiC, a two-dimensional hole gas with a high concentration can be formed at the 3C-SiC interface. The two-dimensional hole gas serves as a conductive channel, which can improve the hole mobility. Through the grooved gate structure of the device, since the bottom of the grooved gate is formed within the epitaxial layer, the thickness of the part where the gate exists in the epitaxial layer is thinner than that of the part where the gate does not exist. This can improve the accuracy of the gate to control the current while reducing the damage of the process to the device, thereby reducing the surface state charge traps of the device and reducing the trapping of holes by the traps, thus improving the hole mobility. Description of the Drawings
[0015] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above content and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:
[0016] Figure 1 Schematically shows the structural diagram of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC according to the embodiments of the present disclosure;
[0017] Figure 2 Schematically shows the schematic diagram of the transistor with dimensions according to the embodiments of the present disclosure;
[0018] Figure 3 Schematically shows the flowchart of the manufacturing method of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC according to the embodiments of the present disclosure;
[0019] Figures 4A to 4H Shows Figure 3 The cross-sectional view of the device structure formed after some operations in the shown method flow are executed; and
[0020] Figure 5 Schematically shows the transfer characteristic diagram of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC according to the embodiments of the present disclosure. Detailed Embodiments
[0021] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.
[0022] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprising", "including", etc. as used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0023] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.
[0024] In cases where expressions such as "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those of ordinary skill in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).
[0025] Schematic diagrams of various structures according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where certain details are enlarged for the purpose of clear expression, and certain details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary, and may actually deviate due to manufacturing tolerances or technical limitations. Those of ordinary skill in the art can additionally design regions / layers having different shapes, sizes, and relative positions according to actual needs.
[0026] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.
[0027] Existing SiC-based devices are restricted by the problem of gate oxide layer defects in the 4H-SiC structure. Interface state charge traps capture charges, reducing the carrier density in the MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) channel, resulting in a channel mobility that is only 5% of the bulk mobility. The channel mobility of traditional SiC P-MOSFETs is only 3 cm 2 / Vs ~ 7 cm 2 / Vs. In addition, the ionization rate of Al impurities in 4H-SiC at room temperature is relatively low, the ohmic contact resistivity of P-type 4H-SiC is high, and the reliability of P-type MOSFETs is poor. Therefore, it is difficult to fabricate high-performance P-channel MOSFET devices, which also becomes an important factor restricting the development of SiC devices.
[0028] In addition to the above-mentioned gate oxide layer, the device process can also cause low mobility of the device. For example, in the above device, in order to improve the control accuracy of the gate over the current, the thickness of the epitaxial layer is generally thinned. Because the thinner the epitaxial layer, the stronger the influence of the gate electric field on the channel, and the stronger the control ability of the gate over the current. However, the process of etching and thinning the epitaxial layer may cause etching damage to the device, which in turn leads to interface state traps in the device and reduces the hole mobility.
[0029] In view of this, based on the fact that SiC material is a typical crystal polymorphic material, there are differences in the stacking order of Si-C bilayers between different crystal forms, resulting in significant differences in physical and chemical properties between crystal forms. SiC crystal form materials can include 3C-SiC with a zinc blende structure, and 4H-SiC and 6H-SiC with a wurtzite structure. The wurtzite structure has a spontaneous polarization effect. When a heterojunction is formed between 3C-SiC and the Si face of 4H-SiC, under the action of the spontaneous polarization effect and the quantum well barrier formed by the heterostructure, a high-concentration two-dimensional hole gas (2DHG) can be formed at the 3C-SiC interface. A heterojunction field-effect transistor using the two-dimensional hole gas as a conductive channel can realize a P-channel SiC device with high electron mobility, providing a new technical route for SiC materials in the fields of integrated circuits, power electronic devices, etc.
[0030] Based on this, the embodiments of the present disclosure provide a P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC and a preparation method thereof, which are used to improve the hole mobility. The P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC in this embodiment can be as Figure 1 shown.
[0031] Figure 1 Schematically shows the structural diagram of a P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC according to an embodiment of the present disclosure.
[0032] As Figure 1As shown, the transistor may include: a substrate 101, the material of the substrate 101 including 4H-SiC; an epitaxial layer 102 formed on the upper surface of the substrate 101, the material of the epitaxial layer 102 including 3C-SiC; a source electrode 103 and a drain electrode 104 formed on the upper surface of the epitaxial layer 102; a passivation layer 105 covering the upper surfaces of the source electrode 103 and the drain electrode 104; a recessed gate 106, the top of the recessed gate 106 being formed on the upper surface of the passivation layer 105, the bottom of the recessed gate 106 being formed inside the epitaxial layer 102, the bottom of the recessed gate being electrically isolated from the epitaxial layer by a gate oxide dielectric layer 107, and the orthographic projection area of the top of the recessed gate 106 on the substrate 101 covering the orthographic projection area of the bottom of the recessed gate 106 on the substrate 101.
[0033] Optionally, device isolation grooves 108 may be provided on both sides of the epitaxial layer 102, which can be used for electrical isolation, parasitic capacitance isolation, thermal isolation, etc. between different devices, prevent mutual interference between devices, effectively isolate devices, reduce defects, and improve hole mobility.
[0034] Optionally, the material of the passivation layer may be selected as silicon dioxide (SiO2). SiO2 is relatively stable and has high interface quality. Using SiO2 as the passivation layer can reduce the interface state density, reduce carrier recombination, improve hole mobility, and improve transistor performance.
[0035] Optionally, the recessed gate 106 is formed by etching the 3C-SiC epitaxial layer and the 3C-SiC oxidation process. The orthographic projection area of the top of the recessed gate 106 on the substrate 101 covers the orthographic projection area of the bottom of the recessed gate 106 on the substrate 101. The size of the top of the recessed gate in the horizontal direction is larger than the size of the bottom in the horizontal direction. The structure with a wider top can make the electric field more evenly distributed in the channel, improve the gate's control ability over the channel current, and improve device performance. Moreover, the structure with a wider top is easier to perform photolithography and etching during the manufacturing process, can avoid damage to the device caused by the process, reduce interface state traps, and improve hole mobility.
[0036] The P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC provided by the embodiments of the present disclosure selects 4H-SiC as the substrate material and 3C-SiC as the epitaxial layer material. When 3C-SiC and 4H-SiC form a heterojunction, a high-concentration two-dimensional hole gas can be formed at the 3C-SiC interface. The two-dimensional hole gas serves as a conductive channel, which can improve the hole mobility. Through the grooved gate structure of the device, since the bottom of the grooved gate is formed in the epitaxial layer, the thickness of the part of the gate existing in the epitaxial layer is thinner than that of the part without the gate, so that the whole epitaxial layer does not need to be thinned. Thus, while improving the accuracy of the gate control current, the damage to the device caused by the etching and thinning process can be reduced, and further the surface state charge traps of the device can be reduced, and the trapping of holes by the traps can be reduced, thereby improving the hole mobility.
[0037] Figure 2 Schematically shows a schematic diagram of a transistor with dimensions according to an embodiment of the present disclosure.
[0038] As Figure 2 shown, the thickness D1 of the epitaxial layer 102 can be adjusted between 100 nm and 500 nm. The groove depth D2 of the grooved gate 106 can be adjusted between 30 nm and 400 nm.
[0039] Optionally, an overly deep groove may lead to uneven electric field distribution, weakening the control of the gate over the channel current. At the same time, an overly deep groove may also increase the burden of the etching process, which is not conducive to obtaining a device with few interface traps and is not conducive to the improvement of the hole rate; an overly shallow groove may prevent the gate electric field from effectively penetrating the entire channel, also weakening the gate control ability. Based on this, when the thickness of the epitaxial layer in the embodiments of the present disclosure is between 100 nm and 500 nm, the depth of the groove is preferably between 30 nm and 400 nm. The depth of the groove can also be adaptively adjusted according to the actual thickness of the epitaxial layer.
[0040] Continuing to refer to Figure 2 , the thickness D3 of the gate oxide dielectric layer can be between 20 nm and 100 nm, and can be specifically adjusted adaptively according to actual needs. An overly thick gate oxide layer may result in a large on-resistance, affecting the on-current of the device; an overly thin gate oxide layer may result in insufficient gate control ability, thus also affecting the on-current of the device and reducing the performance of the device. The thickness of the gate oxide dielectric layer can be adjusted within the above range.
[0041] Optionally, continuing to refer to Figure 2, device isolation grooves 108 may be provided on both sides of the epitaxial layer 102. The top of the device isolation groove 108 is flush with the upper surface of the epitaxial layer 102, and the bottom of the device isolation groove 108 is provided inside the substrate 101. The device isolation groove depth D4 from the top of the device isolation groove 108 to the bottom of the device isolation groove 108 can be adjusted between 700 nm and 1200 nm.
[0042] Figure 3 FIG. schematically shows a flowchart of a method for manufacturing a P-channel heterojunction field effect transistor with a recessed gate structure 3C / 4H-SiC according to an embodiment of the present disclosure.
[0043] As Figure 3 shown, the manufacturing method of this embodiment may include operation S310 to operation S340.
[0044] In operation S310, an epitaxial layer is formed on a substrate. The material of the substrate includes 4H-SiC, and the material of the epitaxial layer includes 3C-SiC.
[0045] In operation S320, a source electrode, a drain electrode, and a passivation layer are formed on the epitaxial layer, and the upper surfaces of the source electrode and the drain electrode are covered by the passivation layer.
[0046] In operation S330, a recessed gate is formed on the passivation layer and the epitaxial layer. The top of the recessed gate is formed on the upper surface of the passivation layer, and the bottom of the recessed gate is formed inside the epitaxial layer. The bottom of the recessed gate is electrically isolated from the epitaxial layer by a gate oxide dielectric layer. The positive projection area of the top of the recessed gate on the substrate covers the positive projection area of the bottom of the recessed gate on the substrate.
[0047] In operation S340, the passivation layer on the upper surfaces of the source electrode and the drain electrode is etched so that the upper surfaces of the source electrode and the drain electrode are exposed.
[0048] Figures 4A to 4H shows Figure 3 a cross-sectional view of a device structure formed after some operations in the method flow shown are performed.
[0049] As Figure 4A shown, an epitaxial layer 102 of 3C-SiC with a thickness of 100 nm to 500 nm is epitaxially grown on a substrate 101 of Si-face 4H-SiC. For example, an epitaxial layer of 3C-SiC with a thickness of 200 nm is epitaxially grown on Si-face 4H-SiC.
[0050] In some embodiments, the doping concentration of the epitaxial layer may be between 1.0×10 14 cm -3 ~5.0×10 16 cm -3 , and can be specifically adjusted adaptively according to actual needs.
[0051] As Figure 4B shown, SiO2 with a thickness of 500 nm is deposited on the epitaxial layer 102 of 3C-SiC, and a device isolation groove 108 with a depth of 700 nm to 1200 nm is etched. For example, a layer of SiO2 with a thickness of 500 nm is deposited on the 3C-SiC epitaxial layer and a device isolation groove with a depth of 800 nm is etched.
[0052] As Figure 4C shown, source metal connection holes and drain metal connection holes are etched on the device surface shown in Figure 4B . Metal is deposited in the source metal connection holes and drain metal connection holes to form ohmic contacts, obtaining a source 103 and a drain 104.
[0053] As Figure 4D shown, SiO2 is deposited on the device surface shown in Figure 4C to passivate the metal of the source 103 and the metal of the drain 104, forming a passivation layer 105.
[0054] As Figure 4E , Figure 4F and Figure 4G shown, a recessed gate 106 is formed on the passivation layer 105 and the epitaxial layer 102. In one example, this process may include the following process: etching from the upper surface of the passivation layer 105 towards the epitaxial layer 102 to obtain a recess, the bottom of the recess being inside the epitaxial layer 102; forming a gate oxide dielectric layer inside the recess by thermal oxidation; filling the recess formed with the gate oxide dielectric layer with polysilicon to form a recessed gate 106 structure.
[0055] In one embodiment, a recess with a depth of 30 nm to 400 nm in the 3C-SiC epitaxial layer can be formed by dry etching on the passivation layer 105 of SiO2 and the epitaxial layer 102 of 3C-SiC. For example, a recess with a depth of 100 nm is formed by etching on the SiO2 passivation layer and the 3C-SiC epitaxial layer, as Figure 4E shown. A device gate oxide dielectric is formed by thermal oxidation inside the recess, as Figure 4F shown, and the material of the gate oxide dielectric can be the same as the material of the passivation layer. A recessed gate 106 structure is formed by depositing polysilicon inside the recess formed with the gate oxide layer, as Figure 4G shown.
[0056] In some embodiments, the horizontal spacing D5 between the source 10 and the top of the grooved gate 106 may be between 1 μm and 3 μm, and the horizontal spacing D6 between the drain 104 and the top of the grooved gate 106 may be between 2 μm and 9 μm, and can be adaptively adjusted according to actual needs. If the horizontal spacing between the source and the drain and the top of the grooved gate is too large or too small, it may affect the on-current of the device, thereby reducing the performance of the device. Therefore, the spacing can be set within the above range.
[0057] As Figure 4H shown, the passivation layers on the upper surfaces of the source 103 and the drain 104 as Figure 4G shown are etched so that the upper surfaces of the source 103 and the drain 104 are exposed.
[0058] Figure 5 Schematically shows the transfer characteristic diagram of a P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC according to an embodiment of the present disclosure.
[0059] The embodiments of the present disclosure use simulation and theoretical formulas to Figure 1 simulate the transfer characteristic curves of the structure of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC as Figure 5 shown at different mobilities, and the simulation results can be as
[0060] In Figure 5 , the abscissa is the gate voltage and the ordinate is the drain current. The thickness of the 3C-SiC epitaxial layer of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC in this embodiment is 100 nm, the gate length is 1 μm, and the gate-source spacing is 3 μm. The 6 curves in the figure are the transfer curves of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC when the simulated hole mobility varies from 1 cm 2 / Vs to 30 cm 2 / Vs. The mobility of the two-dimensional hole gas formed by the heterojunction is higher and can reach more than 20 cm 2 / Vs, and is much larger than the hole mobility (3 cm 2 / Vs to 5 cm 2 / Vs) in the traditional SiC P-MOSFET structure. Based on this, the channel current density of the P-channel heterojunction field-effect transistor with a grooved gate structure of 3C / 4H-SiC in the embodiments of the present application is higher, and can play a greater role in fields such as integrated circuits and power electronic devices.
[0061] The groove-gate structure 3C / 4H-SiC P-channel heterojunction field-effect transistor structure and manufacturing method proposed in the embodiments of the present invention have the following beneficial effects: a high-mobility two-dimensional hole gas conductive channel structure is formed through the heterostructure, and it can be compatible with the processes of traditional SiC MOSFET devices without involving additional process operations, enabling the realization of high-mobility P-channel SiC devices and improving the on-current of the devices.
[0062] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
[0063] The embodiments of the present disclosure have been described above. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.
Claims
1. A P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC, characterized in that, The transistor includes: a substrate, the material of the substrate including 4H-SiC; an epitaxial layer formed on the upper surface of the substrate, the material of the epitaxial layer including 3C-SiC; a source and a drain formed on the upper surface of the epitaxial layer; a passivation layer covering the upper surfaces of the source and the drain; a trench gate, the top of the trench gate being formed on the upper surface of the passivation layer, the bottom of the trench gate being formed inside the epitaxial layer, the bottom of the trench gate being electrically isolated from the epitaxial layer by a gate oxide dielectric layer, and the projection area of the top of the trench gate on the substrate covering the projection area of the bottom of the trench gate on the substrate.
2. The transistor according to claim 1, characterized in that, The trench depth of the trench gate is between 30 nm and 400 nm.
3. The transistor according to claim 1, wherein The thickness of the epitaxial layer is between 100 nm and 500 nm.
4. The transistor according to claim 1, wherein The thickness of the gate oxide dielectric layer is between 20 nm and 100 nm.
5. The transistor according to claim 1, wherein Device isolation trenches are provided on both sides of the epitaxial layer, the top of the device isolation trenches being flush with the upper surface of the epitaxial layer, and the bottom of the device isolation trenches being provided inside the substrate.
6. The transistor according to claim 5, characterized in that, The device isolation trench depth from the top to the bottom of the device isolation trench is between 700 nm and 1200 nm.
7. A preparation method of a P-channel heterojunction field effect transistor with a grooved gate structure of 3C / 4H-SiC, characterized in that The method includes: forming an epitaxial layer on a substrate, the material of the substrate including 4H-SiC, and the material of the epitaxial layer including 3C-SiC; forming a source, a drain and a passivation layer on the epitaxial layer, and using the passivation layer to cover the upper surfaces of the source and the drain; forming a trench gate on the passivation layer and the epitaxial layer, the top of the trench gate being formed on the upper surface of the passivation layer, the bottom of the trench gate being formed inside the epitaxial layer, the bottom of the trench gate being electrically isolated from the epitaxial layer by a gate oxide dielectric layer, and the projection area of the top of the trench gate on the substrate covering the projection area of the bottom of the trench gate on the substrate; etching the passivation layer on the upper surfaces of the source and the drain to expose the upper surfaces of the source and the drain.
8. The method according to claim 7, characterized in that The forming the trench gate on the passivation layer and the epitaxial layer includes: etching from the upper surface of the passivation layer towards the epitaxial layer to obtain a trench, the bottom of the trench being inside the epitaxial layer; forming the gate oxide dielectric layer inside the trench by thermal oxidation; filling polysilicon into the trench formed with the gate oxide dielectric layer to form the trench gate structure.
9. The method according to claim 7, characterized in that, The doping concentration of the epitaxial layer is between 1.0×10 14 cm -3 ~5.0×10 16 cm -3 .
10. The method according to claim 7, characterized in that, The horizontal distance between the source and the top of the trench gate is between 1 μm and 3 μm, and the horizontal distance between the drain and the top of the trench gate is between 2 μm and 9 μm.