Hole filling method of copper interconnection semiconductor cooler

Abstract

The invention relates to the technical field of semiconductor copper interconnection, in particular to a hole filling method of a copper interconnection semiconductor cooler, which comprises the following steps of: performing multi-stage chemical cleaning treatment on a semiconductor substrate after laser drilling, removing dirt on the surface of the substrate, coarsening the surface of the substrate to increase binding force and removing residual slag at a hole after drilling; the influence on seed layer sputtering in subsequent holes caused by slag accumulation at the hole opening is avoided; and meanwhile, three-step electroplating of the initial copper layer, through hole filling and orifice and surface leveling are adopted, so that cavity-free hole filling and surface nanoscale leveling are realized, and the final product yield is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor copper interconnection technology, and specifically relates to a method for filling holes in a copper-interconnected semiconductor cooler. Background Art

[0002] To achieve AI communication transmission, it is necessary to greatly improve the transmission rate of optical communication modules, which can reach over 800G or even 1.6T. Therefore, there are higher requirements for the heat dissipation of communication modules. Existing communication modules often use TEC (thermoelectric cooler) to achieve heat dissipation of communication modules. A thermoelectric cooler is an electronic device that uses the Peltier effect of semiconductor materials to achieve refrigeration.

[0003] Application No. 202410962055.4 electroplates and fills holes with copper from the original connection electrode of the thermoelectric cooler, so that the original connection electrode is connected to the lower surface of the lower substrate of the thermoelectric cooler to form an electrode contact. In this way, the thermoelectric cooler can be directly connected to the upper end of the power supply electrode of the high-speed optical communication module circuit board through copper interconnection without using any additional gold wires. The above method can avoid line loss caused by gold wire jumpers through copper interconnection and effectively increase the effective heat dissipation area of the thermoelectric cooler.

[0004] However, in actual preparation, copper interconnection hole filling technology is prone to generating bubbles and holes, resulting in relatively large on-resistance on both the front and back sides of the thermoelectric cooler during use, thus affecting the product yield and the refrigeration efficiency of the thermoelectric cooler.

[0005] In view of this, a method for filling holes in a copper-interconnected semiconductor cooler is proposed. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for filling holes in a copper-interconnected semiconductor cooler. By performing multi-stage chemical cleaning treatment on the semiconductor substrate after laser drilling, the dirt on the substrate surface is removed, the substrate surface is roughened to increase the bonding force, and the slag remaining at the hole opening after drilling is removed, avoiding the accumulation of slag at the hole opening and affecting the subsequent sputtering of the seed layer inside the hole. At the same time, a three-stage stepped electroplating initial copper layer, via filling, and planarization of the hole opening and surface are adopted to achieve void-free hole filling and nanoscale surface flatness, solving the problems existing in the prior art.

[0007] To solve the above technical problems, the present invention adopts the following solutions: A method for filling holes in a copper-interconnected semiconductor cooler, which sequentially performs the following steps: S1, after laser drilling the semiconductor substrate to form through holes, perform multi-stage chemical cleaning treatment to remove the slag at the through hole openings and roughen the surface of the semiconductor substrate; S2. Deposit a titanium seed layer and a copper seed layer in sequence on the surface and within the through-holes of the semiconductor substrate by magnetron sputtering as the conductive seed layer; S3. Fabricate the circuit pattern using a dry film combined with a laser direct imaging technique; S4. Perform pre-treatment for electroplating on the semiconductor substrate to remove surface impurities; S5. Use three-stage step electroplating to sequentially form an initial copper layer within the through-holes, through-hole filling, and planarization of the hole mouth and the surface; S6. Remove the dry film and etch the seed layer to complete the circuit patterning; then perform electroless nickel palladium gold treatment on the surface of the semiconductor substrate.

[0008] Furthermore, the multi-stage chemical cleaning treatment in step S1 is as follows: Organic cleaning: Acetone ultrasonic cleaning at 55°C for 10 minutes, isopropanol immersion at room temperature for 5 minutes, and primary rinsing with deionized water; Alkaline cleaning: In a mixed solution of potassium permanganate and sodium hydroxide, clean at 75°C for 5 to 10 minutes, and perform secondary rinsing with deionized water; Acid cleaning: In a mixed solution of sulfuric acid and hydrogen peroxide, clean for 5 to 10 minutes; Hot water washing at 80 - 90°C; Tertiary rinsing with deionized water.

[0009] Furthermore, the mass concentrations of both potassium permanganate and sodium hydroxide are 3% - 5%; the volume ratio of sulfuric acid to hydrogen peroxide is 3:1.

[0010] Furthermore, in step S2, during the sputtering process, the vacuum degree is 1×10 -3 Pa to 9×10 -3 Pa, the chamber temperature is 150°C - 250°C, and a bias voltage of 100V - 300V is applied during the sputtering process.

[0011] Furthermore, the thickness of the titanium seed layer is 0.1μm - 0.3μm, and the thickness of the copper seed layer is 1μm - 3μm.

[0012] Furthermore, the three-stage step electroplating is in sequence: direct current pre-plating, pulse electroplating, and direct current final plating.

[0013] Furthermore, during direct current pre-plating, the current density is 0.5 ASD, and the electroplating time is 15 minutes; The electroplating solution is: copper sulfate 60 g / L - 90 g / L; sulfuric acid 180 g / L - 220 g / L; chloride ion 40 mg / L - 60 mg / L; brightening agent 10 ml / L - 15 ml / L; wetting agent 1 ml / L - 5 ml / L.

[0014] Further, during pulse electroplating, the forward current density is 0.5 ASD to 0.7 ASD, the time is 27 ms to 36 ms, the reverse current density is 1.25 ASD to 1.75 ASD, the time is 3 ms to 4 ms, and the total pulse electroplating time is 300 min; The electroplating solution is: copper sulfate 210 g / L to 260 g / L; sulfuric acid 40 g / L to 60 g / L; chloride ions 40 mg / L to 60 mg / L; brightener 1 ml / L to 5 ml / L; wetting agent 5 ml / L to 15 ml / L; leveling agent 2 ml / L to 10 ml / L.

[0015] Further, during DC final plating, the current density is 0.7 ASD and the electroplating time is 60 min; The electroplating solution is: copper sulfate 60 g / L to 90 g / L; sulfuric acid 180 g / L to 220 g / L; chloride ions 40 mg / L to 60 mg / L; brightener 10 ml / L to 15 ml / L; wetting agent 1 ml / L to 5 ml / L.

[0016] Further, the nickel layer thickness is 2.5 μm to 7.5 μm, the palladium layer thickness is > 0.1 μm, and the gold layer thickness is > 0.2 μm.

[0017] The beneficial effects of the present invention are as follows: on the one hand, by adopting multi-stage chemical cleaning treatment after laser drilling of the substrate, successively performing organic cleaning, alkali cleaning, acid cleaning, hot water washing and three rinses with deionized water, the organic matter-oxide-ion pollution is removed step by step to avoid cross-contamination; the combination of alkali cleaning to roughen the surface and acid cleaning to activate the surface improves the adhesion of the subsequent seed layer.

[0018] On the other hand, three-stage stepped electroplating is adopted to successively form an initial copper layer in the through hole, through hole filling, and planarization of the hole mouth and surface. By optimizing the current mode in stages, DC → pulse → DC, and dynamically adjusting the electroplating solution composition, pre-plating with high acid / pulse with high copper / final plating with high brightener, void-free hole filling and nano-level surface planarity are achieved, improving the yield and qualification rate of the final product. Description of the Drawings

[0019] Figure 1 It is a photographed picture after slicing the product prepared in the example; Figure 2 It is the X-RAY scanning result after slicing the product prepared in the example; Figure 3 It is a photographed picture after slicing the product prepared in the comparative example; Figure 4 It is the X-RAY scanning result after slicing the product prepared in the comparative example. Detailed Embodiments

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0021] Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present invention.

[0022] In addition, for the sake of clarity and conciseness, descriptions of well-known structures, functions, and configurations may be omitted. Those of ordinary skill in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0023] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be regarded as part of the authorization specification.

[0024] In all the examples shown and discussed here, any specific value should be construed as merely exemplary, and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0025] Embodiment A method for filling holes in a copper-interconnected semiconductor refrigerator, which sequentially performs the following steps: S1, after laser drilling through holes in the semiconductor substrate, multi-stage chemical cleaning treatment is performed to remove the slag at the hole orifice of the through holes and roughen the surface of the semiconductor substrate.

[0026] Among them, the multi-stage chemical cleaning treatment includes: Organic cleaning: Acetone ultrasonic cleaning at 55°C for 10 min, isopropanol immersion at room temperature for 5 min, and one-time rinsing with deionized water; Alkaline cleaning: In a mixed solution of potassium permanganate and sodium hydroxide, the mass concentrations of the two are 3% - 5% respectively, cleaning at 75°C for 5 - 10 min, and two-time rinsing with deionized water; Acid cleaning: In a mixed solution of sulfuric acid and hydrogen peroxide, the volume ratio of the two is 3:1, cleaning for 5 - 10 min; Hot water washing at 80 - 90°C; Three-time rinsing with deionized water.

[0027] Through multi-stage chemical cleaning treatment, 1) Organic cleaning removes contaminants such as grease, fingerprints, and dust remaining on the surface of the semiconductor substrate. At the same time, acetone and isopropyl alcohol, as polar-nonpolar mixed solvents, can dissolve a variety of organic substances, avoiding interference in subsequent chemical reactions; Acetone ultrasonic treatment at 55°C increases the solvent activity to strip stubborn contaminants; Isopropyl alcohol immersion replaces the residual acetone and further dissolves hydrophilic organic substances, while reducing the toxic residue of acetone; 2) Alkaline cleaning involves the reaction of potassium permanganate in a strong alkaline medium to oxidize and decompose the metal oxide slag generated by laser drilling; At the same time, sodium hydroxide corrodes the substrate surface to form a micron-scale rough structure, enhancing the adhesion of the subsequent seed layer; 3) Acid cleaning mainly neutralizes the sodium hydroxide in the previous step to prevent the residual alkali solution from corroding the metal layer in the subsequent process; Hydrogen peroxide is used for reductive cleaning to reduce the metal oxides not removed by alkaline cleaning and dissolve trace organic residues, removing surface micro-contaminants; 4) High-temperature hot water washing removes chemical residues, and at the same time reduces the internal stress of the substrate through temperature changes, avoiding the warping risk during subsequent sputtering or electroplating; 5) Three rinses with deionized water thoroughly clean the substrate, and the low conductivity of deionized water reduces electrostatic adsorption, ensuring that the substrate surface is in a highly active state, which is beneficial to the sputtering deposition of the subsequent seed layer.

[0028] Through multi-stage chemical cleaning treatment, organic-oxide-ion contamination is removed step by step to avoid cross-contamination; The combination of surface roughening by alkaline cleaning and surface activation by acid cleaning enhances the adhesion of the subsequent seed layer.

[0029] S2, Conductive seed layers of titanium seed layer and copper seed layer are sequentially deposited on the surface and through holes of the semiconductor substrate by magnetron sputtering. The thickness of the titanium seed layer is 0.1μm - 0.3μm, and the thickness of the copper seed layer is 1μm - 3μm; The vacuum degree during sputtering is 1×10 -3 Pa - 9×10 -3 Pa, the chamber temperature is 150°C - 250°C, and a bias voltage of 100V - 300V is applied during sputtering. During sputtering, the titanium seed layer and copper seed layer are sputtered first, and a bias voltage of 100V - 300V is applied to sputter a relatively thick titanium-copper seed layer in the holes as much as possible to improve the mechanical strength of the seed layer.

[0030] S3, The circuit pattern is fabricated using a dry film combined with a laser direct imaging technique; Improve the circuit accuracy and consistency, and make the dry film combine tightly with the titanium seed layer and copper seed layer.

[0031] S4. Pretreat the semiconductor substrate before electroplating to remove surface impurities, mainly including degreasing and micro-etching. For degreasing, it is treated with a mixed solution composed of dilute sulfuric acid with a concentration of 60 ml / L - 90 ml / L and a surfactant with a concentration of 10 ml / L - 50 ml / L for 30 s - 60 s to remove organic pollutants and activate the surface; the surfactant peels off organic pollutants such as grease, fingerprints, and dust on the copper surface through emulsification and dispersion; the dilute sulfuric acid provides an acidic environment, dissolves some metal oxides such as copper oxide, and at the same time enhances the decontamination efficiency of the surfactant and improves the wettability of the subsequent electroplating solution. For micro-etching, it is treated with a mixed solution composed of dilute sulfuric acid with a concentration of 60 ml / L - 100 ml / L and sodium persulfate with a concentration of 50 g / L - 100 g / L for 10 s - 30 s to micro-roughen the surface microscopically and thoroughly clean the residues, ensuring that the subsequent electroplating solution directly contacts the pure copper surface and improving the adhesion to the electroplating layer.

[0032] S5. Use three-stage step electroplating to sequentially form an initial copper layer in the through-hole, through-hole filling, and planarization of the hole opening and surface, including the following: During DC pre-plating, the current density is 0.5 ASD and the electroplating time is 15 min; The electroplating solution is: copper sulfate 60 g / L - 90 g / L; sulfuric acid 180 g / L - 220 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 10 ml / L - 15 ml / L; wetting agent 1 ml / L - 5 ml / L.

[0033] During pulse electroplating, the forward current density is 0.5 ASD - 0.7 ASD, the time is 27 ms - 36 ms, the reverse current density is 1.25 ASD - 1.75 ASD, the time is 3 ms - 4 ms, and the total pulse electroplating time is 300 min; The electroplating solution is: copper sulfate 210 g / L - 260 g / L; sulfuric acid 40 g / L - 60 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 1 ml / L - 5 ml / L; wetting agent 5 ml / L - 15 ml / L; leveling agent 2 ml / L - 10 ml / L.

[0034] During DC final plating, the current density is 0.7 ASD and the electroplating time is 60 min; The electroplating solution is: copper sulfate 60 g / L - 90 g / L; sulfuric acid 180 g / L - 220 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 10 ml / L - 15 ml / L; wetting agent 1 ml / L - 5 ml / L.

[0035] Here, the initial copper layer is formed by DC pre - plating. A low current density is used to avoid excessive deposition at the hole openings, preferentially forming a thin and continuous copper layer inside the holes, reducing the resistance inside the holes. A high - concentration sulfuric acid inhibits dendritic growth, ensuring that the initial layer is dense and defect - free. At the same time, pulse electroplating is used for filling through - holes. The forward pulse uses a high current density (0.5 ASD - 0.7 ASD) to accelerate deposition at the bottom of the holes. The reverse pulse uses a short - time high reverse current (1.25 ASD - 1.75 ASD) to dissolve the overly thick copper layer at the hole openings. The leveling agent adsorbs on the protruding areas, inhibiting local deposition and achieving bottom - up filling. The leveling agent is prior art and will not be listed one by one here. DC final plating is used for planarization, increasing the current density, preferentially depositing in the concave areas (hole openings) to compensate for the minor depressions after pulse hole filling. And the brightener, through surface - active action, obtains a mirror - level flatness.

[0036] Three - stage stepped electroplating optimizes the current mode (DC → pulse → DC) in stages and dynamically adjusts the electroplating solution composition (pre - plating high - acid / pulse high - copper / final - plating high - brightener) to achieve void - free hole filling and nanoscale surface flatness.

[0037] S6. Remove the dry film and etch the seed layer to complete the circuit patterning; then perform electroless nickel - palladium - gold plating on the surface of the semiconductor substrate.

[0038] When removing the dry film, use a sodium hydroxide solution with a concentration of 3% - 5% and perform ultrasonic cleaning at 40°C - 60°C to thoroughly remove the dry - film resist, exposing the underlying seed layers not protected by electroplated copper, such as titanium seed layers and copper seed layers; thus avoiding dry - film residues interfering with subsequent etching, resulting in burrs or short - circuits at the circuit edges.

[0039] When etching the copper seed layer, use a mixture of 50 ml / L - 100 ml / L hydrogen peroxide and 300 ml / L - 500 ml / L copper etchant to selectively etch the exposed copper seed layer, only retaining the areas covered by electroplated copper and avoiding mis - etching the titanium seed layer.

[0040] When etching the titanium seed layer, use a mixture of titanium etchant and hydrogen peroxide with a volume ratio of 1.3:1 to remove the exposed titanium seed layer, complete the circuit patterning, and only retain the electroplated copper and the underlying titanium layer.

[0041] Among them, for the electroless plating layer, the nickel layer thickness is 2.5 μm - 7.5 μm, the palladium layer thickness is > 0.1 μm, and the gold layer thickness is > 0.2 μm; the nickel layer can effectively block the diffusion of copper atoms to the surface, prevent copper oxidation or reaction with solder to form brittle intermetallic compounds; it has high hardness, provides mechanical support, provides a flat substrate for the subsequent palladium / gold layer, and reduces surface roughness. The palladium layer is dense and chemically inert, preventing the oxidation of the nickel layer during storage or soldering and improving the adhesion of the gold layer. The gold layer has stable chemical properties, does not oxidize in air, protects the palladium layer, and improves long - term reliability.

[0042] The results of slicing microscopy and X-RAY scanning of the product obtained by the via filling method of this application are as Figure 1 and Figure 2 shown.

[0043] Comparative example The via filling method of this comparative example is basically the same as that of the example, except that the process parameters of pulse electroplating are different. Specifically: the forward current density is 0.8 ASD - 1.0 ASD, the time is 37 ms - 45 ms, the reverse current density is 2.0 ASD - 2.5 ASD, the time is 4.2 ms - 5 ms. The results of slicing microscopy and X-RAY scanning of the product after final via filling are as Figure 3 and Figure 4 shown.

[0044] According to Figures 1 to 4 it can be known that in the via filling method of this example, for the copper interconnect semiconductor cooler product with a substrate thickness of 0.5 mm, a via diameter of 70 μm, and a via diameter ratio of 7:1, the sliced view shows that the via is completely filled with a copper plating layer after completion. The X-RAY scanning result shows that the copper filling in the via is 100% completed without defects such as bubbles and holes. However, in the comparative example, the sliced photo of the product shows obvious cracks at the via opening, and the X-RAY scanning result shows defects such as bubbles and holes in the copper in the via, as shown in the circled areas in Figure 3 and Figure 4 .

[0045] The above is only a preferred embodiment of the present invention, and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content without departing from the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for filling holes in a copper-interconnected semiconductor refrigerator, characterized in that, The following steps are carried out successively: S1. After laser drilling through holes in the semiconductor substrate, a multi-stage chemical cleaning treatment is carried out to remove the slag at the hole openings of the through holes and roughen the surface of the semiconductor substrate. S2. A titanium seed layer and a copper seed layer are successively deposited on the surface of the semiconductor substrate and inside the through holes by magnetron sputtering as a conductive seed layer. S3. A circuit pattern is made by using a dry film combined with a laser direct imaging technique. S4. The semiconductor substrate is pretreated before electroplating to remove surface impurities. S5. A three-stage stepped electroplating is used to successively form an initial copper layer inside the through holes, fill the through holes, and planarize the hole openings and the surface. S6. The dry film is removed and the seed layer is etched to complete the circuit patterning; then the semiconductor substrate surface is subjected to electroless nickel-palladium-gold plating treatment.

2. The method for filling holes of a copper interconnect semiconductor refrigerator according to claim 1, wherein The multi-stage chemical cleaning treatment in step S1 is as follows: Organic cleaning: Acetone ultrasonic cleaning at 55°C for 10 min, isopropyl alcohol immersion at room temperature for 5 min, and primary rinsing with deionized water. Alkali cleaning: Cleaning in a mixed solution of potassium permanganate and sodium hydroxide at 75°C for 5 min to 10 min, and secondary rinsing with deionized water. Acid cleaning: Cleaning in a mixed solution of sulfuric acid and hydrogen peroxide for 5 min to 10 min. Hot water washing at 80 - 90°C. Tertiary rinsing with deionized water.

3. The method for filling holes in a copper-interconnected semiconductor refrigerator according to claim 2, characterized in that, The mass concentrations of the potassium permanganate and sodium hydroxide are both 3% - 5%; the volume ratio of sulfuric acid to hydrogen peroxide is 3:

1.

4. The via filling method of a copper interconnect semiconductor refrigerator according to claim 2, characterized in that In step S2, the vacuum degree during the sputtering process is 1×10 -3 Pa to 9×10 -3 Pa, the chamber temperature is 150°C to 250°C, and a bias voltage of 100V to 300V is applied during the sputtering process.

5. The method for filling holes of a copper-interconnected semiconductor refrigerator according to claim 2, characterized in that The thickness of the titanium seed layer is 0.1 μm - 0.3 μm, and the thickness of the copper seed layer is 1 μm - 3 μm.

6. The method for filling holes of a copper-interconnected semiconductor refrigerator according to claim 2, characterized in that The three-stage stepped electroplating is successively: direct current pre-plating, pulse electroplating, and direct current final plating.

7. A method for filling holes in a copper-interconnected semiconductor refrigerator according to claim 6, characterized in that, During direct current pre-plating, the current density is 0.5 ASD and the electroplating time is 15 min. The electroplating solution is: copper sulfate 60 g / L - 90 g / L; sulfuric acid 180 g / L - 220 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 10 ml / L - 15 ml / L; wetting agent 1 ml / L - 5 ml / L.

8. The via filling method of a copper interconnect semiconductor refrigerator according to claim 6, characterized in that, During pulse electroplating, the forward current density is 0.5 ASD - 0.7 ASD, the time is 27 ms - 36 ms, the reverse current density is 1.25 ASD - 1.75 ASD, the time is 3 ms - 4 ms, and the total pulse electroplating time is 300 min. The electroplating solution is: copper sulfate 210 g / L - 260 g / L; sulfuric acid 40 g / L - 60 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 1 ml / L - 5 ml / L; wetting agent 5 ml / L - 15 ml / L; leveling agent 2 ml / L - 10 ml / L.

9. A method for filling holes in a copper-interconnected semiconductor refrigerator according to claim 6, characterized in that, During direct current final plating, the current density is 0.7 ASD and the electroplating time is 60 min. The electroplating solution is: copper sulfate 60 g / L - 90 g / L; sulfuric acid 180 g / L - 220 g / L; chloride ion 40 mg / L - 60 mg / L; brightener 10 ml / L - 15 ml / L; wetting agent 1 ml / L - 5 ml / L.

10. The method for filling holes of a copper-interconnected semiconductor refrigerator according to claim 6, wherein The thickness of the nickel layer is 2.5 μm - 7.5 μm, the thickness of the palladium layer is > 0.1 μm, and the thickness of the gold layer is > 0.2 μm.

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