True random number generator circuit based on 1T1R and random number generation method thereof

Abstract

The invention discloses a true random number generator circuit based on 1T1R and a random number generation method thereof, belongs to the field of information security, and aims to solve the problem that in most true random number generator circuit designs based on volatile memristors, peripheral circuits generally comprise logic gates, triggers and clock signal generators, so that the reliability of the true random number generator circuit is greatly improved. The circuit comprises a memristor, a transistor and a T flip-flop, and the memristor, the transistor and the T flip-flop are connected with the memristor and the T flip-flop respectively. One end of the memristor is connected with an input voltage # imgabs0 #, and the other end of the memristor is connected in series to the drain electrode of the transistor through a first wire; the grid electrode of the transistor is connected to a fixed voltage # imgabs1 #, and the source electrode of the transistor is grounded; a second wire is led out from the first wire connected with the memristor and the transistor and is connected to the clock end of the T trigger, and the cross connection point of the first wire and the second wire is an output node # imgabs2.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and particularly relates to a 1T1R-based true random number generator circuit and a method for generating random numbers. Background Art

[0002] Hardware true random number generators (TRNGs) generate truly random values using physical processes, which are inherently unpredictable and are more secure than traditional pseudo-random number generators (PRNGs) that rely on deterministic algorithms and seed values. Therefore, they have become an ideal choice for data encryption and secure communication. Mainstream storage technologies, such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory (FLASH), are all based on charge storage. However, as the process size shrinks to 10 nanometers and higher nodes, these memories face serious scalability challenges and are difficult to meet the requirements of future high-energy efficiency, miniaturization, and high-performance TRNGs in terms of power consumption, speed, density, and durability. The resistive random access memory (RRAM), also known as memristor, stands out due to its unique advantages. Compared with other new non-volatile memories, the simple metal-insulator-metal (MIM) structure of the memristor has a lower manufacturing cost and a higher storage density. Its lower programming voltage, faster write / read speed, and better scalability can meet the requirements of both low power consumption and high access speed, making the memristor have great potential in compact and low-power secure hardware design. In addition, when the memristor undergoes high and low resistance state switching, the periodic variation and the noise in the read current constitute two main entropy sources, providing a new method for generating high-quality random numbers with its inherent random characteristics.

[0003] Early TRNGs utilize the random characteristics of the switching voltage or programming state of non-volatile memristors to generate random numbers. These methods typically rely on random variations related to a reference value. When the reference value drifts over time or with the device operating cycle, the randomness may be affected, thereby reducing the reliability of the TRNG. In addition, many TRNG circuits using non-volatile memristors require an additional RESET process to ensure that the state of the memristor can be correctly restored to the initial state. However, this process not only increases power consumption but also affects the system efficiency, making it difficult for TRNG designs to meet the requirements of high speed, low power consumption, and high stability. To overcome these limitations, volatile memristors are introduced into TRNG designs. Different from non-volatile memristors, volatile memristors automatically return to the high-resistance state without applying an external voltage, eliminating the need for an additional reset process, thus reducing the reset power consumption overhead. On the other hand, the volatile memristors after saving the reset step, with their fast response ability, can significantly improve the throughput of the TRNG, enabling it to generate random bitstreams at a higher rate, thereby meeting the requirements of lightweight application scenarios and secure communications for high-speed and high-quality random numbers. However, in most TRNG circuit designs based on volatile memristors, the peripheral circuits usually include logic gates, flip-flops, and clock signal generators, resulting in high power consumption, low throughput, and large area occupation, no longer adapting to the development trend of high integration and low power consumption in lightweight application scenarios. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention proposes a true random number generator circuit based on 1T1R, including a memristor, a transistor, and a T flip-flop; One end of the memristor is connected to the input voltage and the other end is connected in series to the drain of the transistor through a first wire; the gate of the transistor is connected to a fixed voltage , and the source is grounded; a second wire is led out from the first wire connecting the memristor and the transistor and connected to the clock terminal of the T flip-flop, and the cross-connection point of the first wire and the second wire is the output node ; The T flip-flop is used to connect the output node to the clock signal terminal as the input; a stable high-level effective signal High is continuously input to the input terminal T, and as an oscillating signal is continuously input to the clock terminal, the output terminal Q flips with the clock terminal, flipping to record the jump of the memristor device state, realizing a counting-like function; every time a fixed is input for a period of time, the number of flips is random, and finally the output is the result of binarizing the number of flips, and this result is the generated random number, so as to realize a self-clock circuit without an additional high-frequency clock signal generator.

[0005] As a further improvement of the present invention, the memristor is a volatile memristor, and its initial state is a high resistance state.

[0006] As a further improvement of the present invention, the 1T1R structure is prepared by stacking and integrating a transistor and a memristor. Specifically, after forming a silicon dioxide layer on a silicon substrate through thermal oxidation, the gate region is defined through a patterned photolithography process, and the gate thin film is deposited, which is the preparation of the bottom gate; then the gate oxide layer is deposited as an isolation layer; then the channel region is defined through a patterned photolithography process, and the channel layer of the transistor is deposited; the source and drain regions are defined through a patterned photolithography process, and the source and drain electrode layers are deposited by magnetron sputtering; on this basis, the via holes are defined through a patterned photolithography process, that is, the memristor region is defined, which is located above one side of the source / drain electrode, and then the bottom electrode, the interlayer dielectric layer, and the top electrode are sequentially deposited by sputtering.

[0007] As a further improvement of the present invention, the entropy source of the true random number generator circuit utilizes the random oscillation period time of the memristor to continuously provide raw entropy data with a high degree of randomness.

[0008] In a second aspect, the present invention provides a method for generating random numbers based on the above-mentioned true random number generator circuit, including the following steps: Step 1: Input a fixed input voltage at one end of the memristor , and the voltage division effect continuously occurs between the memristor and the transistor. The voltage across the memristor oscillates continuously between being higher than the threshold turn-on voltage and lower than the holding voltage, and jumps and oscillates between the high resistance state and the low resistance state; since the time of each cycle when the memristor switches between the high and low resistance states is random, the number of times the memristor flips within a fixed input time is also random; Step 2: The oscillating output of the output node reflects the flipping state of the memristor and is used as the input to the clock signal terminal of the falling-edge T flip-flop. Therefore, the flipping of the output of the T flip-flop also reflects the random oscillation of the memristor; Step 3: After inputting a fixed time period, the parity of the number of times the memristor flips within this time period is mapped to the output state of the T flip-flop, specifically: the output of the T flip-flop being low level represents logic "0", and the output being high level represents logic "1", realizing the binary expression of the number of flips. When multiple square wave signals with a fixed duty cycle are repeatedly given at the input end, the output of the T flip-flop is to output a string of random numbers.

[0009] Advantages of the present invention: The proposed true random number generator circuit adopts an architecture that combines a volatile memristor with a simple peripheral circuit to generate random numbers. This structure does not require a device reset step in the design. By utilizing the volatile memristor to achieve rapid switching, this circuit design can ensure high-quality randomness of the generated random numbers while effectively improving system throughput, reducing power consumption, and demonstrating good integration potential.

[0010] It can generate a self-oscillating signal without relying on an external clock module. This feature can simplify the peripheral circuit design, reduce system power consumption, and save chip area at the same time.

[0011] The 1T1R structure is applied to the memristor circuit, making the circuit highly integrated, with a relatively simple fabrication process and small chip area occupation.

[0012] The overall circuit structure is simple and is fabricated based on a standard CMOS process platform, with good compatibility and engineering practicability. Description of the Drawings

[0013] Figure 1 is the 1T1R-based TRNG circuit structure of the present invention; Figure 2 is the structure diagram of the memristor of the present invention; Figure 3 is the I-V curve of the volatile memristor of the present invention; Figure 4 is the process fabrication diagram of the 1T1R applied in the TRNG circuit of the present invention; Figure 5 is the method flowchart for the 1T1R-based true random number generator circuit of the present invention to generate random numbers; Figure 6 is the simulation experiment waveform diagram of the present invention.

[0014] In the figure: 1, memristor; 2, T flip-flop; 3, transistor; A1, first wire; A2, second wire; 101, silicon substrate; 102, silicon dioxide layer; 103, bottom gate; 104, gate oxide layer; 105, channel layer; 106, source-drain electrode layer; 107, bottom electrode; 108, interlayer dielectric layer; 109, top electrode. Detailed Embodiments

[0015] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Embodiments are given in the drawings. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thoroughly and comprehensively understood.

[0016] The analyzer in this embodiment is an electrical characteristic parameter analyzer, which is used to accelerate the development of various materials, semiconductor devices and advanced processes, complete process control, reliability analysis and fault analysis, and provide synchronous current-voltage curve testing, that is, I-V curve testing.

[0017] Embodiment 1 As Figure 1 shown, a 1T1R true random number generator circuit includes a memristor 1, a transistor 3 and a T flip-flop 2; the memristor 1 is a volatile memristor, and its initial state is a high-resistance state; Using the metal ion migration mechanism to realize a volatile memristor, its I-V curve is as Figure 3 shown. The volatility of the memristor 1 is specifically manifested as follows: when the voltage across the memristor 1 is greater than its turn-on voltage threshold , the memristor 1 jumps from the high-resistance state to the low-resistance state; when the voltage across the memristor 1 is lower than its holding voltage , the memristor 1 automatically jumps from the low-resistance state to the high-resistance state.

[0018] One end of the memristor 1 is connected to the input voltage , and the other end is connected in series to the drain of the transistor 3 through the first wire A1; the gate of the transistor 3 is connected to a fixed voltage , and the source is grounded; the first wire A1 connecting the memristor 1 and the transistor 3 further leads out a second wire A2 and is connected to the clock terminal of the T flip-flop 2. The cross-connection point of the first wire A1 and the second wire A2 is the output node .

[0019] As Figure 2 shown, the basic structure of the memristor 1 includes a bottom electrode 107, an interlayer dielectric layer 108 and a top electrode 109. Among them, the top electrode 109 is made of Ag, Cu or other active metals, the interlayer dielectric layer 108 usually adopts an oxide dielectric layer, and the bottom electrode 107 is selected from inert metals such as Pt, W, Au or heavily doped silicon.

[0020] As Figure 4 shown, in the true random number generator circuit TRNG, 1T1R (1 Transistor 1 Resistor) uses the process of stacking the memristor 1 on the transistor 3, and five photolithography processes are carried out. The transistor 3 has voltage-controlled conduction characteristics, and its conduction and cut-off are realized by adjusting the gate voltage. The memristor 1 is a simple metal-insulator-metal MIM (Metal-Insulator-Metal) structure, which is prepared on the transistor 3 and has typical volatility.

[0021] The above 1T1R structure is fabricated by stacking and integrating one transistor and one memristor. Specifically, after forming a silicon dioxide layer 102 on a silicon substrate 101 through thermal oxidation, the gate region is defined by a patterned lithography process, and a gate thin film is deposited, which is the fabrication of the bottom gate 103. Then, a gate oxide layer 104 is deposited as an isolation layer. Through a patterned lithography process, the channel region is defined, and the channel layer 105 of transistor 3 is deposited. The source and drain regions are defined by a patterned lithography process, and the source and drain electrode layers 106 are deposited by magnetron sputtering. Thus, the fabrication of transistor 3 is completed. The source / drain electrodes have a symmetric structure and are not clearly defined. On this basis, vias are defined by a patterned lithography process, that is, the memristor region is defined, which is located above one of the source / drain electrodes. Then, the bottom electrode 107, the interlayer dielectric layer 108, and the top electrode 109 are sequentially sputter-deposited, finally realizing the application of 1T1R in the TRNG circuit.

[0022] The entropy source of the TRNG circuit utilizes the random oscillation period time of memristor 1 to continuously provide raw entropy data with a high degree of randomness for subsequent random number generation, ensuring the unpredictability of the output random numbers. This oscillation time is the spontaneous oscillation of the device under voltage division. Each oscillation period time is short and has a high degree of randomness, meeting the requirements for high-speed and high-quality random numbers.

[0023] The T flip-flop 2 is used to connect the output node to the clock signal terminal as an input; the input terminal T continuously inputs a stable high-level valid signal High. As the clock terminal continuously inputs an oscillation signal, the output terminal Q flips with the clock terminal, and the flip records the jump situation of the state of memristor 1 device, realizing a similar counting function; every time a fixed is input for a period of time, the number of flips is random, and finally the output is the result of binarizing the number of flips, and this result is the generated random number, so as to realize a self-clocking circuit without an additional high-frequency clock signal generator.

[0024] Among them, to ensure that memristor 1 can achieve spontaneous flipping, that is, to realize the change of the resistance state of memristor 1, the resistance value of transistor 3 is determined by the following process: The low-resistance state resistance value of memristor 1 is , the holding voltage , the high-resistance state resistance value of memristor 1 is , and the threshold opening voltage . When the input voltage is , according to Ohm's law, the minimum resistance value of transistor 3 is , and the maximum value is . By controlling the gate voltage, the resistance value of transistor 3 can be located within this range. Therefore, the resistance value of transistor 3 in the TRNG circuit is determined by memristor 1 and the input voltage.

[0025] Based on the above, the TRNG circuit proposed by the present invention combines a volatile memristor with a simple peripheral circuit to generate random numbers. This circuit design abandons the device reset step and utilizes the high-speed state flipping characteristic of memristor 1 to achieve high throughput. The circuit achieves significant gains in terms of energy efficiency, throughput, and integration. The 1T1R structure it adopts has the advantages of high integration, relatively simple fabrication process, and small occupied area. This achievement provides a new solution for future information security problems facing resource constraints, high reliability, and energy-saving requirements.

[0026] Embodiment 2 A method for generating random numbers by a 1T1R-based true random number generator circuit includes the following steps: Step 1: Input a fixed input voltage at one end of the memristor , and voltage division effects continuously occur in the memristor and the transistor. The voltage across the memristor oscillates continuously between a voltage higher than the threshold turn-on voltage and a voltage lower than the holding voltage, and jumps and oscillates between the high-resistance state and the low-resistance state; since the time of each cycle during the high-low resistance state switching of the memristor is random, the number of times the memristor flips within a fixed input time is also random; Step 2: The oscillating output of the output node reflects the flipping state of the memristor and is used as the input to the clock signal terminal of the falling-edge T flip-flop. Therefore, the flipping of the output terminal of the T flip-flop also reflects the random oscillation of the memristor; Step 3: After inputting a fixed for a period of time, the parity of the number of times the memristor flips within this period is mapped to the output state of the T flip-flop, specifically: the output of the T flip-flop being at a low level represents logic "0", and the output being at a high level represents logic "1", realizing a binary expression of the number of flips. When multiple square wave signals with a fixed duty cycle are repeatedly given at the input end, the output of the T flip-flop is to output a string of random numbers.

[0027] Based on the above, the random number generation method of the present invention can generate a self-oscillating signal, without an external clock circuit, reducing the peripheral circuit, lowering power consumption, and saving area.

[0028] To further illustrate the method for generating random numbers provided by the present invention, it is described in detail in combination with specific embodiments as follows: As Figure 5 shown, the method for generating random numbers based on the true random number generator circuit provided in Embodiment 1 includes the following steps: Step 1: Apply The voltage is used to implement a gate control mechanism, making the transistor resistance lower than the resistance value of the memristor in the high resistance state and higher than the resistance value of the memristor in the low resistance state; Step 2: Input a fixed input voltage at one end of the memristor , The voltage value is greater than the turn-on voltage threshold of the memristor ; Step 3: The voltage division effect continuously occurs between the transistor and the memristor; in addition, the initial state of the memristor is the high resistance state; Step 4: When the transistor resistance is lower than the high resistance state resistance of the memristor, the input voltage basically falls on the memristor, and the memristor undergoes the first jump, that is, from the high resistance state to the low resistance state; at this time, the transistor resistance is higher than the low resistance state resistance of the memristor, and the input voltage basically falls on the transistor, and the output node output is close to ; Step 5: When the input voltage basically falls on the transistor, when the voltage across the memristor is lower than the holding voltage , the memristor undergoes the second jump, that is, from the low resistance state back to the high resistance state; at this time, the transistor resistance is lower than the high resistance state resistance of the memristor, and the input voltage basically falls on the memristor, the output is close to 0V, and the resistance of the memristor returns to the initial high resistance state; Step 6: Repeat steps 3 to 5, so that the memristor continuously undergoes jumps and oscillations between the high resistance state and the low resistance state, and the output voltage value oscillates spontaneously; Step 7: The output node continues to be used as the input of the clock signal terminal of the falling-edge T flip-flop; Step 8: A stable high-level valid signal High is input to the T input terminal of the T flip-flop. Along with the oscillating signal input at the clock terminal, when the T flip-flop detects the falling edge, the output terminal Q will flip along with the clock terminal; Step 9: After inputting a fixed for a period of time, the parity of the number of flips of the memristor within this period of time is mapped to the output state of the T flip-flop. Specifically, the output of the T flip-flop being low level represents logic "0", and the output being high level represents logic "1", realizing a binary representation of the number of flips. When a multi-segment square wave signal with a fixed duty cycle is repeatedly given at the input terminal, the output of the T flip-flop will output a string of random numbers.

[0029] To verify the performance of the proposed true random number generator circuit, experimental simulations are carried out, and the simulation waveforms are as shown in Figure 6As shown. This simulation mainly verifies the functions of the above circuit, and proves the feasibility and effectiveness of the designed structure in randomness and circuit implementation.

[0030] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several variations and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A 1T1R-based true random number generator circuit, characterized in that, It includes a memristor, a transistor, and a T flip-flop; One end of the memristor is connected to the input voltage and the other end thereof is connected in series to the drain of the transistor through a first wire; The gate of the transistor is connected to a fixed voltage , and the source is grounded; a second wire is led out from the first wire connecting the memristor and the transistor and connected to the clock terminal of the T flip-flop, and the cross-connection point of the first wire and the second wire is the output node ; The T flip-flop is used to connect the output node to the clock signal terminal as an input; the input terminal T continuously inputs a stable high-level valid signal High. As the clock terminal continuously inputs an oscillating signal, the output terminal Q flips with the clock terminal, and the flip records the jump of the memristor device state, realizing a counting-like function; every time a fixed is input for a period of time, the number of flips is random, and finally the output is the result of binarizing the number of flips, and the result is the generated random number.

2. The 1T1R-based true random number generator circuit according to claim 1, wherein The memristor is a volatile memristor, and its initial state is the high-resistance state.

3. The 1T1R-based true random number generator circuit according to claim 1, characterized in that The 1T1R structure is prepared by stacking and integrating a transistor and a memristor. Specifically, after thermally oxidizing to form a silicon dioxide layer on a silicon substrate, the gate region is defined through a patterned photolithography process, and the gate thin film is deposited, which is the preparation of the bottom gate; then the gate oxide layer is deposited as an isolation layer; then the channel region of the transistor is defined through a patterned photolithography process, and the channel layer of the transistor is deposited; the source-drain region is defined through a patterned photolithography process, and the source-drain electrode layer is deposited by magnetron sputtering; on this basis, the via hole is defined through a patterned photolithography process, that is, the memristor region is defined, which is located above one side of the source / drain electrode, and then the bottom electrode, the interlayer dielectric layer, and the top electrode are successively sputter-deposited.

4. The true random number generator circuit based on 1T1R according to claim 1, characterized in that The entropy source of the true random number generator circuit utilizes the random oscillation period time of the memristor to continuously provide high-randomness raw entropy data.

5. A method for generating random numbers based on the 1T1R-based true random number generator circuit according to any one of claims 1-4, characterized in that, It includes the following steps: Step 1: Input an input voltage with a fixed voltage at one end of the memristor , and voltage division effects continuously occur between the memristor and the transistor. The voltage across the memristor oscillates continuously between a voltage higher than the threshold turn-on voltage and a voltage lower than the holding voltage, and jumps and oscillations occur between the high-resistance state and the low-resistance state; since the time of each cycle when the memristor switches between the high and low resistance states is random, the number of flips of the memristor within a fixed-time input is also random; Step 2: Output node The oscillating output reflects the switching state of the memristor and serves as the input to the clock signal terminal of the falling-edge T flip-flop. Therefore, the flip-flop output also reflects the random oscillation of the memristor; Step 3: After inputting a fixed period of time, the parity mapping of the number of flips of the memristor during this period is the output state of the T flip-flop, specifically manifested as: the output of the T flip-flop being low level represents logic "0", and the output being high level represents logic "1", realizing the binary expression of the number of flips. When multiple square wave signals with a fixed duty cycle are repeatedly given at the input end, the output of the T flip-flop i.e., a string of random numbers is output. ​

Images