Wide-level-range high-speed level conversion circuit

Abstract

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a high-speed level conversion circuit with a wide level range. Background Art

[0002] In large-scale digital chip design, in order to reduce the overall power consumption and adapt to the thin oxide layer transistors used in advanced process technologies, the core area of the chip usually operates within a relatively low voltage range, such as 0.8V to 1.2V. However, the main power supply of the chip often needs to be compatible with higher voltage standards such as 3.3V or 5V to meet the communication requirements of traditional peripherals or other chip systems. It is necessary to integrate a level conversion circuit in the chip for logical signal conversion between different voltage domains.

[0003] The level conversion circuits in related technologies, such as Figure 1 shown, mostly adopt a static structure composed of cross-coupled inverters. Its basic form includes two pairs of complementary and symmetric PMOS and NMOS transistors, forming a positive feedback inverting output structure. The input signal controls the conduction state of the cross node via a pair of control NMOS transistors to achieve level conversion from the low voltage domain to the high voltage domain. In Figure 1 the shown structure, nodes A and B can be pulled up to the main power supply voltage at most.

[0004] Under a wide voltage range, especially under the condition of a higher voltage power supply, in order to prevent the device from being at risk of breakdown due to excessive voltage stress, NMOS transistors usually adopt devices with a relatively thick gate oxide layer. However, such NMOS transistors usually operate in a low voltage power supply domain, and the gate drive voltage is limited. Moreover, a relatively thick gate oxide layer is usually accompanied by a relatively high threshold voltage, making it difficult for the NMOS transistor to be fully turned on due to insufficient gate-source voltage, resulting in insufficient pull-down ability, causing the output node not to be pulled down in time, reducing the conversion speed, and even unable to complete an effective level flip. Especially when the drive signal voltage is low, the NMOS transistor may operate in the subthreshold region. Therefore, in order to ensure the normal operation of the level conversion circuit, the size of the NMOS transistor is usually increased to enhance the pull-down ability, but the resulting increase in parasitic capacitance will in turn limit the signal transmission speed.

[0005] In addition, under a wide range of voltages, Figure 1 the pull-up ability of the PMOS transistor in the level conversion circuit is significantly affected by the main power supply voltage of the chip, while the pull-down ability of the NMOS transistor is relatively less affected by the power supply change, resulting in an imbalance in the pull-up and pull-down abilities under different voltage conditions. This mismatch will increase the positive feedback establishment time of the circuit, thereby reducing the speed of the level conversion circuit. Summary of the Invention

[0006] The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, the object of the present invention is to propose a high-speed level conversion circuit with a wide level range, so that the pull-down ability of the level conversion circuit can be adaptively adjusted with the change of the pull-up ability caused by the main supply voltage within a wide voltage range, thereby ensuring the conversion speed within a wide range of voltage changes.

[0007] To achieve the above object, an embodiment of the first aspect of the present invention proposes a high-speed level conversion circuit with a wide level range, including: a level conversion module, a bias voltage generation module, and an input module; the level conversion module includes a first PMOS transistor and a second PMOS transistor; the input module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a signal access selection unit; the first NMOS transistor and the second NMOS transistor are NMOS devices with a voltage level lower than the device level corresponding to the main supply voltage of the chip; The gate of the first NMOS transistor is connected to the input signal, the source is grounded, and the drain is connected to the source of the third NMOS transistor; the gate of the second NMOS transistor is connected to the inverted input signal, the source is grounded, and the drain is connected to the source of the fourth NMOS transistor; The source of the first PMOS transistor is connected to the main supply voltage of the chip, and the drain is connected to the drain of the third NMOS transistor and the gate of the second PMOS transistor at a first node; the source of the second PMOS transistor is connected to the main supply voltage of the chip, and the drain is connected to the drain of the fourth NMOS transistor and the gate of the first PMOS transistor at a second node; The bias voltage generation module is connected to the main supply voltage of the chip and is used to generate a bias voltage; the bias voltage is dynamically adjusted with the change of the main supply voltage of the chip; The signal access selection unit is respectively connected to the gates of the third NMOS transistor and the fourth NMOS transistor and is used to control the gates to be connected to the bias voltage or the ground potential.

[0008] In addition, the high-speed level conversion circuit with a wide level range according to the above embodiment of the present invention may further have the following additional technical features: According to an embodiment of the present invention, the signal access selection unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The sources of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the bias voltage; the gates of the third PMOS transistor and the fifth NMOS transistor are commonly connected to a control signal; the gate of the third NMOS transistor, the drain of the third PMOS transistor, and the drain of the fifth NMOS transistor are connected to a third node; The source electrodes of the fifth NMOS transistor and the sixth NMOS transistor are grounded respectively; the gate electrodes of the fourth PMOS transistor and the sixth NMOS transistor are commonly connected to a control signal; the gate electrode of the fourth NMOS transistor, the drain electrode of the fourth PMOS transistor, and the drain electrode of the sixth NMOS transistor are connected to a fourth node.

[0009] According to an embodiment of the present invention, the control signal is an inverted enable signal.

[0010] According to an embodiment of the present invention, the wide-level-range high-speed level conversion circuit further includes a first capacitor and a second capacitor; One end of the first capacitor is connected to the input signal, and the other end is connected to the third node; One end of the second capacitor is connected to the inverted input signal, and the other end is connected to the fourth node.

[0011] According to an embodiment of the present invention, the generation of the bias voltage is controlled by an inverted enable signal.

[0012] According to an embodiment of the present invention, the bias voltage generation module includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor connected in series in sequence; Wherein, the gate electrode and the drain electrode of each stage of PMOS transistor in the bias voltage generation module are short-circuited and are sequentially connected to the source electrode of the next stage of PMOS transistor; the source electrode of the fifth PMOS transistor is connected to the main power supply voltage of the chip, the gate electrode of the ninth PMOS transistor is connected to the inverted enable signal, and the drain electrode of the ninth PMOS transistor is grounded.

[0013] According to an embodiment of the present invention, the bias voltage is output through the drain electrode of the sixth PMOS transistor.

[0014] According to an embodiment of the present invention, the voltage levels of the first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are adapted to the main power supply voltage of the chip.

[0015] According to an embodiment of the present invention, the first node is connected to a first inverter, and the first inverter outputs the output signal of the level conversion circuit; The second node is connected to a second inverter, and the second inverter outputs the inverted output signal of the level conversion circuit.

[0016] The high-speed level conversion circuit with a wide level range according to an embodiment of the present invention includes a level conversion module composed of a first and a second PMOS transistor, an input module composed of a first to a fourth NMOS transistor and a signal access selection unit, and a bias voltage generation module connected to the main supply voltage of the chip. The input signal and its inverted signal control the conduction of the first and second NMOS transistors, and then pull down the cross-coupled node through the third and fourth NMOS transistors to achieve level inversion. Among them, the first NMOS transistor and the second NMOS transistor are NMOS devices with a voltage level lower than the device level corresponding to the main supply voltage of the chip, which can provide sufficient pull-down ability; the signal access selection unit connects the gates of the third and fourth NMOS transistors to the bias voltage, effectively enhancing their conduction ability, and the bias voltage is automatically adjusted according to the change of the main supply voltage of the chip, so that the gate voltage of the third and fourth NMOS transistors adapts to the power supply change and enhances their driving ability under different voltage conditions. Through the above structural design, while realizing high-speed level conversion, the NMOS pull-down ability can be dynamically adjusted adaptively following the change of the supply voltage, thereby balancing the driving abilities of the pull-up and pull-down paths, effectively improving the level conversion speed and response stability, and being applicable to chips supporting multiple voltage levels. Description of the Drawings

[0017] Figure 1 is a schematic structural diagram of a level conversion circuit in the related art; Figure 2 is a schematic structural diagram of a high-speed level conversion circuit with a wide level range in an embodiment; Figure 3 is a schematic specific structural diagram of a signal access selection unit in an embodiment; Figure 4 is a schematic connection diagram of a first capacitor and a second capacitor in a high-speed level conversion circuit with a wide level range in an embodiment; Figure 5 is a schematic specific structural diagram of a bias voltage generation module in an embodiment; Figure 6 is a schematic connection diagram of an inverter in a high-speed level conversion circuit with a wide level range in an embodiment; Figure 7 is a simulation waveform of a high-speed level conversion circuit with a wide level range when the supply voltage is 5.5V in an embodiment; Figure 8 is a simulation waveform of a high-speed level conversion circuit with a wide level range when the supply voltage is 2.97V in an embodiment.

[0018] Reference Numerals: Level conversion module 10, bias voltage generation module 20, input module 30, signal access selection unit 301, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth NMOS transistor MN6, first capacitor C1, second capacitor C2, first inverter INV1, second inverter INV2, first node A, second node B, third node C, fourth node D, chip main supply voltage VDD, input signal Vin, inverted input signal Vin_b, inverted enable signal Ven_b, bias voltage Vbias, first node output Vout1, second node output Vout2, output signal Vout, inverted output signal Vout_b. Detailed implementation manners

[0019] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0020] The implementation details of the technical solutions of the embodiments of the present application will be described in detail below.

[0021] In one embodiment, as Figure 2 shown, a structural schematic diagram of a wide-level-range high-speed level conversion circuit is provided. The circuit includes a level conversion module 10, an input module 30, and a bias voltage generation module 20. Each module works together to achieve level conversion. The following will describe each module in the circuit in detail.

[0022] The level conversion module 10 includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the chip main supply voltage VDD, that is, the power supply node of the high voltage domain. The drain of the first PMOS transistor MP1 is connected to the first node A, and this node is also connected to the gate of the second PMOS transistor MP2; the drain of the second PMOS transistor MP2 is connected to the second node B, and this node is simultaneously connected to the gate of the first PMOS transistor MP1. Through this cross-connection method, the two PMOS transistors form a positive feedback structure, which is used to accelerate the change of the node potential during level flipping, thereby improving the speed and stability of level conversion.

[0023] The input module 30 includes four NMOS transistors. The gate of the first NMOS transistor MN1 receives an external input signal Vin, its source is grounded, and its drain is connected to the source of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 receives an inverted input signal Vin_b, its source is grounded, and its drain is connected to the source of the fourth NMOS transistor MN4. The drain of the third NMOS transistor MN3 is connected to the first node A, and the drain of the fourth NMOS transistor MN4 is connected to the second node B. Here, the inverted input signal Vin_b is the inverted signal of the input signal Vin. The input signal Vin can be input into an inverter, and the inverter outputs the inverted input signal Vin_b.

[0024] It can be understood that the gate-source voltages of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 determine their conduction degree. Thus, when the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to an effective voltage, that is, the gate-source voltages of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are greater than the cut-off voltage, they are in the conducting state and can limit the drain voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 within a safe range, avoiding overvoltage failure.

[0025] In practical applications, since the third NMOS transistor MN3 and the fourth NMOS transistor MN4 can achieve voltage clamping, the first NMOS transistor MN1 and the second NMOS transistor MN2 here are low-voltage transistors, that is, the first NMOS transistor MN1 and the second NMOS transistor MN2 are NMOS devices with a voltage level lower than the device level corresponding to the main supply voltage VDD of the chip. Since the gate oxide thickness of the first NMOS transistor MN1 and the second NMOS transistor MN2 is less than the standard process, they have the characteristics of a thinner gate oxide layer and a lower threshold voltage, can be quickly turned on under the drive of a low-voltage input signal Vin, and can provide a large pulling-down ability even under the condition of a small size, reducing the input parasitic capacitance and effectively improving the conversion speed.

[0026] Here, the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are respectively connected to a signal access selection unit 301. The signal access selection unit 301 is used to switch and control the potential connected to the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 between the ground potential and the bias voltage Vbias. In the normal working mode, the signal access selection unit 301 connects the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to the bias voltage Vbias to make them have a certain conduction ability to play a voltage-limiting role; in other cases, the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded, making the third NMOS transistor MN3 and the fourth NMOS transistor MN4 cut off.

[0027] Based on this, with the cooperation of the level conversion module 10 and the input module 30, when the input signal Vin is at a high level, the first NMOS transistor MN1 conducts, pulling down the source of the third NMOS transistor MN3. If the gate of the third NMOS transistor MN3 is connected to the bias voltage Vbias, then it conducts, pulling down the first node A and promoting the establishment of positive feedback; conversely, when the input signal Vin is at a low level, the second NMOS transistor MN2 conducts. If the gate of the fourth NMOS transistor MN4 is connected to the bias voltage Vbias, then it conducts, pulling down the second node B through the fourth NMOS transistor MN4 to complete the level inversion in the opposite direction.

[0028] The bias voltage generation module 20 is connected to the main chip supply voltage VDD and is used to generate a bias voltage Vbias lower than the main supply voltage from the main chip supply voltage VDD. Among them, the bias voltage Vbias can be realized by a voltage divider, a bandgap reference circuit, or a bias generation circuit controlled by a current mirror to ensure the stability of Vbias and meet the device requirements of different voltage domains. This bias voltage Vbias serves as the gate drive voltage source for the third NMOS transistor MN3 and the fourth NMOS transistor MN4, providing a bias control basis for the safe and reliable conduction of the clamping transistors.

[0029] In practical applications, the bias voltage generation module 20 obtains the bias voltage Vbias based on the main chip supply voltage VDD. Therefore, when the main chip supply voltage VDD changes, the bias voltage Vbias will also be linearly adjusted accordingly. Through this dynamic adjustment, the bias voltage Vbias can maintain a matching relationship with the main chip supply voltage VDD within the entire main power supply voltage range.

[0030] In a wide level range high-speed level conversion circuit, the bias voltage Vbias is used as the gate voltage of the third NMOS tube MN3 and the fourth NMOS tube MN4, and its change will directly affect the conduction capability of these MOS tubes. Specifically, as the chip main power supply voltage VDD increases, the bias voltage Vbias increases accordingly, increasing the gate voltage of the third NMOS tube MN3 and the fourth NMOS tube MN4, so that the pull-down capability of the third NMOS tube MN3 and the fourth NMOS tube MN4 is enhanced; conversely, when the chip main power supply voltage VDD decreases, the bias voltage Vbias also decreases accordingly, the gate voltage of the third NMOS tube MN3 and the fourth NMOS tube MN4 decreases, and the pull-down capability is weakened. Since the pull-up path in the level conversion circuit is a PMOS device, its conduction capability itself changes with the change of the chip main power supply voltage VDD. Therefore, within the static leakage current range allowed by the power supply current, by making the bias voltage Vbias change linearly with the chip main power supply voltage VDD, the pull-down capability can be dynamically matched with the chip main power supply voltage VDD, thereby maintaining a relative balance between the pull-up and pull-down capabilities, avoiding the problem of slow positive feedback establishment caused by the mismatch between the pull-up and pull-down capabilities, and improving the response speed and stability during the level conversion process.

[0031] It should be noted that the chip main power supply voltage VDD refers to the basic voltage source that provides energy for the main functional modules in the chip, which is usually the core power supply voltage of the chip in the working state. The bias voltage Vbias has different voltage levels from the chip main power supply voltage VDD. Normally, the chip main power supply voltage VDD is a higher power supply voltage level, such as 3.3V, 5V or higher. The bias voltage Vbias is an intermediate voltage or a low voltage level generated by the bias voltage generating module 20, such as 1.65V or 2.5V. In a wide level range and high-speed level conversion circuit, by forming a voltage gradient between the bias voltage Vbias and the chip main power supply voltage VDD, the gate drive capability can be effectively adjusted and the device reliability can be protected, ensuring the normal operation of the level conversion circuit in a multi-voltage environment.

[0032] In the level conversion circuit, the converted signal is outputted externally through the first node A and the second node B, that is, the first node outputs Vout1 and the second node outputs Vout2. When the input signal Vin changes from a low level to a high level, the voltage of the first node A decreases and the voltage of the second node B increases, thereby realizing the conversion of the input low voltage signal to a high voltage level within the chip main power supply voltage VDD range; conversely, when the input signal Vin changes from a high level to a low level, the voltage of the first node A increases and the voltage of the second node B decreases, realizing the reverse conversion from a high voltage level to a low voltage level.

[0033] In the above high-speed level conversion circuit with a wide level range, by introducing the cascaded structure of the low-voltage input transistor and the clamping protection transistor, the high conduction efficiency of the first NMOS transistor MN1 and the second NMOS transistor MN2 can be fully utilized under the high-voltage domain, significantly improving the speed and energy efficiency of level conversion. At the same time, it ensures that the first NMOS transistor MN1 and the second NMOS transistor MN2 operate within a safe voltage range, achieving reliability control and performance balance under a wide voltage range. Coupled with the dynamically adjustable bias control mechanism and the signal access selection module, the pull-down ability in the circuit can be adaptively adjusted following the pull-up ability, realizing the dynamic balance between the pull-down ability and the pull-up ability within a wide voltage range.

[0034] In practical applications, to adapt to the voltage range and performance requirements under different processes, a cooperative optimization mechanism between the device and the bias voltage Vbias is introduced in the circuit parameter design. Specifically, there is a trade-off relationship in the conduction ability among the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4: if a low-voltage input transistor with lower breakdown voltage and higher speed is selected, the bias voltage Vbias needs to be set lower to prevent the drain terminals of the first NMOS transistor MN1 and the second NMOS transistor MN2 from overvoltage. However, reducing the bias voltage Vbias may lead to insufficient conduction ability of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, thus affecting the performance of the pull-down path; conversely, if a low-voltage transistor with higher breakdown voltage is selected, the bias voltage Vbias can be set higher to enhance the conduction ability of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, but at the same time, it will increase the threshold voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, resulting in a decrease in conduction ability. Therefore, it is necessary to comprehensively consider the specific process conditions and select the appropriate type of input device and the bias voltage Vbias to maximize the overall level conversion performance.

[0035] In one embodiment, as Figure 3 shown, Figure 3 FIG. shows the specific structural schematic diagram of the signal access selection unit 301. The signal access selection unit 301 is used to control the gate potentials of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to achieve their dynamic switching between the bias voltage Vbias and the ground potential.

[0036] The signal access selection unit 301 includes two PMOS transistors and two NMOS transistors, namely the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6. Specifically, the source of the third PMOS transistor MP3 is connected to the bias voltage Vbias, and the drain is connected to an intermediate node (the third node C), which is electrically connected to the gate of the third NMOS transistor MN3; while the drain of the fifth NMOS transistor MN5 is also connected to the third node C, and the source is grounded. The gates of the third PMOS transistor MP3 and the fifth NMOS transistor MN5 both receive the control signal. The source of the fourth PMOS transistor MP4 is connected to the bias voltage Vbias, and the drain is connected to an intermediate node (the fourth node D), which is electrically connected to the gate of the fourth NMOS transistor MN4; while the drain of the sixth NMOS transistor MN6 is also connected to the fourth node D, and the source is grounded. The gates of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6 both receive the control signal.

[0037] Among them, when the control signal is at a low level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, while the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned off. The third node C and the fourth node D are pulled up to the bias voltage Vbias, and the gate voltages of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are the bias voltage Vbias, so they are in the on state; when the control signal is at a high level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, while the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on, and the third node C and the fourth node D are pulled to the ground potential, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off.

[0038] In one embodiment, the control signal is the inverted enable signal Ven_b, that is, the inverted signal of the enable signal Ven. The enable signal Ven can be input into an inverter, and the inverter outputs the inverted enable signal Ven_b. When the inverted enable signal Ven_b is at a low level, it indicates that the level conversion circuit is in the working state; when the inverted enable signal Ven_b is at a high level, it indicates that the level conversion circuit is in the off or standby state. Driven by this control signal, the signal access selection unit 301 dynamically controls the gate voltages of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, thereby realizing the regulation of their conduction states.

[0039] Specifically, the gates of the third PMOS transistor MP3 and the fifth NMOS transistor MN5 in the signal access selection unit 301 jointly receive the inverted enable signal Ven_b, and the gates of the fourth PMOS transistor MP4 and the sixth NMOS transistor MN6 also receive this inverted enable signal Ven_b. When the inverted enable signal Ven_b is at a low level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, while the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned off. The third node C and the fourth node D are pulled up to the bias voltage Vbias, enabling the gate voltages of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to access the bias voltage Vbias, and thus being in the on state. In this state, the input signal Vin can be effectively pulled down through the first NMOS transistor MN1 and the third NMOS transistor MN3 or the second NMOS transistor MN2 and the fourth NMOS transistor MN4, which helps to quickly establish the positive feedback process of the level conversion circuit, thereby achieving high-speed and stable level inversion.

[0040] Conversely, when the inverted enable signal Ven_b is at a high level, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, and the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are turned on. The third node C and the fourth node D are pulled to the ground potential, causing the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to turn off, thereby disconnecting the pull-down path between the input signal Vin and the cross-coupled PMOS network and turning off the level conversion circuit.

[0041] In practical applications, when the level conversion circuit needs to perform a level conversion on the input signal Vin, a valid enable signal Ven is generated. At this time, under the inverted enable signal Ven_b, the signal access selection module enables the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to access the bias voltage Vbias and be in the on state. The on-state third NMOS transistor MN3 and fourth NMOS transistor MN4, as important components of the input pull-down path, together with the first NMOS transistor MN1, the second NMOS transistor MN2, and the pull-down path of the cross-coupled PMOS network, ensure that the level conversion circuit can quickly complete the level inversion of the input signal Vin.

[0042] In one embodiment, as Figure 4As shown, the wide-level-range high-speed level conversion circuit further includes a first capacitor C1 and a second capacitor C2, which are used to accelerate the establishment of positive feedback during the level conversion process through capacitive coupling. One end of the first capacitor C1 is connected to the input signal Vin, and the other end is connected to the third node C. One end of the second capacitor C2 is connected to the inverted input signal Vin_b, and the other end is connected to the fourth node D. Under this connection relationship, the voltage change of the input signal Vin can be quickly coupled to the third node C, thereby directly acting on the gate voltage of the third NMOS transistor MN3; similarly, the voltage change of the inverted input signal Vin_b can be coupled to the fourth node D and act on the gate voltage of the fourth NMOS transistor MN4.

[0043] When the level conversion circuit is in the working state, that is, the inverted enable signal Ven_b is at a low level, the signal access selection unit 301 pulls up the third node C and the fourth node D to the bias voltage Vbias, so that the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are in the conducting state. At this time, the first capacitor C1 and the second capacitor C2 can quickly transfer the edge changes of the input signal Vin and its inverted signal to the third node C and the fourth node D, thereby improving the conduction speed of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, accelerating the driving ability of the cross-coupled PMOS network, shortening the establishment time of the positive feedback loop, and helping to improve the response speed of the entire level conversion process and the flipping speed of the signal edge.

[0044] In one embodiment, the generation of the bias voltage Vbias is controlled by the inverted enable signal Ven_b, that is, the working state of the bias voltage generation module 20 is controlled by the inverted enable signal Ven_b. When the inverted enable signal Ven_b is at a low level, it indicates that the level conversion circuit is in the working state, the bias voltage generation module 20 is activated, and a stable bias voltage Vbias is output, which can provide the bias voltage Vbias to the signal access selection unit 301 to drive the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, thereby realizing the normal operation of the level conversion circuit.

[0045] When the inverted enable signal Ven_b is at a high level, it indicates that the level conversion circuit is in a non-working or standby state. At this time, the bias voltage generation module 20 stops working, the output of the bias voltage Vbias is turned off, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are kept in the cut-off state, thereby disconnecting the driving path of the input signal to the cross-coupled network and avoiding unnecessary power consumption.

[0046] In one embodiment, as Figure 5 shown, Figure 5The specific structural schematic diagram of the bias voltage generation module 20 is shown. The bias voltage generation module 20 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP9 connected in series in sequence. Among them, the source of the fifth PMOS transistor MP5 is connected to the main chip supply voltage VDD, and the drain of the ninth PMOS transistor MP9 is grounded.

[0047] In the series structure, the gate and drain of each stage of PMOS transistor are short-circuited and connected to the source of the next stage of PMOS transistor. Specifically: the gate and drain of the fifth PMOS transistor MP5 are connected together and connected to the source of the sixth PMOS transistor MP6; the gate and drain of the sixth PMOS transistor MP6 are connected together and connected to the source of the seventh PMOS transistor MP7; the gate and drain of the seventh PMOS transistor MP7 are connected together and connected to the source of the eighth PMOS transistor MP8; the gate and drain of the eighth PMOS transistor MP8 are connected together and connected to the source of the ninth PMOS transistor MP9. The gate of the ninth PMOS transistor MP9 receives the inverted enable signal Ven_b, which is used to control the generation state of the bias voltage Vbias.

[0048] When the inverted enable signal Ven_b is at a low level, the ninth PMOS transistor MP9 is turned on, and the entire series bias structure is turned on, forming voltage drops in sequence, and forming a set of voltage distributions at each connection node, so as to generate the bias voltage Vbias through the series PMOS transistor network in the bias voltage generation module 20. On the contrary, when the inverted enable signal Ven_b is at a high level, the ninth PMOS transistor MP9 is turned off, the series connection path is disconnected, the entire bias voltage link is interrupted, and the output of the bias voltage Vbias is turned off. Through this structural design, the generation of the bias voltage Vbias is directly related to the state of the inverted enable signal Ven_b.

[0049] In one embodiment, the bias voltage Vbias is output through the drain of the sixth PMOS transistor MP6 in the bias voltage generation module 20. Specifically, since the bias voltage generation module 20 adopts a multi-stage series PMOS transistor structure, where the gate and drain of each stage of PMOS transistor are short-circuited and connected to the source of the next stage, a stable intermediate potential is formed between the drain of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7.

[0050] When the inverting enable signal Ven_b is at a low level, the ninth PMOS transistor MP9 is turned on, and the entire PMOS series link is turned on. An equivalent voltage division relationship is established between levels according to the main chip supply voltage VDD. In this state, there is a certain voltage drop at the drain of the sixth PMOS transistor MP6 compared to the main chip supply voltage VDD, which is suitable for use as the bias voltage Vbias and is thus provided to the signal access selection unit 301 in the wide-level-range high-speed level conversion circuit.

[0051] In practical applications, the bias voltage Vbias is generated by the PMOS transistors connected in series in the bias voltage generation module 20. Therefore, under the condition of different process corner variations, its voltage output still has good stability and consistency. In addition, since the leakage current of the PMOS transistor in the subthreshold region is extremely small, the static current loss of this structure in the enabled state is very low, and the maximum static power consumption of the entire bias voltage generation module 20 under the worst process corner condition is still less than 1 μA.

[0052] In one embodiment, the voltage levels of the first PMOS transistor MP1, the second PMOS transistor MP2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are adapted to the main chip supply voltage VDD, that is, the process levels of these devices can withstand and adapt to the voltage range corresponding to the main chip supply voltage VDD. For example, when the main supply voltage VDD is 5V, these PMOS devices and NMOS devices are selected as high-voltage level devices (such as 5V or higher level process devices). Through this matching design of device voltage levels, it can be ensured that the key devices in the level conversion circuit do not suffer breakdown or overvoltage failure during operation, thereby improving the voltage compatibility and long-term reliability of the overall circuit.

[0053] In one embodiment, as Figure 6 shown, the level conversion circuit includes two inverters, which are respectively used to obtain the converted signals from different nodes of the level conversion module 10. Among them, the first node A is connected to the first inverter INV1, and the first inverter INV1 is used to invert the level signal of the first node A and output it as the forward output signal Vout of this level conversion circuit. The second node B is connected to the second inverter INV2, and the second inverter INV2 also inverts the level signal of the second node B and outputs it as the inverted output signal Vout_b of this level conversion circuit.

[0054] Based on this, the overall working process of the wide-level-range high-speed level conversion circuit is described in combination with Figures 2 to 6 this.

[0055] When the enable signal Ven is at a high level, the bias voltage generation module 20 operates normally, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, so that the third node C and the fourth node D are respectively biased to the bias voltage, thereby turning on the third NMOS transistor MN3 and the fourth NMOS transistor MN4; when the enable signal Ven is at a low level, the corresponding inverted signal is at a high voltage. At this time, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, and the fifth NMOS transistor MN5 and the sixth NMOS are turned on, pulling the third node C and the fourth node D to the ground potential, and then turning off the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0056] Assume that in the initial state, the enable signal Ven is at a high level, the input signal is at a low level, and the inverted signal is at a high level. Then the first NMOS transistor MN1 is turned off, the second NMOS transistor MN2 is turned on, the second node B is pulled to a low level, the first PMOS transistor MP1 is turned on, pulling up the first node A, and at the same time the second PMOS transistor MP2 is in a cut-off state.

[0057] When the input signal jumps from a low level to a high level, the first NMOS transistor MN1 is turned on, and the mutation of the input signal injects charge into the third node C through the first capacitor C1, making the third node C stable at a higher potential during the period when the input signal is high, further enhancing the conduction ability of the third NMOS transistor MN3. At this time, the first node A forms a path to the ground through the first MOS transistor and the third MOS transistor. Since the second node B is still at a low level at this time, the first PMOS transistor MP1 is in a conducting state, so there is a process in which the first PMOS transistor MP1 pulls up the first node A, and the first NMOS transistor MN1 and the second NMOS transistor MN2 pull down the first node A. The potential of the first node A gradually decreases under the combined action of the two.

[0058] At the same time, when the input signal jumps from a low level to a high level, the inverted input signal Vin_b changes from a high level to a low level, the second NMOS transistor MN2 is turned off, and the mutation of the inverted input signal Vin_b discharges through the second capacitor C2 to the fourth node D, making the fourth node D stable at a lower potential, inhibiting the conduction of the fourth NMOS transistor MN4, and thus blocking the path of the second node B to the ground. The decrease in the voltage of the first node A prompts the second PMOS transistor MP2 to turn on, pulling up the second node B. The pulling up of the second node B further turns off the first PMOS transistor MP1, thereby accelerating the decrease of the first node A, and a positive feedback process is quickly established, finally realizing the high-speed flip of the signal.

[0059] When the main supply voltage VDD of the chip increases, during the above signal inversion process, the pull-up ability of the first PMOS transistor MP1 to the first node A will be enhanced. In the wide-level-range high-speed level conversion circuit of this embodiment, since the bias voltage Vbias increases synchronously with the main supply voltage VDD of the chip, the gate voltage of the third NMOS transistor MN3 increases, thereby reducing the impedance of the ground path formed by the first NMOS transistor MN1 and the third NMOS transistor MN3, enhancing the pull-down ability, and effectively eliminating the influence of the power supply voltage change on the positive feedback establishment speed.

[0060] In practical applications, the performance of the wide-level-range high-speed level conversion circuit was simulated and verified. The input signal voltage was set to 0.99V. After comprehensively considering the trade-off relationship between the input transistor and the bias voltage Vbias, a low-voltage transistor with 2.5V was selected as the input device, that is, used as the first NMOS transistor MN1 and the second NOMS transistor, and a reasonable bias voltage Vbias was set to avoid overvoltage at the drain end of the input transistor.

[0061] The simulation was carried out under the conditions of an ambient temperature of 25°C and the slow-slow (SS, Slow-Slow) process corner. Among them, the SS process corner means that the manufacturing parameters of both NMOS transistors and PMOS transistors are in the slowest limit state, used to simulate the circuit performance under the most unfavorable manufacturing conditions. During the simulation process, the working state of the circuit was evaluated by detecting the signal change of the second node B. Figure 7 and Figure 8 respectively show the simulation waveforms when the main supply voltage VDD of the chip is 5.5V and 2.97V. The simulation results show that during the process of the 125MHz input signal transitioning from a low level to a high level, the second node B is pulled up to a high level after a certain delay; when the 125MHz input signal transitions from a high level to a low level, the second node B is pulled down to a low level after a certain delay. Specifically, in the case where the main supply voltage VDD of the chip is 5.5V as shown in Figure 7 , the average value of the bias voltage Vbias is 3.11V. After the input signal transitions from a low level to a high level, the level of the second node B rises from 0.99V to 5.5V, its falling delay is 545ps, and its rising delay is 552ps. In the case where the main supply voltage VDD of the chip is 2.97V as shown in Figure 8 , the average value of the bias voltage Vbias drops to 1.49V, and the corresponding level of the second node B changes from 0.99V to 2.97V, its falling delay is 526ps, and its rising delay is 664ps.

[0062] It can be seen that the high-speed level conversion circuit with a wide level range in this embodiment still has good level conversion ability within a wide voltage range, and maintains a small delay difference under different supply voltages, demonstrating the effective matching of the pull-up and pull-down capabilities under dynamic conditions and the stability of the conversion speed.

[0063] In the above embodiment, the high-speed level conversion circuit with a wide level range effectively controls the conduction state of the pull-down path by introducing the third NMOS transistor MN3 and the fourth NMOS transistor MN4 into the input module 30 and using the signal access selection unit 301 to control the gate voltage to access the bias voltage Vbias or the ground potential. The level conversion module 10 is constructed with the first PMOS transistor MP1 and the second PMOS transistor MP2 to form a positive feedback structure, which is beneficial to improving the conversion speed. At the same time, the bias voltage generation module 20 is dynamically associated with the main supply voltage VDD of the chip, and can adaptively adjust the bias voltage Vbias when the supply voltage changes, so as to maintain the matching relationship between the conduction capabilities of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 and the supply voltage, enabling the level conversion circuit to still maintain the balance of the pull-up and pull-down capabilities within a wide voltage range, and avoiding problems such as insufficient establishment of positive feedback and decreased response speed caused by changes in the power supply voltage in the traditional structure. Based on this, the level conversion circuit is not only applicable to a wide range of power supply voltages (such as 2.97V to 5.5V), but also can achieve high-speed and stable logic level conversion, with good power adaptability and response performance, and is particularly suitable for chip design scenarios that need to support multiple voltage standards.

[0064] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0065] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0066] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A high-speed level conversion circuit with a wide level range, characterized in that, Comprising: A level conversion module, a bias voltage generation module, and an input module; the level conversion module includes a first PMOS transistor and a second PMOS transistor; the input module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a signal access selection unit; the first NMOS transistor and the second NMOS transistor are NMOS devices with a voltage level lower than the device level corresponding to the main supply voltage of the chip. The gate of the first NMOS transistor is connected to the input signal, the source is grounded, and the drain is connected to the source of the third NMOS transistor; the gate of the second NMOS transistor is connected to the inverted input signal, the source is grounded, and the drain is connected to the source of the fourth NMOS transistor. The source of the first PMOS transistor is connected to the main supply voltage of the chip, and the drain is connected to the drain of the third NMOS transistor and the gate of the second PMOS transistor at a first node; the source of the second PMOS transistor is connected to the supply voltage of the chip, and the drain is connected to the drain of the fourth NMOS transistor and the gate of the first PMOS transistor at a second node. The bias voltage generation module is connected to the main supply voltage of the chip and is used to generate a bias voltage; the bias voltage is dynamically adjusted with the change of the main supply voltage of the chip. The signal access selection unit is respectively connected to the gates of the third NMOS transistor and the fourth NMOS transistor and is used to control the gates to be connected to the bias voltage or the ground potential.

2. The high-speed level conversion circuit with a wide level range according to claim 1, wherein The signal access selection unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The sources of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the bias voltage; the gates of the third PMOS transistor and the fifth NMOS transistor are commonly connected to a control signal; the gate of the third NMOS transistor, the drain of the third PMOS transistor, and the drain of the fifth NMOS transistor are connected to a third node. The sources of the fifth NMOS transistor and the sixth NMOS transistor are respectively grounded; the gates of the fourth PMOS transistor and the sixth NMOS transistor are commonly connected to a control signal; the gate of the fourth NMOS transistor, the drain of the fourth PMOS transistor, and the drain of the sixth NMOS transistor are connected to a fourth node.

3. The high-speed level conversion circuit with a wide level range according to claim 2, wherein The control signal is an inverted enable signal.

4. The high-speed level conversion circuit with a wide level range according to claim 2, characterized in that, The wide-level-range high-speed level conversion circuit further includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the input signal, and the other end is connected to the third node. One end of the second capacitor is connected to the inverted input signal, and the other end is connected to the fourth node.

5. The high-speed level conversion circuit with a wide level range according to claim 1, characterized in that, The generation of the bias voltage is controlled by the inverted enable signal.

6. The high-speed level conversion circuit with a wide level range according to claim 5, characterized in that, The bias voltage generation module includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor connected in series in sequence. Among them, the gates and drains of each stage of PMOS transistors in the bias voltage generation module are short-circuited and connected to the sources of the next-stage PMOS transistors in sequence; the source of the fifth PMOS transistor is connected to the main power supply voltage of the chip, the gate of the ninth PMOS is connected to the inverted enable signal, and the drain of the ninth PMOS transistor is grounded.

7. The high-speed level conversion circuit with a wide level range according to claim 6, wherein The bias voltage is output through the drain of the sixth PMOS transistor.

8. The high-speed level conversion circuit with a wide level range according to claim 1, characterized in that The voltage levels of the first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are adapted to the main power supply voltage of the chip.

9. The high-speed level conversion circuit with a wide level range according to claim 1, characterized in that, The first node is connected to the first inverter, and the first inverter outputs the output signal of the level conversion circuit; The second node is connected to the second inverter, and the second inverter outputs the inverted output signal of the level conversion circuit.

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