Early exit error location polynomial determination

Abstract

A method may include generating a state signal indicating a state of error location polynomial (ELP) determination by an ELP determination circuit; and control the ELP determination by the ELP determination circuit in response, at least in part, to a value of the status signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Ser. No. 63 / 387,639, filed on Dec. 15, 2022, entitled “EARLY EXIT FROM ERROR - LOCATOR POLYNOMIAL CALCULATION”, the content and disclosure of which are incorporated herein by reference in their entireties. Technical Field

[0003] Examples generally relate to determining an error - locator polynomial and a decoder that utilizes the error - locator polynomial. More specifically, one or more examples relate to early - exiting from an error - locator polynomial (ELP) determination based on a state determined for the ELP. In one or more examples, if it is determined that an estimated ELP is the final ELP, further iterations of the ELP determination may be omitted. Background Art

[0004] An error - locator polynomial (ELP) is a polynomial expression, where the roots of the expression represent an error pattern in a data block. The ELP is used in a variety of operational contexts, including Reed - Solomon (RS) decoders and Bose–Chaudhuri–Hocquenghem (BCH) decoders. Brief Description of the Drawings

[0005] To easily identify the discussion of any particular element or action, the most significant digit in the reference numeral refers to the figure number in which the element was first introduced.

[0006] Figure 1 is a block diagram depicting an apparatus for determining an error - locator polynomial (ELP) at least in part based on a state signal, where the state signal indicates a state of the ELP determination.

[0007] Figure 2 depicts a matrix equation for determining a difference value.

[0008] Figure 3 is a flowchart depicting a process for determining an error - locator polynomial (ELP) at least in part based on a state signal.

[0009] Figure 4 is a flowchart depicting a process for determining a state of an ELP determination.

[0010] Figure 5 is a flowchart depicting a process for setting a status signal indicative of a status determined by ELP according to one or more examples.

[0011] Figure 6 is a flowchart depicting a process for controlling the ELP determination according to one or more examples.

[0012] Figure 7 Illustrates an example process for controlling the ELP determination according to one or more examples.

[0013] Figure 8 Illustrates an example process for error correcting a codeword according to one or more examples.

[0014] Figure 9 is a block diagram of an RS decoder depicting Reed - Solomon decoding for providing an early exit from the ELP determination according to one or more examples.

[0015] Figure 10 Illustrates a process according to one or more examples.

[0016] Figure 11 is a block diagram of a circuit that may be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. Detailed Description

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part of this disclosure, and in which specific examples of examples in which the disclosure may be practiced are shown by way of illustration. The examples are described in sufficient detail to enable those of ordinary skill in the art to practice the disclosure. However, other examples may be utilized and changes in structure, materials, and processes may be made without departing from the scope of the disclosure.

[0018] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations of examples for describing the disclosure. The accompanying drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbers; however, the similarity of the numbers does not mean that the structure or component must be the same in terms of size, composition, configuration, or any other property.

[0019] The following description may include examples to assist those of ordinary skill in the art in practicing the disclosed examples. The use of the terms "exemplary," "by way of example," and "for example" means that the relevant description is illustrative, and while the scope of the disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples of the disclosure to the specified components, steps, features, or functions, etc.

[0020] It should be readily understood that the components of the examples, as generally described herein and illustrated in the figures, can be arranged and designed in a variety of different configurations. Accordingly, the following description of the various examples is not intended to limit the scope of the present disclosure, but merely represents the various examples. While aspects of the examples may be presented in the figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0021] In addition, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure with unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic between various blocks are examples of a particular specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure may be practiced with many other partitioning solutions. In most instances, details regarding timing considerations and the like have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0022] Those of ordinary skill in the art will understand that any of a variety of different technologies and techniques can be used to represent information and signals. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art should understand that a signal can represent a signal bus, where the bus can have a variety of bit widths, and the present disclosure can be implemented on any number of data signals, including a single data signal.

[0023] The various illustrative logical blocks, modules, and circuits described in connection with the examples disclosed herein can be implemented or executed with a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply a host) can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer that is configured to execute computing instructions (e.g., software code) related to the examples of the present disclosure is considered a special-purpose computer when it includes a processor.

[0024] Examples may be described with reference to processes depicted as flowcharts, process schematics, structural diagrams, or block diagrams. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the acts may be rearranged. A process may correspond to a method, thread, function, procedure, subroutine, or subprogram, but is not limited thereto. Further, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or transmitted on a computer-readable medium as one or more instructions or code. A computer-readable medium includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.

[0025] Any reference in this document to elements using terms such as "first", "second", etc. does not limit the number or order of those elements, unless such limitations are expressly stated. Instead, these terms may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must in some way precede the second element. In addition, unless otherwise specified, a group of elements may include one or more elements.

[0026] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which the given parameter, property, or condition is satisfied with a minor degree of variance that would be understood by one of ordinary skill in the art, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0027] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", but not limited thereto) are used for clarity and convenience in understanding the present disclosure and the drawings, and such relational terms do not imply or depend on any particular preference, orientation, or order, unless the context clearly indicates otherwise.

[0028] In this description, the terms "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and has the same meaning, unless expressly indicated otherwise or the context would otherwise indicate to one of ordinary skill in the art.

[0029] A typical method for solving the error-location polynomial (ELP) is to complete all 2*t iterations of the Berlekamp-Massey (“Berlekamp”) algorithm, where t is the highest number of errors that can be corrected by the corresponding instance of the Berlekamp algorithm. The Berlekamp algorithm continues to evolve the ELP even after convergence to the ELP.

[0030] This allows the ELP to determine a consistent latency (e.g., always having the same latency, but not limited thereto), which reduces the burden in any overall circuit flow integrated within a device. A typical RS decoder attempts to maintain a consistent latency regardless of the number of errors in a forward error correction (FEC) data block (“FEC block”). In actual system operation, those FEC blocks with a low number of errors (0 or 1 symbol in error) are the most common, while those FEC blocks with t or t - 1 errors are rare. However, even for FEC blocks with t or t - 1 errors, a standard Reed-Solomon decoder typically must maintain the overall system throughput.

[0031] The latency of a typical RS decoder is generally related to the highest number of errors that the decoder can correct for a given application. The ELP calculation is typically completed using 2*t iterations, where t is the highest error-correction capability of the decoder. For latency-critical systems, it is desirable to reduce the RS decoder latency.

[0032] During the corresponding iteration of the ELP determination, the Berlekamp algorithm determines a difference value (also referred to herein as the “Berlekamp difference value”), which represents the difference between the error pattern that can be detected by the current version of the ELP (the current version of the ELP at various iterations is referred to herein as the “estimated ELP” or “corresponding ELP”) and the error pattern indicated by the syndrome.

[0033] If the difference value at any iteration is zero and all future difference values are zero, the estimated ELP is the final ELP. If the state of the ELP determination is stable in an iteration earlier than the 2*t iterations, it may be desirable to exit the ELP determination before performing all 2*t iterations of the Berlekamp algorithm.

[0034] One or more examples generally relate to determining an early-exit condition for the Berlekamp algorithm. The estimated ELP is used to determine whether all difference values for subsequent iterations of the Berlekamp algorithm are zero.

[0035] The ELP determination block that provides for early exit discussed herein, or an RS decoder that includes such an ELP determination block, may exhibit reduced latency (e.g., the duration from the input of a codeword to the corresponding output, but not limited thereto). For example, if the number of errors is v, the latency of the ELP determination with the early exit option is 2*v, rather than 2*t as in the typical case.

[0036] Figure 1 is a block diagram depicting an apparatus 100 for determining an error-locator polynomial (ELP) based at least in part on a status signal, where the status signal indicates the status of the ELP determination.

[0037] Apparatus 100 includes an ELP determination circuit 102 and an early exit logic circuit 122. The early exit logic circuit 122 includes an ELP determination status logic component 104 and an exit condition logic component 110.

[0038] In one or more examples, the ELP determination circuit 102 generates an ELP 112 based at least in part on a syndrome 114. The ELP determination circuit 102 receives the syndrome 114, determines the ELP 112 associated with the syndrome 114, and provides the determined ELP 112. A "codeword" is a sequence of symbols. The ELP determination circuit 102 determines the ELP 112 based on the syndrome 114 having coefficients that indicate the location of one or more of the errors in the codeword associated with the syndrome 114, as discussed below. An "error" is a difference between the current form of a codeword and its original or expected form. Non-limiting examples of errors include, but are not limited to, symbol errors, burst errors, or erasure errors. As a non-limiting example, such differences may be caused during the transmission (e.g., via an electronic communication system, but not limited thereto) or storage (e.g., via a data storage device, but not limited thereto) of the codeword associated with the syndrome 114.

[0039] In one or more examples, the syndrome 114 is a syndrome vector (e.g., the syndrome vector includes one or more syndromes, but not limited thereto). The syndrome 114 indicates the presence (and implicitly or explicitly indicates the absence) of errors in the codeword and the location of the errors in the codeword. The location of the errors in the codeword may also be referred to herein as an "error pattern" in this document. A corresponding syndrome corresponds to a corresponding specific error pattern. For a given code (e.g., FEC coding technique, but not limited thereto) that can correct up to t errors, 2*t syndromes 114 are determined on the codeword.

[0040] A corresponding syndrome 114 can be received from a syndrome calculator (not depicted). The ELP determination circuit 102 determines the ELP 112 over one or more iterations based at least in part on the syndrome 114. The coefficients of the ELP 112 are set such that the location of an error in a codeword associated with the syndrome 114 can be determined based at least in part on the coefficients, as discussed below.

[0041] In one or more examples, the ELP determination circuit 102 can determine the ELP 112 based at least in part on the Berlekamp algorithm. During ELP determination, the Berlekamp algorithm iteratively refines the ELP, including changing the coefficients of the ELP. The Berlekamp algorithm makes 2*t iterations to complete the ELP determination. By the end of the i-th iteration, the Berlekamp algorithm has evolved (e.g., changed, but not limited to) the ELP such that the difference value (V*ELP - Si)=0, where Si is the i-th syndrome, the syndrome (e.g., syndrome 114, but not limited to) is a vector of v syndromes represented by their subscripts [Si-1 Si-2,…,Si-v], and the ELP (e.g., ELP 112, but not limited to) is a vector of v coefficients of the ELP [σ1,σ2,…,σv].

[0042] During the corresponding iteration, the Berlekamp algorithm determines a difference value (also referred to herein as the "Berlekamp difference value"), which represents the difference between the error pattern indicated by the current version of the ELP (the current version of the ELP in various iterations can also be referred to herein as the "estimated ELP") and the error pattern indicated by the syndrome 114. As a non-limiting example, a difference value of zero indicates no difference, and a non-zero difference value indicates a difference. A zero difference value means that all errors represented by the current syndrome can be detected by the estimated ELP. A non-zero difference value means that all errors represented by the current syndrome cannot be detected by the estimated ELP.

[0043] The Berlekamp algorithm changes the coefficients of the estimated ELP to account for the discrepancy value, i.e., to reduce the difference between the error pattern indicated by the estimated ELP and the error pattern indicated by the syndrome 114. The iterative process continues until the Berlekamp algorithm converges to an ELP that accurately detects the error pattern indicated by the syndrome 114. When the Berlekamp algorithm of the ELP determination circuit 102 determines that the estimated ELP accurately detects the error pattern indicated by the syndrome 114, the Berlekamp algorithm does not change the coefficients of the estimated ELP. In one or more examples, the ELP determination circuit 102 may stop changing the coefficients of the ELP and provide the ELP as the ELP 112 in response to completing all 2*t iterations of the Berlekamp algorithm, or in response to the assertion of the ELP completion signal 120 regardless of whether all 2*t iterations of the Berlekamp algorithm are completed, as discussed below. The ELP 112 can be utilized to locate and correct errors in the codeword associated with the syndrome 114. As a non-limiting example, the reciprocal roots of the coefficients of the ELP 112 indicate the locations of the errors in the codeword, and thus, as a non-limiting example, a correction circuit ( Figure 1 a correction circuit not depicted) may determine the reciprocal roots of the ELP 112 and apply error correction to the locations in the codeword indicated by the roots of the ELP 112.

[0044] The early exit logic circuit 122 receives the syndrome 114 and the estimated ELP 108, and sets the ELP completion signal 120 based at least in part on the syndrome 114 and the estimated ELP 108. The exit condition logic component 110 of the early exit logic circuit 122 controls the ELP determination at the ELP determination circuit 102 via the ELP completion signal 120. When asserted, the ELP completion signal 120 instructs the ELP determination circuit 102 to stop estimating the ELP determination (regardless of whether all 2*t iterations of the Berlekamp algorithm are completed), and when de-asserted, the ELP completion signal 120 instructs the ELP determination circuit 102 that the ELP determination can continue. The exit condition logic component 110 sets the ELP completion signal 120 (e.g., sets to asserted or de-asserted, but not limited thereto) at least in part in response to the value of the status signal 106. The status signal 106 indicates the status of the ELP determination at the ELP determination circuit 102. In one or more examples, a first value represents a stable state, and a different second value represents an unstable state. In one or more examples, the exit condition logic component 110 can indicate a conditional exit from the ELP determination via the ELP completion signal 120. The exit condition logic component 110 can assert the ELP completion signal 120 at least in part in response to a first value of the status signal 106 indicating that the ELP determination has reached a stable state, and can de-assert the ELP completion signal 120 at least in part in response to a second different value of the status signal 106 indicating that the ELP determination has not reached a stable state. In response to the exit condition logic component 110 asserting the ELP completion signal 120, the ELP determination circuit 102 stops the ELP determination and provides the estimated ELP as the ELP 112 of the syndrome 114.

[0045] The ELP determination status logic component 104 receives the estimated ELP 108 from the ELP determination circuit 102 and receives the syndrome 114. The estimated ELP 108 is the estimated ELP determined by the ELP determination circuit 102, and the estimated ELP is associated with a specific iteration of the estimated ELP determination performed at the ELP determination circuit 102.

[0046] The ELP determination status logic component 104 at least partially receives and determines the status of the ELP determination of the ELP determination circuit 102, and sets the status signal 106 at least partially based on the determined status of the ELP determination, as discussed below. Generally speaking, the ELP determination status logic component 104 determines whether the ELP determination performed by the ELP determination circuit 102 is in a stable state. In one or more examples, the ELP determination status logic component 104 may determine that the ELP determination is in a stable state in response to determining that no change will occur to the coefficients of the estimated ELP in a further (e.g., future, but not limited to) iteration of the ELP determination, as discussed below. The ELP determination status logic component 104 sets the status signal 106 to a value representing the determined status of the ELP determination, sets the status signal 106 to a first value indicating that the ELP determination is in a stable state, and sets the status signal 106 to a second different value indicating that the ELP determination is in an unstable state.

[0047] Figure 1 The ELP determination circuit 102 and the early exit logic circuit 122 are depicted in separate logic blocks, but this is not intended to limit the present disclosure in any way. In one or more examples, one or both of the ELP determination status logic component 104 and the exit condition logic component 110 may be or form part of the logic circuit of the ELP determination circuit 102, or may be or form part of a separate logic circuit having one or more connections (e.g., one or more pins, terminals, wires, data paths, but not limited to) between the ELP determination status logic component 104 and the ELP determination circuit 102 for transmitting the estimated ELP 108 and the status signal 106.

[0048] In a corresponding iteration, the Berlekamp algorithm of the ELP determination circuit 102 determines the estimated ELP 108 for the corresponding iteration, and provides the estimated ELP 108 to the early exit logic circuit 122, and more specifically, to the ELP determination status logic component 104. In one or more examples, the ELP determination status logic component 104 determines a difference value between the current iteration and a subsequent iteration of the ELP determination based on the syndrome 114 and the estimated ELP 108, determines whether all the determined difference values are zero, and determines the value of the status signal 106 based on whether all the difference values are zero.

[0049] Figure 2Depicts expression 200 for representational difference value analysis according to one or more examples. In one or more examples, the ELP determination state logic component 104 can determine a difference value according to expression 200 and utilize the determined difference value to determine the state determined by the ELP. Expression 200 includes: matrix 202, which includes (2*t - 2*v) rows, where the corresponding rows 210, 212......214 include syndromes (taken from syndrome 114); a matrix 204 of estimated ELP 108 coefficients σ1 to σ v of matrix 204; a matrix 206 of syndrome 114; and a matrix 224 of difference values. The result of multiplying matrix 202 by matrix 204 is a value matrix.

[0050] The result of multiplying matrix 202 by matrix 204 is added to the values in matrix 206 (represented by “+” in Figure 2 ), and if the values are the same, the result will be a zero value in matrix 224. If the values are different, the result will be a non-zero value in matrix 224. In this specific example, the addition operation refers to verifying whether two quantities are the same.

[0051] If the quantities are the same, the difference value in matrix 224 is 0, otherwise the difference value is non-zero. Figure 2 The expression 200 in depicts a non-limiting example where all determined difference values are zero. Here, “v” is an integer greater than or equal to 1 and also represents the current iteration evaluated by the ELP determination state logic component 104.

[0052] In one or more examples, the estimated ELP determined by the ELP determination circuit 102 at the even-numbered iterations determined by the corresponding ELP is provided to the early exit logic circuit 122, and the estimated ELP determined during the odd-numbered iterations determined by the corresponding ELP is not (e.g., never, but not limited to this) provided to the early exit logic circuit 122. This is because the number of iterations to determine the correct ELP is at least twice the number of errors present in the codeword, so the correct ELP will be determined on the even-numbered iterations of the Berlekamp algorithm. In one or more examples, the iterations evaluated by expression 200 are all even-numbered iterations from the current iteration v to the final iteration t by the ELP determination state logic component 104 using the estimated ELP 108 and the syndrome 114. If all difference values are zero for all such even-numbered iterations from v to t, the ELP determination state logic component 104 sets the status signal 106 to indicate the stable state determined by the ELP, and if there are any non-zero difference values, the ELP determination state logic component 104 sets the status signal 106 to indicate the non-stable state determined by the ELP.

[0053] As a non - limiting example, for a syndrome vector S of degree L and an estimated ELP C, the Berlekamp difference value at the n - th iteration of the Berlekamp algorithm can be expressed as follows:

[0054] For n = 0:13 (L = 1, using 14 multipliers), the difference value is given by Equation 1:

[0055] dn = C[0]*S[n + 1]+S[n + 2] (Equation 1)

[0056] For n = 0:11 (L = 2, using 24 multipliers), the difference value is given by Equation 2:

[0057] dn = C[1 ] *S[n + 2]+C[0]*S[n + 3]+S[n + 4] (Equation 2)

[0058] For n = 0:9 (L = 3, using 30 multipliers), the difference value is given by Equation 3:

[0059] dn = C[2]*S[n + 3]+C[1]*S[n + 4]+C[2]*S[n + 5]+S[n + 6] (Equation 3)

[0060] For n = 0:7 (L = 4, using 32 multipliers), the difference value is given by Equation 4:

[0061] dn = C[3]*S[n + 4]+C[2]*S[n + 5]+C[1*S[n + 6]+C[0]*S[n + 7]+S[n + 8]

[0062] (Equation 4)

[0063] For n = 0:5 (L = 5, using 30 multipliers), the difference value is given by Equation 5:

[0064] dn = C[4|*S[n + 5]+C[3]*S[n + 6]+C[3]*S[n + 7]+C[1]*S[n + 8]+C[0]*S[n + 9]+S[n + 10]

[0065] (Equation 5)

[0066] As a non - limiting example, if the current iteration is n = 2 and the estimated ELP is an ELP of order 1, the difference values dn for n = 0 to 13 are determined according to Equation 1. If all the difference values are zero, the error pattern represented by the syndrome vector S can be detected by the estimated ELP. This determination is performed using the estimated ELP 108 and the syndrome 114 of the current iteration and subsequent iterations. If all the difference values are zero, the ELP determination state logic component 104 determines that the ELP determination has a stable state and sets the status signal 106 to indicate this stable state. If any of the difference values is non - zero, the ELP determination state logic component 104 determines that the ELP determination has an unstable state and sets the status signal 106 to indicate this unstable state.

[0067] In one or more examples, the ELP determination state logic component 104 can determine the difference values for the respective iterations in parallel (e.g., during substantially the same duration, during the same iteration of the Berlekamp algorithm at the ELP determination circuit 102, during the same clock cycle, the same series of clock cycles, but not limited to this). In one or more examples, the respective determinations of the difference values for the rows 210, 212,......, 214 of the matrix 202 can occur in parallel. In one or more examples, the respective determinations can be performed in parallel. In one or more examples, a set of multipliers (and optionally, adders, inverters, but not limited to this) can be provided at the ELP determination state logic component 104, and this set of multipliers is used to perform the respective difference value determinations in parallel. As a non - limiting example, compared with sequential determination, parallel determination reduces the time used by the ELP determination state logic component 104 to determine the state of the ELP determination (thus reducing the latency). In one or more examples, the parallel determination of the difference values can occur during the odd - numbered iterations of the ELP determination at the ELP determination circuit 102 (e.g., substantially entirely during the odd - numbered iterations, but not limited to this), and these odd - numbered iterations immediately follow the even - numbered iterations that generate the estimated ELP 108 used by the ELP determination state logic component 104.

[0068] Figure 3 is a flowchart depicting a process 300 for determining an error - location polynomial (ELP) based at least in part on a status signal according to one or more examples.

[0069] Although example process 300 depicts a particular order of operations, the order can be changed without departing from the scope of the present disclosure. For example, some of the depicted operations can be performed in parallel or in a different order, which does not substantially affect the functionality of process 300. In other examples, different components of an example device or system implementing process 300 can perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 300 can be performed by one or more of device 100, ELP determination circuit 102, exit condition logic component 110, or ELP determination state logic component 104.

[0070] According to one or more examples, process 300 can include generating a status signal at operation 302 that is used to indicate the status of an error location polynomial (ELP) determination performed by the ELP determination circuit.

[0071] According to one or more examples, process 300 can include controlling the ELP determination performed by the ELP determination circuit at operation 304 at least in part in response to the value of the status signal.

[0072] Figure 4 is a flowchart depicting process 400 for determining the status of an ELP determination according to one or more examples.

[0073] Although example process 400 depicts a particular order of operations, the order can be changed without departing from the scope of the present disclosure. For example, some of the depicted operations can be performed in parallel or in a different order, which does not substantially affect the functionality of process 400. In other examples, different components of an example device or system implementing process 400 can perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 300 can be performed by one or more of device 100, ELP determination circuit 102, or ELP determination state logic component 104.

[0074] According to one or more examples, process 400 can include at operation 402 determining a Berlekamp discrepancy value (e.g., via Figure 1 expression 200 of Figure 1 but not limited to) based at least in part on a respective ELP (e.g., Figure 2 estimated ELP 108 of

[0075] According to one or more examples, process 400 may include determining the status of the ELP determination at operation 404 based at least in part on the determined Berlekamp difference values. As discussed above, if all the difference values are zero values, the status of the ELP determination may be determined to be a stable state, and if any of the difference values is a non-zero value, the status of the ELP determination may be determined to be a non-stable state.

[0076] Figure 5 is a flowchart depicting process 500 for setting a status signal indicative of the status of the ELP determination according to one or more examples.

[0077] Although example process 500 depicts a particular order of operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order, which does not substantially affect the functionality of process 500. In other examples, different components of an example device or system implementing process 500 may perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 300 may be performed by one or more of device 100, ELP determination circuit 102, exit condition logic component 110, or ELP determination status logic component 104.

[0078] According to one or more examples, process 500 may include determining that the status of the ELP determination is a stable state at operation 502 based at least in part on all determined Berlekamp difference values for the corresponding ELP and syndrome vector being zero.

[0079] According to one or more examples, process 500 may include setting the status signal to a first value at operation 504 to indicate the stable state.

[0080] According to one or more examples, process 500 may include determining that the status of the ELP determination is a non-stable state at operation 506 based at least in part on at least one determined Berlekamp difference value for the corresponding ELP and syndrome vector being non-zero.

[0081] According to one or more examples, process 500 may include setting the status signal to a second value at operation 508 to indicate the non-stable state, the second value being different from the first value.

[0082] Figure 6 is a flowchart depicting process 600 for controlling the ELP determination according to one or more examples.

[0083] Although example process 600 depicts a particular order of operations, the order can be changed without departing from the scope of the present disclosure. For example, some of the depicted operations can be performed in parallel or in a different order, which does not substantially affect the functionality of process 600. In other examples, different components of an example device or system implementing process 600 can perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 300 can be performed by one or more of device 100, ELP determination circuit 102, exit condition logic component 110, or ELP determination status logic component 104.

[0084] According to one or more examples, process 600 can include receiving, at operation 602, a status signal that is used to indicate the status of an error location polynomial (ELP) determination performed by an ELP determination circuit.

[0085] According to one or more examples, process 600 can include, at operation 604, stopping further determination of the ELP at least in part in response to the status signal being a first value.

[0086] According to one or more examples, the method includes outputting, at operation 606, the ELP.

[0087] According to one or more examples, process 600 can include, at operation 608, continuing the determination of the ELP at least in part in response to the status signal being a second value, the second value being different from the first value.

[0088] Figure 7 An example process 700 for controlling ELP determination in accordance with one or more examples is illustrated.

[0089] Although example process 700 depicts a particular order of operations, the order can be changed without departing from the scope of the present disclosure. For example, some of the depicted operations can be performed in parallel or in a different order, which does not substantially affect the functionality of process 700. In other examples, different components of an example device or system implementing process 700 can perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 300 can be performed by one or more of device 100, ELP determination circuit 102, exit condition logic component 110, or ELP determination status logic component 104.

[0090] According to one or more examples, process 700 can include generating, at operation 702, a status signal that is used to indicate the status of an error location polynomial (ELP) determination performed by an ELP determination circuit.

[0091] According to one or more examples, process 700 may include, at operation 704, controlling an ELP determination performed by an ELP determination circuit at least in part in response to a value of a status signal.

[0092] According to one or more examples, process 700 may include, at operation 706, updating the status signal at least in part based on an estimated ELP generated during an even-numbered iteration of the ELP determination performed by the ELP determination circuit.

[0093] According to one or more examples, process 700 may include, at operation 708, not updating the status signal based on an estimated ELP generated during an odd-numbered iteration of the ELP determination performed by the ELP determination circuit. In one or more examples, the estimated ELP determined during an odd-numbered iteration of the Berlekamp algorithm is not used to determine the status of the ELP determination. As a non-limiting example, the ELP determination circuit 102 does not provide the estimated ELP to Figure 1 the early exit logic circuit 122.

[0094] In one or more examples, updating the status signal on an even-numbered iteration means updating the status signal based on a version of the estimated ELP determined during an even-numbered iteration of the ELP determination. As a non-limiting example, the even-numbered iteration may correspond to an even-numbered iteration of a for-loop executed by the ELP determination circuit 102, or an even-numbered iteration of a clock cycle. Based on a version of the estimated ELP determined during an odd-numbered iteration of the ELP determination, no update of the status signal occurs (e.g., skipped or omitted, but not limited to this).

[0095] If a block has e errors (where "e" is an integer), the ELP generation process will exactly perform 2*e iterations of the Berlekamp algorithm to complete. At this time, the polynomial order (degree) will be e, and there will be e + 1 terms (coefficients). Therefore, the correct ELP appears on an even cycle of the Berlekamp algorithm because such process 700 updates the status signal and / or verifies an early exit condition on an even-numbered iteration of the Berlekamp algorithm. The status signal is updated or the early exit condition is checked using the estimated ELP generated during an even-numbered iteration of the ELP determination, and the status signal is not updated or the early exit condition is not checked using the estimated ELP generated during an odd-numbered iteration of the ELP determination. The estimated ELP generated during an event iteration of the ELP determination can be used to determine and update the status signal when the next odd-numbered iteration of the Berlekamp algorithm occurs.

[0096] Figure 8 Illustrates an example process 800 for error correction of a codeword according to one or more examples.

[0097] Although example process 800 depicts a particular order of operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order, which does not substantially affect the functionality of process 800. In other examples, different components of an example device or system implementing process 800 may perform functions substantially simultaneously or in a particular order. As a non-limiting example, some or all of the operations of process 800 may be performed by one or more of device 100, ELP determination circuit 102, exit condition logic component 110, ELP determination status logic component 104, or decoder 900.

[0098] According to one or more examples, process 800 may include generating a status signal at operation 802 that is used to indicate the status of an error locator polynomial (ELP) determination performed by the ELP determination circuit.

[0099] According to one or more examples, process 800 may include controlling the ELP determination performed by the ELP determination circuit at operation 804 at least in part in response to the value of the status signal.

[0100] According to one or more examples, process 800 may include error correcting a codeword at operation 806 using the ELP generated by the ELP determination circuit via the ELP determination.

[0101] Figure 9 An example process 90 is illustrated according to one or more examples.

[0102] Although example process 900 depicts a particular order of operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order, which does not substantially affect the functionality of process 900. In other examples, different components of an example device or system implementing process 900 may perform functions substantially simultaneously or in a particular order.

[0103] According to one or more examples, process 900 may include generating a status signal at operation 902 that is used to indicate the status of an error locator polynomial (ELP) determination performed by the ELP determination circuit.

[0104] According to one or more examples, process 900 may include controlling the ELP determination performed by the ELP determination circuit at operation 904 at least in part in response to the value of the status signal. Controlling the ELP determination may include exiting early or continuing the ELP determination, as discussed above.

[0105] According to one or more examples, process 900 may include setting a status signal to indicate an unstable state at operation 906, at least in part based on determining that the order of the corresponding ELP is not at least twice the current iteration order of the ELP determination circuit. Generally, the order of the correct ELP should be at least twice the iteration order, and if not, in one or more examples, the ELP determination status logic component may determine that the status of the current ELP determination is an unstable state and set the value of the status signal accordingly.

[0106] Figure 10 is a functional block diagram depicting a system 1000 for Reed-Solomon decoding that provides for early exit from ELP determination according to one or more examples. System 1000 may also be referred to herein as Reed-Solomon decoder 1000 or RS decoder 1000. Figure 10 The system depicted in may be used for Chien-Horowitz decoding or other decoding based on polynomial arithmetic, the modifications of which will be apparent to those of ordinary skill in the art.

[0107] Receive an FEC block 1002 having errors (e.g., bit errors, symbol errors, burst errors, but not limited thereto) at a first-in, first-out (FIFO) memory 1014 (“block FIFO memory 1014”). At the same time, compute a syndrome 1004 at least in part based on the FEC block 1002. The FIFO memory accumulates future FEC blocks because the processing times of the corresponding FEC blocks may vary, where those with fewer errors take fewer clock cycles while those with many errors will take more clock cycles. While a slow FEC block (i.e., an FEC block with a higher number of errors) is being processed, the FIFO memory may still receive other FEC blocks. Due to the early exit, the output rate of the decoder is higher than the total input rate. This allows the decoder 1000 to empty the FIFO memory even when new blocks arrive at the input. Note that the assumption here is that almost all input blocks have 0 or possibly 1 symbol error, and those blocks with a high error count are also rare in an electronic communication or storage system.

[0108] Determine an ELP 1006 at least in part based on the syndrome 1004 and the BK early exit signal 1010. As a non-limiting example, the BK early exit signal 1010 may be the status signal 106 discussed above, or a signal generated by the exit condition logic component 110 to stop the ELP determination.

[0109] Generate a Chein root 1008 at least in part based on the ELP 1006. The Chein root 1008 is a root of the ELP 1006 determined using the Chein search algorithm.

[0110] The Forney amplitude signal 1012 is generated at least in part based on the Chein root 1008. The Forney amplitude signal 1012 can be determined based on the Forney algorithm. The value of the Forney amplitude signal 1012 represents the amplitude of the error at the position indicated by the Chein root 1008. In one or more examples, the Forney amplitude signal 1012 can be determined at least in part based on the Chein root 1008, the syndrome 1004, and the error amplitude polynomial. At block 1016, a correction represented by one or more of the Forney signal 1012, the Chein root 1008, the ELP 1006, or the syndrome 1004 is applied to produce an output block including the corrected FEC block 1018.

[0111] One of ordinary skill in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or combinations thereof. Figure 11 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all of the functional elements disclosed herein can be performed by hardware specifically configured to perform that functional element.

[0112] Figure 11 FIG. is a block diagram of a circuit 1100 that can be used in some examples to implement the various functions, operations, actions, processes, or methods disclosed herein. The circuit 1100 includes one or more processors 1102 (sometimes referred to herein as "processor 1102") operatively coupled to one or more data storage devices 1104 (sometimes referred to herein as "storage 1104"). The storage 1104 includes machine-executable code 1106 stored thereon, and the processor 1102 includes logic circuitry 1108. The machine-executable code 1106 describes functional elements that can be implemented (e.g., executed) by the logic circuitry 1108. The logic circuitry 1108 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1106. When the functional elements described by the machine-executable code 1106 are executed, the circuit 1100 should be regarded as dedicated hardware configured to implement the functional elements disclosed herein. In some examples, the processor 1102 can be configured to execute the functional elements described by the machine-executable code 1106 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0113] When implemented by the logic circuitry 1108 of the processor 1102, the machine-executable code 1106 is configured to render the processor 1102 suitable for performing the operations of the examples disclosed herein. As a non-limiting example, the machine-executable code 1106 may be configured to render the processor 1102 suitable for performing some or all of the operations of the apparatus 100, expression 200, process 300, process 400, process 500, process 600, process 700, process 800, RS decoder 1000, or process 900.

[0114] The processor 1102 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including one or more processors 1102 is considered a special-purpose computer at least when the general-purpose computer executes functional elements corresponding to the machine-executable code 1106 (e.g., software code, firmware code, configuration data, hardware description, but not limited thereto) related to the examples of the present disclosure. Note that the general-purpose processor (which may also be referred to herein as the host processor or simply "host") may be a microprocessor, but in an alternative, the general-purpose processor of the processor 1102 may include any conventional processor, controller, microcontroller, or state machine. The FPGA or other PLD of the processor 1102 may be configured (e.g., programmed, but not limited thereto) with configuration data to perform the functions disclosed herein, or additionally or alternatively, may be capable of being configured or reconfigured (e.g., programmable or reprogrammable, but not limited thereto) with configuration data to perform the functions disclosed herein. The processor 1102 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0115] In some examples, the storage device 1104 includes volatile data storage devices (e.g., random access memory (RAM)), non-volatile data storage devices (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, the processor 1102 and the storage device 1104 may be implemented as a single device (e.g., semiconductor device product, system-on-chip (SOC), but not limited thereto). In some examples, the processor 1102 and the storage device 1104 may be implemented as separate devices.

[0116] In some examples, the machine-executable code 1106 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by the storage device 1104, accessed directly by the processor 1102, and executed by the processor 1102 using at least the logic circuitry 1108. Also as a non-limiting example, the computer-readable instructions may be stored on the storage device 1104, transferred to a memory device (not shown) for execution, and executed by the processor 1102 using at least the logic circuitry 1108. Thus, in some examples, the logic circuitry 1108 includes electrically configurable logic circuitry 1108.

[0117] In some examples, the machine-executable code 1106 may describe hardware (e.g., circuitry) to be implemented in the logic circuitry 1108 to perform functional elements. The hardware may be described at any of a variety of levels of abstraction from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) may be used, such as the IEEE standard hardware description language (HDL). As a non-limiting example, Verilog, SystemVerilog TM or very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0118] The HDL description may be converted to a description at any of a number of other levels of abstraction as needed. As a non-limiting example, a high-level description may be converted to a logic-level description such as register transfer language (RTL), gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, the micro-operations to be performed by the hardware logic circuitry (e.g., gates, flip-flops, registers, but not limited to) of the logic circuitry 1108 may be described in RTL and then converted to a GL description by a synthesis tool, and the GL description may be converted to a layout-level description by placement and routing tools, which corresponds to the physical layout of an integrated circuit, discrete gates or transistor logic, discrete hardware components, or a combination thereof of a programmable logic device. Thus, in some examples, the machine-executable code 1106 may include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0119] In an example where the machine-executable code 1106 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1104) may be configured to implement the hardware description described by the machine-executable code 1106. By way of non-limiting example, the processor 1102 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1108 may be electrically controlled to implement the circuitry corresponding to the hardware description into the logic circuit 1108. Similarly, as a non-limiting example, the logic circuit 1108 may include hardwired logic fabricated by a manufacturing system (not shown, but including the storage device 1104) according to the hardware description of the machine-executable code 1106.

[0120] Regardless of whether the machine-executable code 1106 includes computer-readable instructions or a hardware description, the logic circuit 1108 is adapted to execute the functional elements described by the machine-executable code 1106 when implementing the functional elements of the machine-executable code 1106. Note that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of executing.

[0121] As used in this disclosure, the term "module" or "component" may refer to a particular hardware implementation configured to perform the actions of a module or component and / or a software object or software routine that may be stored on and / or executed by the general hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) executing on a computing system. Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0122] As used in this disclosure, the term "combination" with respect to multiple elements may include any combination of all the elements or various different sub-combinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0123] The terms used in this disclosure and particularly in the appended claims (e.g., the subject matter of the appended claims, but not limited thereto) are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “comprising but not limited to”, the term “having” should be interpreted as “having at least”, but not limited thereto). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0124] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and absent such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article “a” or “an” will limit any particular claim containing such introduced claim recitation to only examples containing one such recitation, even when the same claim includes an introductory phrase “one or more” or “at least one” and the indefinite article, such as “a” or “an” (e.g., “a” and / or “an” may be interpreted to mean “at least one” or “one or more”, but not limited thereto); the same holds true for the use of the definite article to introduce a claim recitation.

[0125] Furthermore, even if a specific number of introduced claim recitations is expressly recited, those skilled in the art will recognize that such recitation should be interpreted as being intended to be at least the recited number (e.g., an unmodified recitation of “two recitations” in the absence of other modifying components is intended to be at least two recitations, or two or more recitations, but not limited thereto). Additionally, in those instances where a convention similar to “at least one of A, B, and C, but not limited thereto” or “one or more of A, B, and C, but not limited thereto” is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0126] Moreover, regardless of whether in the specification, claims, or drawings, any distinct word or phrase presenting two or more alternative terms should be understood to contemplate the possibility of including one of the terms, any one of the terms, or both terms. For example, the phrase “A or B” should be understood to include the possibility of “A” or “B” or “A and B”.

[0127] Additional non - limiting examples include:

[0128] Embodiment 1: A device, the device comprising: an error location polynomial (ELP) determination circuit; and a logic circuit for setting a status signal for indicating the status of ELP determination performed by the ELP determination circuit, wherein the ELP determination circuit is configured to: at least partially in response to a first value of the status signal, stop ELP determination; and at least partially in response to a second value of the status signal, continue ELP determination, wherein the second value is different from the first value.

[0129] Embodiment 2: The device according to Embodiment 1, wherein the logic circuit is configured to: at least partially determine the status of ELP determination based on the corresponding ELP generated by the ELP determination circuit and the syndrome vector; and at least partially set the status signal based on the determined status of ELP determination.

[0130] Embodiment 3: The device according to any one of Embodiments 1 and 2, wherein the logic circuit is configured to: determine the Berlekamp difference value using the ELP generated by the ELP determination circuit and the syndrome vector; and at least partially determine the status of ELP determination based on the determined Berlekamp difference value.

[0131] Embodiment 4: The device according to any one of Embodiments 1 to 3, wherein the logic circuit is configured to: at least partially determine that the status of ELP determination is a stable state based on all determined Berlekamp difference values being zero for the corresponding ELP and the syndrome vector; and at least partially determine that the status of ELP determination is an unstable state based on at least one determined Berlekamp difference value being non-zero for the corresponding ELP and the syndrome vector.

[0132] Embodiment 5: The device according to any one of Embodiments 1 to 4, wherein the logic circuit is configured to: set the status signal to the first value to indicate the stable state; and set the status signal to the second value to indicate the unstable state.

[0133] Embodiment 6: The device according to any one of Embodiments 1 to 5, wherein the ELP determination circuit is configured to: at least partially in response to the status signal being the first value: stop further determination of the ELP; and provide the ELP, and at least partially in response to the status signal being the second value: continue determination of the ELP.

[0134] Embodiment 7: The device according to any one of Embodiments 1 to 6, wherein the logic circuit includes two or more sub-logic circuits to respectively determine the Berlekamp difference value using the ELP generated by the ELP determination circuit and the corresponding syndrome.

[0135] Example 8: The apparatus according to any one of Examples 1 to 7, wherein the two or more sub-logic circuits are configured to determine corresponding Berlekamp difference values within the same clock cycle.

[0136] Example 9: The apparatus according to any one of Examples 1 to 8, wherein the logic circuit is configured to: update the state signal on even-numbered iterations of the ELP determination performed by the ELP determination circuit.

[0137] Example 10: The apparatus according to any one of Examples 1 to 9, wherein the logic circuit is configured to: not update the state signal on odd-numbered iterations of the ELP determination performed by the ELP determination circuit.

[0138] Example 11: The apparatus according to any one of Examples 1 to 10, wherein the logic circuit is configured to: set the state signal to indicate an unstable state based at least in part on determining that the order of the corresponding ELP is not at least twice the current iteration order of the ELP determination performed by the ELP determination circuit.

[0139] Example 12: A method, the method comprising: generating a state signal for indicating a state of an ELP determination performed by an error-locator polynomial (ELP) determination circuit; and controlling the ELP determination performed by the ELP determination circuit at least in part in response to a value of the state signal.

[0140] Example 13: The method according to Example 12, the method comprising: determining the state of the ELP determination based at least in part on a corresponding ELP generated by the ELP determination circuit and a syndrome vector; and setting the state signal based at least in part on the determined state of the ELP determination.

[0141] Example 14: The method according to any one of Examples 12 and 13, the method comprising: determining a Berlekamp difference value based at least in part on a corresponding ELP generated by the ELP determination circuit and a syndrome vector; and determining the state of the ELP determination based at least in part on the determined Berlekamp difference value.

[0142] Example 15: The method according to any one of Examples 12 to 14, the method comprising: determining that the state of the ELP determination is a stable state based at least in part on all determined Berlekamp difference values being zero for the corresponding ELP and the syndrome vector; and determining that the state of the ELP determination is an unstable state based at least in part on at least one determined Berlekamp difference value being non-zero for the corresponding ELP and the syndrome vector.

[0143] Example 16: The method according to any one of Examples 12 to 15, the method comprising: setting the status signal to a first value to indicate the stable state; and setting the status signal to a second value to indicate the non-stable state, wherein the second value is different from the first value.

[0144] Example 17: The method according to any one of Examples 12 to 16, the method comprising: at least partially in response to the status signal being the first value: stopping further determination of the ELP; and outputting the ELP, and at least partially in response to the status signal being the second value: continuing the determination of the ELP, wherein the second value is different from the first value.

[0145] Example 18: The method according to any one of Examples 12 to 17, the method comprising: during the same clock cycle, determining two or more Berlekamp difference values using the ELP generated by the ELP determination circuit and the corresponding syndromes.

[0146] Example 19: The method according to any one of Examples 12 to 18, the method comprising: updating the status signal on even-numbered iterations of the ELP determination performed by the ELP determination circuit.

[0147] Example 20: The method according to any one of Examples 12 to 19, the method comprising: performing error correction on the codeword using the ELP generated by the ELP determination circuit via the ELP determination.

[0148] Example 21: The method according to any one of Examples 12 to 20, the method comprising: at least partially based on determining that the order of the corresponding ELP is not at least twice the current iteration order of the ELP determination performed by the ELP determination circuit, setting the status signal to indicate the non-stable state.

[0149] Example 22: A decoder for Reed-Solomon decoding or Bose-Chaudhuri-Hocquenghem decoding, the decoder comprising an error locator polynomial (ELP) determination circuit for exiting the ELP determination at least partially in response to an indication that the corresponding ELP has reached a stable state.

[0150] Although the present disclosure describes the invention with respect to certain exemplary embodiments, those of ordinary skill in the art will recognize and understand that the invention is not so limited. On the contrary, many additions, deletions, and modifications may be made to the exemplary embodiments and the examples without departing from the scope of the invention as claimed hereinafter and its legal equivalents. In addition, features from one example may be combined with features of another example while still being within the scope of the invention contemplated by the inventors.

Claims

1. A device, the device comprising: An error location polynomial (ELP) determination circuit; And A logic circuit for setting a status signal for indicating a status of ELP determination performed by the ELP determination circuit, Wherein the ELP determination circuit is configured to: Stop ELP determination at least in part in response to a first value of the status signal; and Continue ELP determination at least in part in response to a second value of the status signal, where the second value is different from the first value.

2. The device according to claim 1, wherein the logic circuit is configured to: Determine the status of ELP determination at least in part based on a corresponding ELP generated by the ELP determination circuit and a syndrome vector; and Set the status signal at least in part based on the determined status of ELP determination.

3. The device according to claim 1, wherein the logic circuit is configured to: Determine a Berlekamp discrepancy value using the ELP generated by the ELP determination circuit and the syndrome vector; and Determine the status of ELP determination at least in part based on the determined Berlekamp discrepancy value.

4. The device according to claim 3, wherein the logic circuit is configured to: Determine that the status of ELP determination is a stable state at least in part based on all determined Berlekamp discrepancy values being zero for a corresponding ELP and the syndrome vector; and Determine that the status of ELP determination is an unstable state at least in part based on at least one determined Berlekamp discrepancy value being non - zero for the corresponding ELP and the syndrome vector.

5. The device according to claim 4, wherein the logic circuit is configured to: Set the status signal to the first value to indicate the stable state; and Set the status signal to the second value to indicate the unstable state.

6. The device according to claim 1, wherein the ELP determination circuit is configured to: At least in part in response to the status signal being the first value: Stop further determination of the ELP; and Provide the ELP, and At least in part in response to the status signal being the second value: Continue determination of the ELP.

7. The device according to claim 1, wherein the logic circuit includes two or more sub - logic circuits to respectively determine Berlekamp discrepancy values using the ELP generated by the ELP determination circuit and corresponding syndromes.

8. The device according to claim 7, wherein the two or more sub - logic circuits are configured to determine corresponding Berlekamp discrepancy values within the same clock cycle.

9. The device according to claim 1, wherein the logic circuit is configured to: Update the status signal on even - numbered iterations of ELP determination performed by the ELP determination circuit.

10. The device according to claim 1, wherein the logic circuit is configured to: Not update the status signal on odd - numbered iterations of ELP determination performed by the ELP determination circuit.

11. The apparatus according to claim 1, wherein the logic circuit is configured to: set the status signal to indicate an unstable state based at least in part on determining that an order of a corresponding ELP is not at least twice a current iteration order of the ELP determination performed by the ELP determination circuit.

12. A method, the method comprising: generating a status signal for indicating a status of an ELP determination performed by an error locator polynomial (ELP) determination circuit; and controlling the ELP determination performed by the ELP determination circuit at least in part in response to a value of the status signal.

13. The method according to claim 12, the method comprising: determining the status of the ELP determination based at least in part on a corresponding ELP generated by the ELP determination circuit and a syndrome vector; and setting the status signal based at least in part on the determined status of the ELP determination.

14. The method according to claim 12, the method comprising: determining a Berlekamp discrepancy value based at least in part on a corresponding ELP generated by the ELP determination circuit and a syndrome vector; and determining the status of the ELP determination based at least in part on the determined Berlekamp discrepancy value.

15. The method according to claim 14, the method comprising: determining that the status of the ELP determination is a stable state based at least in part on all determined Berlekamp discrepancy values being zero for a corresponding ELP and the syndrome vector; and determining that the status of the ELP determination is an unstable state based at least in part on at least one determined Berlekamp discrepancy value being non - zero for the corresponding ELP and the syndrome vector.

16. The method according to claim 15, the method comprising: setting the status signal to a first value to indicate the stable state; and setting the status signal to a second value to indicate the unstable state, wherein the second value is different from the first value.

17. The method according to claim 12, the method comprising: at least in part in response to the status signal being a first value: stopping further determination of the ELP; and outputting the ELP, and at least in part in response to the status signal being a second value: continuing the determination of the ELP, wherein the second value is different from the first value.

18. The method according to claim 12, the method comprising: determining two or more Berlekamp discrepancy values during the same clock cycle using an ELP generated by the ELP determination circuit and a corresponding syndrome.

19. The method according to claim 12, the method comprising: updating the status signal on even - numbered iterations of the ELP determination performed by the ELP determination circuit.

20. The method according to claim 12, the method comprising: performing error correction on a codeword using an ELP generated by the ELP determination circuit via the ELP determination.

21. The method according to claim 12, the method comprising: Set the state signal to indicate an unstable state based at least in part on determining that the order of the corresponding ELP is not at least twice the current iteration order of the ELP determination performed by the ELP determination circuit.

22. A decoder for Reed-Solomon decoding or Bose-Chaudhuri-Hocquenghem decoding, the decoder including an error locator polynomial (ELP) determination circuit configured to exit ELP determination at least in response to an indication that the corresponding ELP has reached a stable state.

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