Data processing system and method, electronic equipment and storage medium

Abstract

The invention discloses a data processing system and method, electronic equipment and a storage medium, and relates to the technical field of computers.Original input data are preprocessed into multiple sets of target input data through a data input module, and the multiple sets of target input data are input into multiple iterative calculation units to obtain data to be calculated and code identifiers; when the code identifier represents that the to-be-calculated data needs to be overturned in advance, the to-be-calculated data is overturned in advance to obtain the to-be-calculated inverted data, and a subsequent iterative calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result; that is, the iterative calculation unit can obtain the data processing result only by performing a small amount of data bit flipping on the to-be-calculated inverted data through the target calculation, the number of data bit flipping in the target calculation is reduced, the dynamic flipping power consumption is reduced, and compared with a power consumption reduction mode in the related technology, the efficiency is improved. High-difficulty chip rear end layout wiring is not needed, and the performance and the power consumption reduction effect of the chip can be ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a data processing system, method, electronic device, and storage medium. Background Art

[0002] In today's digital development, the application of algorithms is becoming increasingly widespread, and the requirements for power consumption are becoming increasingly stringent. The importance of low-power data processing is becoming more prominent. The third-generation Secure Hash Algorithm (SHA-3 algorithm) is the latest generation of secure hash algorithm. Since the algorithm generates high dynamic switching power consumption during data processing, how to reduce the dynamic switching power consumption of data processing has become the focus of research.

[0003] In related technologies, a dynamic voltage regulation scheme is usually adopted to adjust the supply voltage by rounds. However, implementing dynamic voltage regulation on the operation chip of the algorithm requires designing multiple power supply lines, which increases the difficulty of the chip backend layout and wiring. At the same time, it increases the parasitic effects caused by voltage switching, which is not conducive to ensuring the performance of the chip and the power consumption reduction effect. Summary of the Invention

[0004] This application provides a data processing system, method, electronic device, and storage medium to at least solve the problem that the method of reducing the algorithm power consumption in related technologies increases the difficulty of the chip backend layout and wiring, which is not conducive to ensuring the performance of the chip and the power consumption reduction effect.

[0005] This application provides a data processing system, including: a data input module and an iterative calculation module. The iterative calculation module includes multiple iterative calculation units; The data input module is used to obtain the original input data to be processed, perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into the multiple iterative calculation units respectively; The iterative calculation unit is used to, when receiving any group of target input data and the output result of the previous iterative calculation unit, determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit; in the case where the coding identifier indicates that the data to be calculated meets the preset pre-flip condition, perform pre-flip on the data to be calculated to convert the data to be calculated into the data to be calculated in the inverted phase; perform target calculation on the data to be calculated in the inverted phase, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit; Wherein, the target calculation includes performing data bit flipping on the data to be calculated in the inverted phase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0006] The present application also provides a data processing method, which is applied to any of the above data processing systems, and the method includes: Obtain the original input data to be processed; Perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into multiple iterative calculation units respectively; Based on the iterative calculation unit, determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit; When the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, perform pre-flipping on the data to be calculated to convert the data to be calculated into the data to be calculated in the inverted phase; Perform target calculation on the data to be calculated in the inverted phase, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit; Wherein, the target calculation includes performing data bit flipping on the data to be calculated in the inverted phase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0007] The present application also provides a data processing device, including: An acquisition module, configured to acquire the original input data to be processed; A data preprocessing module, configured to perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into multiple iterative calculation units respectively; A determination module, configured to determine the data to be calculated and the coding identifier based on the iterative calculation unit according to the target input data and the output result of the previous iterative calculation unit; A flipping module, configured to perform pre-flipping on the data to be calculated when the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, so as to convert the data to be calculated into the data to be calculated in the inverted phase; A calculation module, configured to perform target calculation on the data to be calculated in the inverted phase, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit; wherein, the target calculation includes performing data bit flipping on the data to be calculated in the inverted phase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0008] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above data processing methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of any of the above data processing methods are implemented.

[0010] The present application also provides a computer program product including a computer program, wherein when the computer program is executed by a processor, the steps of any of the above data processing methods are implemented.

[0011] Through the present application, since the original input data is preprocessed into multiple groups of target input data by a data input module and respectively input into multiple iterative calculation units to obtain data to be calculated and a coding identifier, when the coding identifier indicates that the data to be calculated needs to be pre-flipped, the data to be calculated is pre-flipped to obtain the data to be calculated and inverted. Subsequently, the iterative calculation unit only needs to perform a target calculation on the data to be calculated and inverted to obtain the data processing result, that is, the iterative calculation unit only needs to perform a small number of data bit flips on the data to be calculated and inverted through the target calculation to obtain the data processing result, reducing the number of data bit flips occurring in the target calculation and reducing the dynamic flip power consumption. Compared with the power consumption reduction methods in the related art, the present application does not require a high-difficulty chip back-end layout and wiring, and can ensure the performance and power consumption reduction effect of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a schematic diagram of the interaction process of the data processing system provided by the embodiment of the present application; Figure 2 It is a schematic diagram of the structure of the data processing system provided by the embodiment of the present application; Figure 3 It is a schematic diagram of the structure of the iterative calculation unit provided by the embodiment of the present application; Figure 4 It is a schematic diagram of the structure of the coding identifier determination unit provided by the embodiment of the present application; Figure 5 It is a schematic diagram of the structure of an exemplary register module provided by the embodiment of the present application; Figure 6 It is a schematic diagram of the structure of an exemplary data processing system provided by the embodiment of the present application; Figure 7 It is a schematic diagram of the flow of the data processing method provided by the embodiment of the present application; Figure 8Schematic diagram of the data processing device provided by the embodiment of the present application; Figure 9 Schematic diagram of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0015] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] With the increasingly rapid development of digitalization, in order to improve the performance of chips, higher challenges are posed to their power consumption management. The third-generation Secure Hash Algorithm (SHA-3 algorithm) is widely used in security scenarios such as data encryption and digital signatures. However, the sponge structure and high-frequency iterative operation mechanism of the SHA-3 algorithm cause a large amount of dynamic switching power consumption during data processing, reducing the performance of the chip.

[0017] In the related art, generally, the dynamic voltage regulation method is adopted to adjust the supply voltage by rounds. However, implementing dynamic voltage regulation on the running chip requires designing multiple power supply lines, which increases the difficulty of the back-end layout and wiring of the chip and also increases the parasitic effects caused by voltage switching. It is also possible to adopt a clock gating SHA3 architecture, but this method will increase the delay of the critical path and thus reduce the operation performance.

[0018] The present application discloses a data processing system, method, electronic device, and storage medium, which relate to the field of computer technology. Since the original input data can be preprocessed through a data input module to obtain multiple groups of target input data, and the multiple groups of target input data are respectively input into multiple iterative calculation units to obtain data to be calculated and a coding identifier. When it is determined according to the coding identifier that the data to be calculated needs to be pre-flipped, the data to be calculated is pre-flipped to obtain the data to be calculated and inverted. Subsequently, the iterative calculation unit only needs to perform a target calculation on the data to be calculated and inverted to obtain the data processing result, that is, the iterative calculation unit only needs to perform a small number of data bit flips on the data to be calculated and inverted through the target calculation to obtain the data processing result, reducing the number of data bit flips occurring in the target calculation and reducing the dynamic flip power consumption. Compared with the power consumption reduction methods in the related art, the present application does not require high-difficulty chip backend layout and wiring, and can ensure the performance and power consumption reduction effect of the chip.

[0019] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] An embodiment of the present application provides a data processing system for transmitting the original input data of a data input module to an iterative calculation module for calculation.

[0021] As Figure 1 shown, it is an interaction process schematic diagram of the data processing system provided by the embodiment of the present application. The system includes: a data input module and an iterative calculation module, and the iterative calculation module includes multiple iterative calculation units.

[0022] Among them, the data input module is used to obtain the original input data to be processed. Among them, in the SHA-3 algorithm, the original data to be input can be any data of any size that needs to be encrypted. The original input data is preprocessed to convert the original input data into multiple groups of target input data, and the multiple groups of target input data are respectively input into multiple iterative calculation units; the iterative calculation unit is used to determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit when receiving any group of target input data and the output result of the previous iterative calculation unit; when the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, the data to be calculated is pre-flipped to convert the data to be calculated into the data to be calculated and inverted; a target calculation is performed on the data to be calculated and inverted, and the obtained target calculation result is used as the output result and input into the next iterative calculation unit; among them, the target calculation includes performing a data bit flip on the data to be calculated and inverted, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0023] It should be noted that when the data processing system provided in the embodiments of the present application is applied to the scenario of data encryption processing, the power consumption reduction effect is extremely obvious. Taking the data processing algorithm implemented by the data processing system provided in the embodiments of the present application as the SHA-3 algorithm as an example, the original input data to be processed is the data to be encrypted, such as user privacy data, data to be compressed, or verification data, etc. This algorithm consists of four cryptographic hash functions: SHA3-224, SHA3-256, SHA3-384, SHA3-512 and two expandable output functions SHAKE-128 and SHAKE-256. Among them, the absorption rate, capacity, hash output length of the SHA-3 algorithm, and the mapping relationship with the Keccak-f function of the algorithm are shown in Table 1 below: Table 1

[0024] Table 1 shows the operation parameters of 6 sub-algorithms of the SHA-3 algorithm. The bit rate or absorption rate (Rate, abbreviated as: r) represents the length of the smallest data unit for operation. It can be seen from the table that there are 5 bit rates r for the 6 sub-algorithms. That is, before performing the algorithm operation, the data sent from the previous stage must be grouped according to the length of r. SHA3-224, SHA3-256, SHA3-384, and SHA3-512 belong to fixed-length hash algorithms, and output hash values of fixed byte lengths, while SHAKE128 and SHAKE256 belong to variable-length hash algorithms, and the output length is determined by parameters. The hash output length, that is, the digest length, represents the byte length of the hash value finally generated by the algorithm. The capacity (Capacity, abbreviated as: c) reflects the size of the internal state of the algorithm. The larger the value, the stronger the security and collision resistance of the algorithm. The mapping relationship of the Keccak-f function of the algorithm reveals the core operation logic of the algorithm, where Keccak[n] represents using the Keccak-f function with a capacity of n bits, "M" represents the original input message, and "||" represents string concatenation.

[0025] Among them, the data input module is used to obtain the original input data to be processed. In the SHA-3 algorithm, the original input data to be input can be any data of any size that needs to be encrypted. Data preprocessing is performed on the original input data. The data preprocessing includes message padding according to the corresponding rules of the algorithm, converting the original input data into multiple groups of target input data, and respectively inputting the multiple groups of target input data into multiple iterative calculation units included in the iterative calculation module. The iterative calculation unit is used to determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit when receiving any group of target input data and the output result of the previous iterative calculation unit. The data will be flipped in the iterative calculation unit, that is, 0 is flipped to 1 and 1 is flipped to 0. Due to the complex logic composition of the iterative calculation unit, a large number of bit flips will occur during the target calculation, resulting in a large amount of power consumption. Therefore, pre-flipping can be performed through a simple hardware circuit with low power consumption, which can reduce the bit flips (data bit flips) generated by the target calculation, thereby reducing the dynamic power consumption. Therefore, it is judged whether the preset flipping condition is met through the coding identifier. When the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, pre-flipping is performed on the data to be calculated to convert the data to be calculated into the data to be calculated and inverted. The iterative calculation unit performs target calculation on the data to be calculated and inverted, and inputs the obtained target calculation result as the output result to the next iterative calculation unit.

[0026] Based on the above embodiments, as Figure 2 shown, it is a schematic structural diagram of the data processing system provided by the embodiment of the present application. As an implementable manner, in one embodiment, the data input module includes: An acquisition unit, configured to acquire the original input data to be processed, and judge the size relationship between the input bit width of the original input data and the minimum data unit length of the target calculation unit; when the input bit width of the original input data is less than the minimum data unit length of the target calculation unit, perform data aggregation processing on the original input data to obtain the input data to be filled with a length equal to the minimum data unit length; A filling unit, configured to perform effective message filling on the input data to be filled to obtain grouped data with a length equal to an integer multiple of the minimum data unit length; A grouping unit, configured to perform data grouping on the grouped data to obtain multiple groups of target input data; Among them, the iterative calculation unit includes a target calculation unit.

[0027] Specifically, the input bit width in the acquisition unit generally takes a value of 32 bit or 64 bit according to the data bit width of the bus interface. The minimum data unit length of the target computing unit refers to the bit width of the minimum data unit of the input data required in a single calculation process when the target computing unit performs iterative operations. The specific value is determined according to the type of algorithm. For example, when the target computing unit adopts SHA3-224(M) in Table 1, the minimum data unit length of the target computing unit is the absorption rate r (1152) of SHA3-224(M). When the input bit width of the original input data is less than the minimum data unit length of the target computing unit, the original input data is concatenated into a large block of data that meets the minimum data unit length of the target computing unit through data aggregation, and this data is the input data to be filled.

[0028] Specifically, the valid message padding in the padding unit refers to adding a binary bit sequence at the end or a specific position of the data according to the specific rules corresponding to the type of algorithm, so that the data length reaches an integer multiple of the minimum data unit length, and the data to be grouped is obtained. The valid message padding rule corresponding to the SHA-3 algorithm is to add binary bits at the end of the data, specifically including: first adding 1 one-bit, then padding several 0 bits, and finally adding the binary bits used to identify the length of the original data, so that the total length of the padded data is exactly an integer multiple of the minimum data unit length, that is, an integer multiple of the rate parameter r.

[0029] Specifically, the grouping unit equally divides the data to be grouped according to the minimum data unit length of the target computing unit to generate multiple groups of target input data that can be directly input into the iterative calculation module. In the SHA-3 algorithm, the grouping unit divides the padded data to be grouped into multiple groups according to the value of the minimum data unit length of the target computing unit, and each group is independently input into the iterative calculation module.

[0030] Correspondingly, the acquisition unit can judge the relationship between the input bit width of the original input data and the minimum data unit length of the target computing unit, and then perform data aggregation processing on the original input data according to the judgment result to achieve data concatenation. The padding unit can perform valid message padding on the input data to be filled according to the specific padding rules corresponding to different algorithm types, improving the accuracy of valid data padding. The grouping unit can accurately equally divide the padded data according to the minimum data unit length to generate standard target input data, providing ideal input data for the iterative calculation module to ensure that the subsequent iterative calculation unit can operate normally, laying a foundation for improving the calculation efficiency.

[0031] Correspondingly, in an embodiment, the acquisition unit is further configured to directly use the original input data as the input data to be filled when the input bit width of the original input data is equal to the minimum data unit length of the target computing unit.

[0032] Accordingly, when the input bit width of the original input data is equal to the length of the minimum data unit of the target computing unit, data aggregation processing can be ignored, reducing the resource waste caused by unnecessary operations when the original input data meets the requirements.

[0033] Accordingly, in one embodiment, the padding unit is specifically configured to obtain the algorithm type of the target computing unit; determine the valid message padding rule according to the algorithm type; and perform valid message padding on the input data to be padded according to the valid message padding rule.

[0034] Among them, the target computing unit refers to the part that performs algorithmic logical operations in the iterative computing module. In the implementation of the SHA-3 algorithm, the target computing unit refers to the computing module that includes the KECCAK-f function. Different algorithm types correspond to different target computing units and also different valid message padding rules. The valid message padding rule refers to a data padding rule that meets the algorithm requirements and can be correctly recognized, processed, and achieve the expected function. The padded data content has a clear semantics and can be effectively utilized by the system. Valid message padding requires adding a binary bit sequence at the end or a specific position of the input data to be padded so that the data length reaches an integer multiple of the length of the minimum data unit, obtaining the data to be grouped.

[0035] Accordingly, finding the corresponding padding rule by obtaining the algorithm type of the target computing unit effectively improves the accuracy of data padding, enables the system to have good compatibility, and also enhances the security of the data.

[0036] Accordingly, in one embodiment, the grouping unit is specifically configured to group the data to be grouped according to the length of the minimum data unit, obtaining multiple groups of initial grouped data; and perform invalid message padding on each group of initial grouped data to obtain multiple groups of target input data.

[0037] Among them, the grouping unit is specifically configured to obtain the sub-function of the target computing unit; determine the target length of the target input data according to the sub-function; and perform invalid message padding on each group of initial grouped data according to the target length of the target input data to obtain multiple groups of target input data with the target length.

[0038] Among them, the invalid message padding is to expand the data to be grouped to the target length by padding with invalid data, so that the target input data length conforms to the algorithm rules of the sub-function. The sub-function refers to the core operation function in the target computing unit. For example, the sub-function of the target computing unit SHA3-224(M) is the KECCAK-f function. Different sub-functions correspond to different requirements for the length of the input data. For example, the target length of the target input data of the KECCAK-f function is 1600. The grouping unit determines the target length of the target input data by obtaining the sub-function of the target computing unit. The grouping unit first groups the data to be grouped according to the minimum data unit length to obtain multiple groups of initial grouped data, and then performs invalid message padding on each initial grouped data according to the determined target length to generate multiple groups of target input data with the same length and meeting the operation requirements of the target computing unit, and inputs them into the iterative calculation module. Accordingly, by performing invalid information padding, the calculation errors caused by the substandard data length are reduced, and the reliability of data processing is improved.

[0039] Based on the above embodiments, as Figure 3 shown, it is a schematic structural diagram of the iterative calculation unit provided by the embodiment of the present application. As an implementable manner, in one embodiment, the iterative calculation unit includes: An exclusive OR unit, configured to perform an exclusive OR calculation on the target input data and the output result of the previous iterative calculation unit to obtain the data to be calculated; An encoding identifier determination unit, configured to perform an exclusive OR calculation on the data to be calculated and the output result of the previous iterative calculation unit to obtain a target exclusive OR result, and determine an encoding identifier according to the target exclusive OR result; An inverter, configured to perform a pre-flip on the data to be calculated when the encoding identifier indicates that the data to be calculated meets a preset pre-flip condition, so as to convert the data to be calculated into the data to be calculated and inverted, and write the data to be calculated and inverted and the encoding identifier into a register; A register, configured to cache the data to be calculated and inverted and the encoding identifier; A target computing unit, configured to access the register to obtain the data to be calculated and converted into the data to be calculated and inverted from the register, perform a target calculation on the data to be calculated and inverted, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit.

[0040] Specifically, the iterative calculation module includes multiple iterative calculation units. The output result of the previous iterative calculation unit refers to the result generated after the target calculation unit completes the previous round of iterative operations. The exclusive-OR unit will perform a bitwise exclusive-OR operation on the target input data and the output result of the previous iterative calculation unit, and the result is the data to be calculated. The input values of the first group of exclusive-OR units are the first grouped target input data and the initial value, and the initial value is all 0, that is, the initial value is a binary coding sequence with all 0s of the target length. Specifically, the encoding identifier is a 1-bit binary control signal. When m = 0, the data to be calculated remains unchanged from the original data. When m = 1, that is, when the data to be calculated does not meet the preset pre-inversion condition, the data to be calculated is the bitwise inversion result of the original data to obtain the inverted data to be calculated. The dynamic power consumption of the chip is mainly due to multiple signal dynamic flips during the target calculation process. Since when the encoding identifier indicates that the data to be calculated meets the preset pre-inversion condition, an inverter is used to perform pre-inversion on the data to be calculated, the dynamic power consumption generated by the inverter for pre-inversion is much less than the dynamic power consumption generated by using the algorithm for target calculation. And before performing the target calculation, the encoding identifier judges whether the number of data bit flips that occur when the data to be calculated is pre-inverted and then the target calculation is performed is more, or the number of data bit flips that occur without pre-inversion is more, based on the difference between the data to be calculated and the target calculation result, so as to flexibly select the encoding method that minimizes the dynamic power consumption.

[0041] Specifically, the dynamic power consumption generated by the pre-flip of the inverter is much smaller than the dynamic power consumption generated by the algorithm for target calculation. The structure of the inverter is simple, the load capacitance is small, and the short-circuit current duration is short during each flip, so the power consumption is low. However, the target calculation corresponding to the algorithm depends on a complex circuit with multiple logic gates cascaded. During operation, a large number of bit concurrent flips will be triggered, and there is a cascading effect, resulting in a significant increase in the flip rate. Therefore, the dynamic power consumption generated by the algorithm for target calculation far exceeds the dynamic power consumption generated by the pre-flip using the inverter. Therefore, the system pre-flips the data to be calculated by judging the coding identifier, reducing the dynamic power consumption generated by the target calculation corresponding to the algorithm. When the coding identifier indicates that the data to be calculated meets the preset pre-flip condition, the data to be calculated is pre-flipped using the inverter, the data to be calculated is bitwise parallel inverted, the data to be calculated is converted into the data to be calculated and inverted, and the data to be calculated and inverted and the coding identifier are written into the register. For example, if the original value of signal A is 8’b0000_0010 and needs to be updated to 8’b1111_0100 after target calculation in the next clock cycle, then a total of 6 bit flips occur, including 1-0 and 0-1, which can be simply considered to generate 6 groups of dynamic power consumption. To reduce the dynamic power consumption, the embodiment of the present application uses the following scheme. First, add 1 bit of coding bit (coding identifier), that is, m bits. The relationship between the true value of the data and the coding bit is as follows: when m = 0, the coding value (data to be calculated) is equal to the original value; when m = 1, each bit of the coding value is equal to the bitwise inversion of the corresponding bit of the original value. 8’b1111_0100 can be represented in the following two ways. The first is m = 0, and the coding value EN_D = 8’b1111_0100. The second is m = 1, and the coding value EN_D = 8’b0000_1011. If the embodiment of the present application represents it in the second way, and the original value of signal A is 8’b0000_0010 and needs to be updated to 8’b1111_0100 after target calculation in the next clock cycle, then a total of 3 bit flips occur, including 1 flipping to 0 and 0 flipping to 1, including 2 data bit flips and 1 coding bit flip, which can be simply considered to generate 3 groups of dynamic power consumption, thus achieving power consumption reduction. When performing the KECCAK-f function operation in the SHA-3 algorithm, the data is all 1600-bit data. Therefore, when flipping, multiple bit flips are involved, generating dynamic power consumption. Therefore, when storing data during every two rounds of KECCAK-f function calculations, the data coding method, that is, adding m coding bits, can be used to achieve power consumption reduction.

[0042] Specifically, the sub-functions in the target computing unit are determined by the type of algorithm. The target computing unit first accesses the register, and uses the data to be calculated in the register that is in the inverted phase or does not meet the pre-flipping condition as the input data. In the target computing unit, corresponding target calculations are performed according to the sub-functions to obtain the target calculation result, and the obtained target calculation result is used as the output result and input to the next iterative computing unit. In the target computing unit, dynamic power consumption will be generated due to the flipping of the data to be calculated or the data to be calculated in the inverted phase according to the target calculation corresponding to the algorithm. For example, the sub-function of the SHA-3 algorithm is the KECCAK-f function, and the formula of the KECCAK-f function is as follows:

[0043] Among them, represents the process of XORing the respective 5 bits of two columns around a certain bit and then XORing with that bit. represents a circular shift of 25 Lanes. represents a fixed transposition of the Slice. represents a bit combination of the row. represents modifying some bits of Lane(0, 0), represents the iteration round. The iteration round of the SHA-3 algorithm is 24 rounds, which can indicate which round it is currently in. During the calculation, the above function calculation is performed using the encoded value (data to be calculated / data to be calculated in the inverted phase) EN_D. After the calculation is completed, the output data bit is denoted as F_out, that is, the target calculation result. The m output value remains the same as when it is input, m_out = m_in, where m_out is the output value of the encoded identifier and m_in is the input value of the encoded identifier. Correspondingly, the XOR unit and the encoded identifier determination unit can dynamically determine the encoded identifier, judge whether it is necessary to reduce the dynamic flipping power consumption by the pre-flipping method, and provide a judgment basis for reducing the dynamic flipping power consumption. The inverter pre-flips the data, reducing the subsequent dynamic flipping power consumption caused by the algorithm. The caching function of the register ensures the stability of data transmission, reduces the dynamic power consumption, and improves the energy efficiency and reliability of the system.

[0044] Correspondingly, in an embodiment, the encoded identifier determination unit includes a plurality of basic XOR calculation units, which are used to perform XOR calculations on each data bit of the data to be calculated and the output result of the previous iterative computing unit in parallel to obtain the target XOR result; among them, the number of data bits of the data to be calculated and the output result of the previous iterative computing unit is the same; an adder, which is used to determine the number of different data bits between the data to be calculated and the output result of the previous iterative computing unit according to the target XOR result, and determine the encoded identifier according to the size relationship between the number of different data bits and a preset threshold.

[0045] Among them, the adder is specifically used to determine the target bit width of the binary register of the target exclusive-OR result according to the number of data bits of the data to be calculated; during the exclusive-OR calculation process of multiple exclusive-OR calculation basic units, based on the binary register, the cumulative difference data bit quantity is accumulated according to the target exclusive-OR result of each data bit; according to the target bit width of the binary register and the preset threshold, the target monitoring bit is determined; when the target monitoring bit indicates that the difference data bit quantity is greater than the preset threshold, the coding identifier is determined as the target coding; among them, when the coding identifier is the target coding, the data to be calculated meets the preset pre-inversion condition.

[0046] Specifically, the number of data bits of the data to be calculated is the same as that of the output result of the previous iteration calculation unit and they correspond one by one. The target exclusive-OR result obtained by performing exclusive-OR on each corresponding data bit is input into the carry-lookahead adder for cumulative calculation, and the quantity of difference data bits is accumulated. The maximum value of the cumulative result is the total number of data bits of the data to be calculated and the output result of the previous iteration calculation unit, and the minimum value is 0. The target bit width is the number of binary digits that can represent the total number of data bits of the data to be calculated and the output result of the previous iteration calculation unit. The preset threshold is half of the total number of data bits of the data to be calculated and the output result of the previous iteration calculation unit. The binary bit in the binary register corresponding to the numerical value that can represent the preset threshold is the target monitoring bit. During the process of accumulating the number of difference data bits, when all the target monitoring bits are 1, it indicates that the difference data bit quantity is greater than the preset threshold, that is, when the number of signal flips generated by performing the target calculation on the inverted data to be calculated obtained by using the inverter is less than the number of signal flips generated by directly using the original data to be calculated for the target calculation, that is, it meets the preset pre-inversion condition. The dynamic power consumption of the chip can be reduced through the coding mode of data inversion, that is, the coding identifier is determined as the target coding, that is, the coding identifier is set to 1.

[0047] Exemplarily, such as Figure 4As shown in the figure, it is a schematic structural diagram of the encoding identifier determination unit provided by an embodiment of the present application. The hardware architecture of this encoding identifier calculation method consists of multiple exclusive-OR units, a carry skip adder (CSA for short), and an encoding identifier update module. The input ends of multiple exclusive-OR units are the output results of the previous iteration calculation unit and the data to be calculated. The output results of the previous iteration calculation unit and the data to be calculated are XORed bit by bit one by one, and the obtained target XOR result is input into the carry skip adder for cumulative calculation to accumulate the number of different data bits. The binary register in the carry skip adder can represent the number of different data bits. Since the different data bits are represented by binary numbers, it can represent half of the total number of data bits of the data to be calculated and the output result of the previous iteration calculation unit. Its corresponding binary bit is the target monitoring bit. When all the target monitoring bits are 1, it indicates that the number of different data bits is greater than the preset threshold, indicating that the number of bits to be flipped exceeds half. The binary register is used to update the encoding identifier, and the value of the encoding identifier is updated to the inverse of the encoding identifier value output by the previous set of target calculation results, that is, 0 becomes 1 and 1 becomes 0. When the number of different data bits is less than the preset threshold, the value of the encoding identifier remains unchanged, and the value of the encoding identifier is output to the register in the register module. For example, there are a total of 1600 single-bit exclusive-OR units, where F_out is the output value of the previous f function (iteration calculation unit), that is, the output result of the previous iteration calculation unit. The f function is a sub-function of the target calculation unit and is an initial value of all 0s in the first round. Xor is the data to be calculated, and Xor = F_out group_n, where Represents an exclusive OR operation, and group_n is multiple groups of target input data. The exclusive OR value of 1600 bits, that is, the target exclusive OR result, is accumulated using CSA. The accumulated result is denoted as sum a. The maximum value of sum a is 1600, and the minimum value is 0. Therefore, it can be represented by a binary register with a total bit width of 11. Among them, half of the total number of data bits of the data to be calculated and the output result of the previous iteration calculation unit is half of the total number of 1600. Therefore, the preset threshold is 895. Due to the characteristics of the carry look-ahead adder, that is, each bit of the addition result can be calculated independently. Only calculate 3 bits from bit 9 to bit 7 of suma, denoted as add 3, that is, the target monitoring bit, and do not calculate other bits. In this way, some logic resources can be saved. Generate a new m value. If add_3 = 3'b111, that is, each bit of the target monitoring bit is 1. At this time, add > 895, indicating that the number of data bits of the data to be calculated that need to be flipped and the output result of the previous iteration calculation unit exceeds half of the total number. At this time, update the output value of the encoding flag m to the opposite value of the m value output by the previous group of data. Among them, m_pre_out represents the m value output by the previous group of data, that is, m_out =!m_pre_out, and! represents taking the inverse, that is, 0 is flipped to 1, and 1 is flipped to 0. Otherwise, m remains the m value output by the previous group of data, that is, m_out = m_pre_out.

[0048] Exemplarily, such as Figure 5 As shown, it is a schematic structural diagram of an exemplary register module provided by an embodiment of the present application. The register module includes an inverter and a register. The inverter directly outputs the data to be calculated on the one hand, and on the other hand, outputs the inverted data to be calculated after inverting each bit of the data to be calculated. At the multiplexer, it is judged according to the encoding flag to determine whether the condition for pre-flipping is met. When the encoding flag meets the condition for pre-flipping, that is, when m = 1, the inverted data to be calculated after inverting all the data to be calculated and the encoding flag are input into the register of the register module. When the encoding flag does not meet the condition for pre-flipping, the data to be calculated and the encoding flag are input into the register of the register module.

[0049] Correspondingly, by the relationship between the number of differential data bits characterized by the target exclusive OR result and the preset threshold, the value of the encoding flag is dynamically selected. Further, a signal flipping method with less dynamic power consumption can be flexibly selected, which improves the accuracy of system power consumption optimization. By judging whether the preset threshold is triggered for pre-flipping, the resource consumption of all data calculations is avoided, the real-time performance is improved, and the efficiency of the system is increased.

[0050] On the basis of the above embodiments, as an implementable manner, in an embodiment, the iterative calculation unit is further configured to: In the case where the encoding identifier indicates that the data to be calculated does not meet the preset pre - flip condition, directly perform the target calculation on the data to be calculated, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit.

[0051] Specifically, when the number of signal flips generated by performing the target calculation corresponding to the algorithm on the inverted data to be calculated obtained by using an inverter is more than the number of signal flips generated by directly performing the target calculation on the original data to be calculated, it does not meet the preset pre - flip condition. The dynamic power consumption generated by the flip during the target calculation between the data to be calculated is less, so there is no need for pre - flipping. Then, directly input the data to be calculated into the target calculation unit for target calculation, and input the target calculation result into the next iterative calculation unit.

[0052] Correspondingly, through dynamic decision - making, the data conversion operation is reduced, the processing path is flexibly adjusted, and unnecessary signal flips and power consumption are reduced on the premise of ensuring data processing accuracy.

[0053] Based on the above - mentioned embodiments, as an implementable manner, in one embodiment, the iterative calculation module further includes: An extrusion unit, configured to perform extrusion processing on the output result of the last iterative calculation unit when the length of the output result of the last iterative calculation unit is greater than the minimum data unit length of the target calculation unit, so as to decompose the output result of the iterative calculation unit into multiple output sub - results; Wherein, the length of the output sub - result is equal to the minimum data unit length, and the data processing result includes multiple output sub - results.

[0054] Specifically, the extrusion unit mainly normalizes the output result data of the last iterative calculation unit. When the length of the output result generated by the last iterative calculation unit exceeds the minimum data unit length of the target calculation unit, the extrusion unit starts the extrusion processing. According to the data output rule corresponding to the algorithm, the output result generated by the last iterative calculation unit is processed, and the output result with an excessive length is decomposed into multiple output sub - results with equal lengths, and the length of each output sub - result is the same as the minimum data unit length. Multiple groups of output sub - results together constitute the data processing result.

[0055] Exemplarily, such as Figure 6As shown in the figure, it is a schematic structural diagram of an exemplary data processing system provided by an embodiment of the present application. It mainly includes: for the original input data, first judge the size relationship between the input bit width of the original input data and the minimum data unit length of the target calculation unit. When the input bit width of the original input data is less than the minimum data unit length of the target calculation unit, perform data aggregation on the original input data to obtain the input data to be filled. When the input bit width of the original input data is equal to the minimum data unit length of the target calculation unit, directly use the original input data as the input data to be filled. Then, perform valid message filling on the input data to be filled according to the valid message filling rule of the determined algorithm type of the target calculation unit to obtain the data to be grouped with a length equal to an integer multiple of the minimum data unit length. Group the data to be grouped according to the minimum data unit length to obtain multiple groups of initial grouped data. Then, perform invalid message filling on each group of initial grouped data to obtain multiple groups of target input data. The above process belongs to the data input module, and the output result of the data input module is multiple groups of target input data. Then, input the multiple groups of target input data into the iterative calculation module. The iterative calculation module includes multiple groups of iterative calculation units, an extrusion unit, and a result output module. Among them, the iterative calculation unit is successively composed of an exclusive OR unit, a coding identifier determination unit, an inverter, a register, and a target calculation unit. The inverter and the register together form the register module. The system first inputs the initial value and the first group of target input data into the exclusive OR unit to obtain the data to be calculated. Then, input the initial value and the data to be calculated into the coding identifier determination unit to obtain the target exclusive OR result. Determine the coding identifier according to the target exclusive OR result. When the coding identifier indicates that the data to be calculated meets the preset pre-flip condition, perform pre-flip on the data to be calculated to obtain the inverted data to be calculated, and write the inverted data to be calculated and the coding identifier into the register. Then, input the inverted data to be calculated into the target calculation unit for target calculation. When the coding identifier indicates that the data to be calculated does not meet the preset pre-flip condition, write the data to be calculated and the coding identifier into the register and perform target calculation, and input the target calculation result into the next iterative calculation unit. The second group inputs the target calculation result of the first group of iterative calculation units and the second group of target input data into the exclusive OR unit for calculation. The remaining process is the same as that of the first group of iterative units, and so on until all the target input data is input.

[0056] In the processing flow of the SHA-3 algorithm, both the iterative calculation unit and the squeezing unit are completed in series using the KECCAK-f function (the target calculation unit). The iterative calculation unit absorbs the target input data and performs corresponding data processing. The input of the squeezing unit is the final target calculation result output by the iterative calculation unit. First, before intercepting according to the hash output length corresponding to the algorithm from this state, for example, SHA3-224 takes 224 bits as the initial hash segment. If more output is required, the KECCAK-f function will be executed again on the current state, and then the bits of the new hash output length will be intercepted and appended to the output. By repeating the operations of calling the KECCAK-f function and intercepting segments like this, multiple corresponding output sub-results are finally obtained.

[0057] Correspondingly, through the squeezing unit, the problem of the output result length of the last iterative calculation unit exceeding the limit can be solved, and the output result is decomposed into standardized sub-results to ensure the unity of the data format.

[0058] Based on the above embodiments, as an implementable manner, in one embodiment, the system further includes: A result output module, which is used to perform a digest process on the data processing result according to the encoding identifier to obtain the target digest value of the data processing result and output the target digest value.

[0059] Specifically, the result output module performs a digest process on the output result of the last iterative calculation unit. The digest process refers to compressing the data processing result into a target digest value with a fixed length using an algorithm. The target digest value is the unique identifier for data integrity verification, identity authentication, etc. At the same time, it provides a standardized data input for the next operation. According to the output data length, it determines the length of the output digest value and whether to perform the subsequent squeezing stage, and outputs the final result. For example, according to the m judgment encoding value, when m is 0, the encoding value EN_D = Xor for this time, when m is 1, the encoding value EN_D = ~Xor, where ~ represents the bitwise inversion operation, and Xor is implemented in parallel through 1600 inverters. Then the encoding value EN_D and the m bits are input into the register as input values. When the digest value is output, the encoding value needs to be converted into the original value, that is, when m is 1, the encoding value is bitwise inverted and assigned to the output digest value digest = ~EN_D, where ~ represents the bitwise inversion operation, and when m is 0, the encoding value is directly assigned to the output digest value digest = EN_D.

[0060] Correspondingly, through the squeezing unit, it can provide a standardized input data for the next processing of subsequent data, reduce the dynamic power consumption caused by non-standard data again, shorten the overall processing time, improve the efficiency of the system, and ensure the compatibility, efficiency and security of the data processing system.

[0061] According to the different impacts of each bit data in the algorithm on power consumption, it is accurately divided into high and low power consumption sensitive areas. For example, in the SHA-3 algorithm, the key path data directly participating in the core operations (θ, ρ, π, χ, ι) of the KECCAK-f function is divided into the high sensitive area because the signal flip directly affects the operation result. While for the padding bits and non-core operation auxiliary data with little impact on power consumption caused by signal flips, they can be classified as low power consumption sensitive areas. For different areas, different coding strategies are adopted. For the high sensitive area, the original coding rules are strictly followed to ensure the accuracy of algorithm operations, while for the low sensitive area, the restrictions can be relaxed to allow setting a higher flip threshold to reduce unnecessary coding flips, thereby reducing the consumption of logic resources. On the basis of ensuring the correct operation of the SHA-3 algorithm, the refined control of power consumption and logic resources is realized, and the adaptability and efficiency of the solution in different hardware environments and application scenarios are improved. For example, in the SHA-3 algorithm, based on the difference in the impact of bit positions on operation correctness and power consumption, the area is divided. The key bits directly participating in the core operations (θ / ρ / π / χ / ι) of the KECCAK-f function, such as the bits participating in column XOR in the θ operation and the first byte of the χ operation that causes chain changes in row states, have a high signal flip frequency and directly affect the correctness of the hash result, and are divided into the high sensitive area accounting for about 40%. While for the auxiliary data such as message padding bits and the last byte of non-critical Lanes, where the impact of flipping on power consumption accounts for less than 30% and delayed processing is allowed, they are divided into the low sensitive area accounting for 60%. The accurate division is achieved through the address mapping table pre-stored in the chip combined with the dynamic configuration register. For the high sensitive area, the system provided in the embodiment of the present application is used for pre-flipping to ensure the operation accuracy, while for the low sensitive area, by relaxing the preset threshold from half of the total number of data bits to 70% of the total number of data bits, pre-flipping is only performed when add_3≥1120, reducing the consumption of logic resources.

[0062] The data processing system provided by the embodiment of the present application includes a data input module and an iterative calculation module. The iterative calculation module includes multiple iterative calculation units. The data input module is used to obtain the original input data to be processed, perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into the multiple iterative calculation units respectively. The iterative calculation unit is used to determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit when receiving any group of target input data and the output result of the previous iterative calculation unit. When the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, pre-flip the data to be calculated to convert the data to be calculated into the data to be calculated and inverted data. Perform target calculation on the data to be calculated and inverted data, and use the obtained target calculation result as the output result to input to the next iterative calculation unit. Among them, the target calculation includes performing data bit flipping on the data to be calculated and inverted data, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data. In the system provided by the above solution, since the original input data is preprocessed into multiple groups of target input data by the data input module and input into multiple iterative calculation units respectively to obtain the data to be calculated and the coding identifier, when the coding identifier indicates that the data to be calculated needs to be pre-flipped, pre-flip the data to be calculated to obtain the data to be calculated and inverted data. The subsequent iterative calculation unit only needs to perform target calculation on the data to be calculated and inverted data to obtain the data processing result, that is, the iterative calculation unit only needs to perform a small number of data bit flips on the data to be calculated and inverted data through target calculation to obtain the data processing result, reducing the number of data bit flips occurring in the target calculation and reducing the dynamic flipping power consumption. Compared with the power consumption reduction methods in the related art, the present application does not require high-difficulty chip backend layout and wiring, and can ensure the performance and power consumption reduction effect of the chip. Moreover, the acquisition unit can judge the relationship between the input bit width of the original input data and the minimum data unit length of the target calculation unit, and then perform data aggregation processing on the original input data according to the judgment result to realize splicing data. The filling unit can perform effective message filling on the data to be filled according to the specific filling rules corresponding to different algorithm types, improving the accuracy of effective data filling. The grouping unit can accurately and equally divide the filled data into groups according to the minimum data unit length to generate standard target input data, providing ideal input data for the iterative calculation module to ensure that the subsequent iterative calculation units can operate normally and laying a foundation for improving the calculation efficiency. When the input bit width of the original input data is equal to the minimum data unit length of the target calculation unit, the data aggregation processing can be ignored, reducing the resource waste caused by unnecessary operations when the original input data meets the requirements. Finding the corresponding filling rule by obtaining the algorithm type of the target calculation unit effectively improves the accuracy of data processing, enables the system to have good compatibility, and also enhances the security of the data.Reduces calculation errors caused by non-compliant data lengths and improves the reliability of data processing. The exclusive OR unit and the coding identifier determination unit can dynamically determine the coding identifier, judge whether it is necessary to reduce the dynamic switching power consumption by means of pre-flipping, and provide a judgment basis for reducing the dynamic switching power consumption. The inverter pre-flips the data, reducing the subsequent dynamic switching power consumption caused by the algorithm. The buffering function of the register ensures the stability of data transmission, reduces the dynamic power consumption, and improves the energy efficiency and reliability of the system. By comparing the number of different data bits represented by the target exclusive OR result with the preset threshold, the value of the coding identifier is dynamically selected, and further, a signal flipping method with less dynamic power consumption can be flexibly selected, improving the accuracy of system power consumption optimization. By judging whether the preset threshold is triggered for pre-flipping, the resource consumption of all data calculations is avoided, the real-time performance is improved, and the system efficiency is increased. By making dynamic decisions, data conversion operations are reduced, the processing path is flexibly adjusted, and unnecessary signal flipping and power consumption are reduced on the premise of ensuring the accuracy of data processing. The extrusion unit can solve the problem of the output result length of the last iterative calculation unit exceeding the limit, decompose the output result into standardized sub-results, and ensure the unity of the data format. The extrusion unit can provide standardized input data for the next-step processing of subsequent data, reduce the dynamic power consumption caused by non-standard data again, shorten the overall processing time, improve the system efficiency, and ensure the compatibility, efficiency, and security of the data processing system.

[0063] From the description of the above embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0064] The embodiment of the present application provides a data processing method, which is applied to the data processing system provided in the above embodiment. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a notebook computer, a tablet computer, and other electronic devices that can be used for data processing.

[0065] As Figure 7 shown, it is a schematic flowchart of the data processing method provided by the embodiment of the present application. The method includes: Step 701, obtain the original input data to be processed; Step 702, perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into multiple iterative calculation units respectively; Step 703, based on the iterative calculation unit, determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit; Step 704, when the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, perform pre-flipping on the data to be calculated to convert the data to be calculated into the data to be calculated in the inverted phase; Step 705, perform target calculation on the data to be calculated in the inverted phase, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit; Among them, the target calculation includes performing data bit flipping on the data to be calculated in the inverted phase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0066] For the description of the features in the corresponding embodiments of the data processing method, reference can be made to the relevant descriptions in the corresponding embodiments of the data processing system, which will not be elaborated here one by one.

[0067] An embodiment of the present application also provides a data processing device for executing the data processing method provided in the above embodiment.

[0068] As Figure 8 shown, it is a schematic structural diagram of the data processing device provided in an embodiment of the present application. The data processing device 80 includes an acquisition module 801, a data preprocessing module 802, a determination module 803, a flipping module 804, and a calculation module 805.

[0069] Among them, the acquisition module is used to acquire the original input data to be processed; the data preprocessing module is used to perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into multiple iterative calculation units respectively; the determination module is used to determine the data to be calculated and the coding identifier based on the iterative calculation unit according to the target input data and the output result of the previous iterative calculation unit; the flipping module is used to perform pre-flipping on the data to be calculated when the coding identifier indicates that the data to be calculated meets the preset pre-flipping condition, so as to convert the data to be calculated into the data to be calculated in the inverted phase; the calculation module is used to perform target calculation on the data to be calculated in the inverted phase, and use the obtained target calculation result as the output result and input it into the next iterative calculation unit; among them, the target calculation includes performing data bit flipping on the data to be calculated in the inverted phase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0070] For the description of the features in the corresponding embodiments of the data processing device, reference can be made to the relevant descriptions in the corresponding embodiments of the data processing method, which will not be elaborated here one by one.

[0071] An embodiment of the present application also provides an electronic device, as Figure 9As shown in the figure, it is a schematic structural diagram of an electronic device provided by an embodiment of the present application, including a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above-mentioned data processing method embodiments.

[0072] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned data processing method embodiments when running.

[0073] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0074] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data processing method embodiments.

[0075] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data processing method embodiments.

[0076] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0077] The above has introduced in detail a data processing system, method, electronic device, and storage medium provided by the present application. Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data processing system, characterized in that, Including: A data input module and an iterative calculation module, where the iterative calculation module includes multiple iterative calculation units: The data input module is used to obtain the original input data to be processed, perform data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and input the multiple groups of target input data into the multiple iterative calculation units respectively; The iterative calculation unit is used to determine the data to be calculated and the coding identifier according to the target input data and the output result of the previous iterative calculation unit when receiving any group of target input data and the output result of the previous iterative calculation unit; In the case where the coding identifier indicates that the data to be calculated meets the preset pre-flip condition, perform pre-flip on the data to be calculated to convert the data to be calculated into the data to be calculated and inverted; Perform target calculation on the data to be calculated and inverted, and use the obtained target calculation result as the output result to input to the next iterative calculation unit; Wherein, the target calculation includes performing data bit flipping on the data to be calculated and inverted, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

2. The data processing system according to claim 1, wherein The data input module includes: An acquisition unit, configured to acquire the original input data to be processed, and judge the size relationship between the input bit width of the original input data and the minimum data unit length of the target calculation unit; when the input bit width of the original input data is less than the minimum data unit length of the target calculation unit, perform data aggregation processing on the original input data to obtain the to-be-filled input data with a length equal to the minimum data unit length; A filling unit, configured to perform valid message filling on the to-be-filled input data to obtain the to-be-grouped data with a length equal to an integer multiple of the minimum data unit length; A grouping unit, configured to perform data grouping on the to-be-grouped data to obtain multiple groups of target input data; Wherein, the iterative calculation unit includes the target calculation unit.

3. The data processing system according to claim 2, wherein The acquisition unit is further configured to: When the input bit width of the original input data is equal to the minimum data unit length of the target calculation unit, directly use the original input data as the to-be-filled input data.

4. The data processing system according to claim 2, wherein The filling unit is specifically configured to: Obtain the algorithm type of the target calculation unit; Determine the valid message filling rule according to the algorithm type; Perform valid message filling on the to-be-filled input data according to the valid message filling rule.

5. The data processing system according to claim 2, wherein The grouping unit is specifically configured to: Perform data grouping on the to-be-grouped data according to the minimum data unit length to obtain multiple groups of initial grouped data; Perform invalid message filling on each group of initial grouped data to obtain multiple groups of target input data.

6. The data processing system according to claim 5, wherein The grouping unit is specifically configured to: Obtain the sub-function of the target calculation unit; Determine the target length of the target input data according to the sub-function; Perform invalid message filling on each group of initial grouped data according to the target length of the target input data to obtain multiple groups of target input data with the target length.

7. The data processing system according to claim 1, wherein The iterative calculation unit includes: An exclusive-OR unit is used to perform an exclusive-OR calculation on the target input data and the output result of the previous iteration calculation unit to obtain data to be calculated; An encoding identifier determination unit is used to perform an exclusive-OR calculation on the data to be calculated and the output result of the previous iteration calculation unit to obtain a target exclusive-OR result, and determine the encoding identifier according to the target exclusive-OR result; An inverter is used to pre-flip the data to be calculated when the encoding identifier indicates that the data to be calculated meets a preset pre-flip condition, so as to convert the data to be calculated into data to be calculated and inverted, and write the data to be calculated and inverted and the encoding identifier into a register; A register is used to cache the data to be calculated and inverted and the encoding identifier; A target calculation unit is used to access the register to obtain the data to be calculated and converted into data to be calculated and inverted from the register, perform a target calculation on the data to be calculated and inverted, and use the obtained target calculation result as an output result and input it to the next iteration calculation unit.

8. The data processing system according to claim 7, wherein The encoding identifier determination unit includes: Multiple exclusive-OR calculation basic units are used to perform exclusive-OR calculations on each data bit of the data to be calculated and the output result of the previous iteration calculation unit in parallel to obtain a target exclusive-OR result; wherein, the number of data bits of the data to be calculated and the output result of the previous iteration calculation unit is the same; An adder is used to determine the number of different data bits between the data to be calculated and the output result of the previous iteration calculation unit according to the target exclusive-OR result, and determine the encoding identifier according to the size relationship between the number of different data bits and a preset threshold.

9. The data processing system according to claim 8, wherein The adder is specifically used for: Determining the target bit width of the binary register of the target exclusive-OR result according to the number of data bits of the data to be calculated; During the exclusive-OR calculation process of the multiple exclusive-OR calculation basic units, accumulating the number of different data bits based on the binary register according to the target exclusive-OR result of each data bit; Determining a target monitoring bit according to the target bit width of the binary register and the preset threshold; When the target monitoring bit indicates that the number of different data bits is greater than the preset threshold, determining the encoding identifier as a target encoding; Wherein, when the encoding identifier is the target encoding, the data to be calculated meets a preset pre-flip condition.

10. The data processing system according to claim 1, wherein The iteration calculation unit is further used for: When the encoding identifier indicates that the data to be calculated does not meet the preset pre-flip condition, directly performing a target calculation on the data to be calculated, and using the obtained target calculation result as an output result and inputting it to the next iteration calculation unit.

11. The data processing system according to claim 1, wherein The iteration calculation module further includes: An extrusion unit is used to perform an extrusion process on the output result of the last iteration calculation unit when the length of the output result of the last iteration calculation unit is greater than the minimum data unit length of the target calculation unit, so as to decompose the output result of the iteration calculation unit into multiple output sub-results; Wherein, the length of the output sub-result is equal to the minimum data unit length, and the data processing result includes the multiple output sub-results.

12. The data processing system according to claim 1, wherein The system further includes: A result output module, configured to perform a summary process on the data processing result according to the encoding identifier, so as to obtain a target summary value of the data processing result, and output the target summary value.

13. A data processing method, applied to the data processing system according to any one of claims 1 to 12, characterized in that, The method includes: Obtaining original input data to be processed; Performing data preprocessing on the original input data to convert the original input data into multiple groups of target input data, and respectively inputting the multiple groups of target input data into multiple iterative calculation units; Based on the iterative calculation unit, determining data to be calculated and an encoding identifier according to the target input data and the output result of the previous iterative calculation unit; When the encoding identifier indicates that the data to be calculated meets a preset pre-flipping condition, performing pre-flipping on the data to be calculated to convert the data to be calculated into data to be calculated in antiphase; Performing target calculation on the data to be calculated in antiphase, and using the obtained target calculation result as an output result to input to the next iterative calculation unit; Wherein, the target calculation includes performing data bit flipping on the data to be calculated in antiphase, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

14. An electronic device, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the steps of the data processing method as described in claim 13 when executing the computer program.

15. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the data processing method as described in claim 13.

16. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the data processing method as described in claim 13.

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