Assertion-based clock reset verification method and device, equipment and storage medium

Abstract

The invention provides an assertion-based clock reset verification method, device and equipment and a storage medium, relates to the technical field of signal verification, is applied to a digital circuit, and comprises the following steps: obtaining an input signal generated by an excitation source; the input signal comprises at least one of a clock signal and a reset signal; determining an assertion execution sequence based on the input signal and a preset assertion priority; performing signal verification on the input signal based on a preset assertion statement according to the assertion execution sequence; wherein the assertion statements comprise a clock signal frequency assertion statement, a clock signal duty ratio assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement and a reset signal release assertion statement. In the mode, the requirement of a modern complex digital circuit on efficient and accurate verification of the clock signal and the reset signal is met.

Description

Technical Field

[0001] The present invention relates to the technical field of signal verification, and in particular to an assertion-based clock reset verification method, device, equipment and storage medium. Background Art

[0002] In digital circuit design, clock and reset signals are key elements to ensure the normal operation of the circuit. The clock signal provides a synchronous timing reference for each logic unit in the circuit to ensure that data is processed and transmitted at the correct time; the reset signal is used to initialize the state of the circuit to a known stable state when the system starts, in case of abnormal conditions or specific operations. Therefore, it is important to verify the clock and reset signals to ensure the stability of the circuit.

[0003] In the related art, the verification methods mainly include two ways: simulation-based and formal verification-based, but it is difficult to meet the requirements of modern complex digital circuits for efficient and accurate verification of clock reset signals. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an assertion-based clock reset verification method, device, equipment and storage medium to meet the requirements of modern complex digital circuits for efficient and accurate verification of clock signals and reset signals.

[0005] In a first aspect, an embodiment of the present invention provides an assertion-based clock reset verification method, which obtains an input signal generated by an excitation source; the input signal includes at least one of a clock signal and a reset signal; determines an assertion execution order based on the input signal and a pre-set assertion priority; and performs signal verification on the input signal based on a pre-set assertion statement in accordance with the assertion execution order; wherein the assertion statement includes: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

[0006] In a preferred embodiment of the present invention, the determining the assertion execution order based on the input signal and a pre-set assertion priority includes: determining the parameters to be verified of the input signal; when the input signal is a clock signal, the parameters to be verified include at least one of a clock signal frequency, a clock signal duty cycle, and a clock signal jitter; when the input signal is a reset signal, the parameter to be verified includes one of a reset signal validity and a reset signal release; and performing assertion execution sorting on the parameters to be verified based on the assertion priority to obtain the assertion execution order.

[0007] In a preferred embodiment of the present invention, the signal verification of the input signal based on the pre-set assertion statement includes: if the assertion statement is a clock signal frequency assertion statement, determining whether the clock signal frequency meets the pre-set clock signal frequency range through the clock signal frequency assertion statement; if the assertion statement is a clock signal duty cycle assertion statement, determining the ratio of the high-level duration to the period of the clock signal through the clock signal duty cycle assertion statement; determining whether the ratio meets the pre-set clock signal duty cycle range; if the assertion statement is a clock signal jitter assertion statement, determining the difference between adjacent periods based on consecutive clock cycles through the clock signal jitter assertion statement; determining whether the difference between adjacent periods conforms to the pre-set maximum jitter value.

[0008] In a preferred embodiment of the present invention, the signal verification of the input signal based on the pre-set assertion statement further includes: if the assertion statement is a reset signal validity assertion statement, checking whether the target node in the digital circuit is reset to the initial state when the reset signal is valid through the reset signal validity assertion statement; if the assertion statement is a reset signal release assertion statement, checking whether the digital circuit resumes operation after the reset signal is released through the reset signal release assertion statement.

[0009] In a preferred embodiment of the present invention, after the signal verification of the input signal is performed based on the pre-set assertion statement in accordance with the assertion execution order, the method further includes: adding an assertion enable signal; operating on the assertion statement through the assertion enable signal, and the operations include: pausing, executing, and annotating.

[0010] In a preferred embodiment of the present invention, after the signal verification of the input signal is performed based on the pre-set assertion statement in accordance with the assertion execution order, the method further includes: performing a coverage analysis on the signal verification to obtain an analysis result; adjusting the input signal or the assertion statement based on the analysis result.

[0011] In a preferred embodiment of the present invention, while the signal verification of the input signal is performed based on the pre-set assertion statement in accordance with the assertion execution order, the method further includes: real-time monitoring of the execution situation of the assertion statement; recording information based on the execution situation.

[0012] In a second aspect, an embodiment of the present invention further provides an assertion-based clock reset verification device, which is applied to a digital circuit. The device includes: an input signal acquisition module, configured to acquire an input signal generated by an excitation source; the input signal includes at least one of a clock signal and a reset signal; an assertion execution order determination module, configured to determine an assertion execution order based on the input signal and a preset assertion priority; a signal verification module, configured to perform signal verification on the input signal based on the assertion execution order and a preset assertion statement; wherein the assertion statement includes: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

[0013] In a third aspect, an embodiment of the present invention further provides an electronic device, including a processor and a memory. The memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the assertion-based clock reset verification method in the first aspect above.

[0014] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the assertion-based clock reset verification method in the first aspect above.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] The embodiments of the present invention provide an assertion-based clock reset verification method, device, equipment, and storage medium. By acquiring an input signal generated by an excitation source, the input signal includes at least one of a clock signal and a reset signal, determining an assertion execution order based on the input signal and a preset assertion priority, and performing signal verification on the input signal based on the assertion execution order and a preset assertion statement, wherein the assertion statement includes: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement. In this way, the requirements for efficient and accurate verification of clock signals and reset signals in modern complex digital circuits are met.

[0017] Other features and advantages of the present disclosure will be described in the subsequent specification, or some features and advantages can be inferred from the specification without doubt, or can be known by implementing the above technologies of the present disclosure.

[0018] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specific preferred embodiments are given below, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 Flowchart of a method for assertion-based clock reset verification provided by an embodiment of the present invention;

[0021] Figure 2 Flowchart of another method for assertion-based clock reset verification provided by an embodiment of the present invention;

[0022] Figure 3 Structural schematic diagram of an assertion-based clock reset verification device provided by an embodiment of the present invention;

[0023] Figure 4 Structural schematic diagram of an electronic device provided by an embodiment of the present invention. Specific embodiments

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0025] In digital circuit design, clock and reset signals are key elements to ensure the normal operation of the circuit. The clock signal provides a synchronous timing reference for each logic unit in the circuit, ensuring that data is processed and transmitted at the correct time; the reset signal is used to initialize the state of the circuit to a known stable state when the system starts, in case of abnormal situations, or during specific operations.

[0026] With the continuous expansion of the scale of integrated circuits and the increasing complexity of functions, the design and verification of clock and reset signals face many challenges. On the one hand, there may be problems such as frequency deviation, abnormal duty cycle, clock jitter, and clock skew in the clock signal. For example, in a high-speed data processing chip, a slight deviation in the clock frequency may lead to data sampling errors, which in turn cause functional failures in the entire system; an abnormal duty cycle may affect the power consumption and performance of the circuit, and even lead to logic errors. On the other hand, there may also be situations such as incomplete reset, chaotic reset timing, and asynchronous conflicts with other signals in the reset signal. For instance, if the reset signal fails to correctly reset all registers during system startup, the circuit will be in an incorrect state in the initial state, affecting subsequent normal operation.

[0027] Currently, traditional verification methods mainly include two ways: simulation-based and formal verification-based. The simulation-based verification method determines the correctness of the design by inputting a series of test vectors and observing the output response of the circuit. However, the limitation of this method is that it is difficult for test vectors to comprehensively cover all possible input combinations and circuit states, and it is easy to miss some rare abnormal situations or complex timing problems. Moreover, as the circuit scale increases, the simulation time will increase sharply, resulting in low verification efficiency. Although the formal verification-based method can comprehensively verify the circuit and theoretically can check all possible states and input combinations, it has the problem of high computational complexity. For large-scale complex circuits, it may face problems such as insufficient memory and excessive verification time, and it is also relatively difficult to understand and debug the formal verification results. Therefore, the existing verification methods are difficult to meet the requirements of modern complex digital circuits for efficient and accurate verification of clock and reset signals.

[0028] Based on this, a clock reset verification method, device, equipment, and storage medium based on assertions provided by an embodiment of the present invention can obtain an input signal generated by an excitation source, where the input signal includes at least one of a clock signal and a reset signal, determine the assertion execution order based on the input signal and a preset assertion priority, and based on the assertion execution order, perform signal verification on the input signal based on a preset assertion statement, where the assertion statement includes: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement. In this way, the requirements of modern complex digital circuits for efficient and accurate verification of clock signals and reset signals are met.

[0029] For the convenience of understanding this embodiment, first, a clock reset verification method based on assertions disclosed in an embodiment of the present invention will be introduced in detail.

[0030] Embodiment 1

[0031] An embodiment of the present invention provides an assertion-based clock reset verification method, which is applied to digital circuits. Figure 1 FIG. Figure 1 is a flowchart of an assertion-based clock reset verification method provided by an embodiment of the present invention. As Figure 1 shown, the assertion-based clock reset verification method may include the following steps:

[0032] Step S101, obtain an input signal generated by an excitation source.

[0033] Among them, the input signal includes at least one of a clock signal and a reset signal.

[0034] Among them, a verification environment including a digital circuit under test, an excitation source, and a monitoring unit may be constructed. The excitation source is used to generate input excitations such as a clock signal and a reset signal, and the monitoring unit is used to capture the execution result of the assertion and record the information violating the assertion. For example, a simulation tool (such as ModelSim, Vivado Simulator, etc.) can be used to run the verification environment.

[0035] Step S102, determine the assertion execution order based on the input signal and the preset assertion priority.

[0036] Specifically, determining the assertion execution order based on the input signal and the preset assertion priority may include: determining the parameters to be verified of the input signal; performing assertion execution sorting on the parameters to be verified based on the assertion priority to obtain the assertion execution order.

[0037] Among them, the parameters to be verified that need to be verified can be selected according to the actual situation. When the input signal is a clock signal, the parameters to be verified include at least one of the clock signal frequency, the clock signal duty cycle, and the clock signal jitter. When the input signal is a reset signal, the parameter to be verified includes one of the reset signal validity and the reset signal release. Each parameter to be verified has a corresponding assertion statement.

[0038] Step S103, verify the input signal based on the preset assertion statements in the assertion execution order.

[0039] Among them, the assertion statements include: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

[0040] Among them, in the design code of the digital circuit, according to the structure and function of the digital circuit, the designed assertion statements can be reasonably embedded in the corresponding positions. For example, for the assertion of the clock signal, it can be added near the clock generation module or the clock buffer module. For the assertion of the reset signal, it can be added in modules such as registers and state machines that use the reset signal.

[0041] The assertion - based clock reset verification method provided by an embodiment of the present invention can obtain an input signal generated by an excitation source. The input signal includes at least one of a clock signal and a reset signal. Based on the input signal and a preset assertion priority, an assertion execution order is determined. According to the assertion execution order, the input signal is verified based on preset assertion statements, where the assertion statements include: a clock signal frequency assertion statement, a clock signal duty - cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement. In this way, the requirements for efficient and accurate verification of clock signals and reset signals in modern complex digital circuits are met.

[0042] Embodiment 2

[0043] Another assertion - based clock reset verification method is also provided by an embodiment of the present invention; this method is implemented on the basis of the method in the above - mentioned embodiment.

[0044] Figure 2 is a flowchart of another assertion - based clock reset verification method provided by an embodiment of the present invention. As Figure 2 shown, the assertion - based clock reset verification method may include the following steps:

[0045] Step S201: Obtain an input signal generated by an excitation source.

[0046] Among them, the input signal includes at least one of a clock signal and a reset signal;

[0047] Step S202: Determine an assertion execution order based on the input signal and a preset assertion priority.

[0048] Among them, in complex circuit designs, there may be multiple assertions. To improve verification efficiency, different assertion priorities can be set for assertions. For some key assertions, such as the reset signal validity assertion, a higher assertion priority can be set to perform verification first; for some secondary assertions, a lower assertion priority can be set to perform verification after the key assertions pass the verification.

[0049] Step S203: According to the assertion execution order, verify the input signal based on preset assertion statements.

[0050] Among them, the assertion statements include: a clock signal frequency assertion statement, a clock signal duty - cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

[0051] Specifically, if the assertion statement is a clock signal frequency assertion statement, it is determined whether the clock signal frequency meets a preset clock signal frequency range through the clock signal frequency assertion statement.

[0052] Among them, the expected frequency value f of the clock signal can be preset expected , and the allowable frequency error range ±Δf. In the digital circuit, the corresponding assertion statement is used to monitor the actual clock frequency f in real time actual , to ensure that it satisfies the clock signal frequency range f expected -Δf ≤ f actual ≤ f expected ≤ f + Δf.

[0053] For example, for a digital circuit that requires the clock signal frequency to be 100 MHz and allows an error of ±1 MHz, the following clock signal frequency assertion statement can be written in SystemVerilog language:

[0054] assert property(@(posedge clk) ($period(clk) >= (1 / (100MHz + 1MHz)) && $period(clk) <= (1 / (100MHz - 1MHz))))

[0055] else $error("Clock frequency is out of the expected range!");

[0056] Specifically, if the assertion statement is a clock signal duty cycle assertion statement, the ratio of the high-level duration of the clock signal to the period is determined through the clock signal duty cycle assertion statement; it is determined whether the ratio satisfies the preset clock signal duty cycle range.

[0057] Among them, the upper limit duty of the clock signal duty cycle can be predefined max and the lower limit duty min , then calculate the ratio duty = of the high-level duration t high of the clock signal to the period T Tthigh , and judge whether duty min ≤ duty ≤ duty max holds through the assertion statement.

[0058] Taking the clock signal with the required clock signal duty cycle between 45% - 55% as an example, the clock signal duty cycle assertion statement can be written as:

[0059] Assert property(@(posedge clk) (($high_time(clk) / $period(clk)) >= DUTY_MIN && ($high_time(clk) / $period(clk)) <= DUTY_MAX))

[0060] Else $error("Clock duty cycle is out of the expected range!");

[0061] Specifically, if the assertion statement is a clock signal jitter assertion statement, the adjacent cycle difference is determined based on consecutive clock cycles through the clock signal jitter assertion statement; it is determined whether the adjacent cycle difference meets the pre-set maximum jitter value.

[0062] Among them, the maximum allowable jitter value Jmax can be pre-set, and then by continuously measuring multiple clock cycles T1, T2, …, Tn, the adjacent cycle difference |Ti+1 - Ti| is calculated, and assertions are used to ensure that all adjacent cycle differences are less than Jmax.

[0063] An example of a clock signal jitter assertion statement is as follows:

[0064]

[0065] Specifically, if the assertion statement is a reset signal validity assertion statement, it is checked whether the target node in the digital circuit is reset to the initial state when the reset signal is valid through the reset signal validity assertion statement.

[0066] Among them, the target node is a key node in the digital circuit, such as a register, a counter, etc.

[0067] For example, for a register reg_data with an initial value of INIT_VALUE, when the reset signal rst is valid, it is verified whether reg_data is equal to INIT_VALUE through an assertion. The example code is as follows:

[0068] assert(reg_data == INIT_VALUE)

[0069] else $error("Register is not reset to the initial value!");

[0070] Specifically, if the assertion statement is a reset signal release assertion statement, it is checked whether the digital circuit resumes operation after the reset signal is released through the reset signal release assertion statement.

[0071] Among them, to verify whether the digital circuit can resume normal operation after the reset signal is released, the values of the key nodes can change as expected.

[0072] For example, in the first clock cycle after the reset signal rst is released, the value of the register reg_data should start to be updated according to the input signal. The example code is as follows:

[0073]

[0074] To facilitate the subsequent debugging and maintenance of the assertion statements, while verifying the input signals based on the pre-set assertion statements in the order of assertion execution, the method further includes: monitoring the execution of the assertion statements in real time; recording information based on the execution.

[0075] Among them, if the execution of a certain assertion statement is that the assertion is violated, it is recorded by the monitoring unit. Specifically, information such as the time when the assertion is violated and the values of relevant signals can be recorded for analyzing the recorded information after the verification to locate the problem and modify and optimize the design.

[0076] Through the above, the assertion statement code can be automatically generated by a script and integrated into the verification environment, greatly improving the verification efficiency.

[0077] Furthermore, for some common clock and reset verification assertions, they can be encapsulated into reusable modules or functions.

[0078] For example, encapsulate the clock signal frequency assertion statement into a function, and the function can be directly called in different designs to verify the clock signal frequency, improving the code reusability and maintainability, as follows:

[0079]

[0080] Step S204, perform coverage analysis on the signal verification to obtain the analysis result, and adjust the input signal or assertion statement based on the analysis result.

[0081] Among them, during the verification process, coverage analysis can be performed to ensure that the assertions can cover various possible situations of the clock signal and reset signal. Multiple coverage metrics such as statement coverage, branch coverage, and condition coverage can be used to evaluate the sufficiency of the verification. For the uncovered situations, the assertions or stimulus sources can be further adjusted to improve the comprehensiveness of the verification.

[0082] Step S205, add an assertion enable signal, and operate on the assertion statement through the assertion enable signal.

[0083] Among them, the operations include: pause, execute, and comment.

[0084] Among them, during the verification process, assertion mis-triggering or missed triggering may occur. An assertion enable signal can be added to establish an effective debugging and maintenance mechanism, which is convenient for temporarily disabling certain assertions during the debugging process; detailed comments can be added to the assertions to explain their functions and verification purposes, facilitating subsequent maintenance and modification.

[0085] The clock reset verification method based on assertions provided by the embodiments of the present invention can cover a large area of possible circuit states and input signals, so as to achieve comprehensive, efficient, and accurate verification of clock signals and reset signals, thereby timely discovering potential problems in digital circuit design, improving the reliability and stability of digital circuits, and reducing the design cost and development cycle.

[0086] Embodiment 3

[0087] Corresponding to the above method embodiments, the embodiments of the present invention provide an assertion-based clock reset verification device, which is applied to digital circuits. Figure 3 As shown in the structural schematic diagram of an assertion-based clock reset verification device provided by the embodiments of the present invention, Figure 3 as shown, the assertion-based clock reset verification device may include:

[0088] An input signal acquisition module 301, configured to acquire input signals generated by an excitation source; the input signals include at least one of a clock signal and a reset signal.

[0089] An assertion execution order determination module 302, configured to determine an assertion execution order based on the input signals and a preset assertion priority.

[0090] A signal verification module 303, configured to perform signal verification on the input signals based on the assertion execution order and a preset assertion statement.

[0091] Among them, the assertion statements include: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

[0092] The assertion-based clock reset verification device provided by the embodiments of the present invention can acquire input signals generated by an excitation source, where the input signals include at least one of a clock signal and a reset signal, determine an assertion execution order based on the input signals and a preset assertion priority, and perform signal verification on the input signals based on the preset assertion statement according to the assertion execution order. Among them, the assertion statements include: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement. In this way, the requirements for efficient and accurate verification of clock signals and reset signals in modern complex digital circuits are met.

[0093] In some embodiments, the assertion execution order determination module is further configured to determine the parameters to be verified for the input signal; when the input signal is a clock signal, the parameters to be verified include at least one of the clock signal frequency, the clock signal duty cycle, and the clock signal jitter; when the input signal is a reset signal, the parameter to be verified includes one of the reset signal validity and the reset signal release; and an assertion execution order is obtained by sorting the parameters to be verified based on the assertion priority.

[0094] In some embodiments, the signal verification module is further configured to, if the assertion statement is a clock signal frequency assertion statement, determine whether the clock signal frequency meets a preset clock signal frequency range through the clock signal frequency assertion statement; if the assertion statement is a clock signal duty cycle assertion statement, determine the ratio of the high-level duration to the period of the clock signal through the clock signal duty cycle assertion statement; determine whether the ratio meets a preset clock signal duty cycle range; if the assertion statement is a clock signal jitter assertion statement, determine the adjacent cycle difference based on a plurality of consecutive clock cycles through the clock signal jitter assertion statement; and determine whether the adjacent cycle difference conforms to a preset maximum jitter value.

[0095] In some embodiments, the signal verification module is further configured to, if the assertion statement is a reset signal validity assertion statement, check whether a target node in the digital circuit is reset to an initial state when the reset signal is valid through the reset signal validity assertion statement; if the assertion statement is a reset signal release assertion statement, check whether the digital circuit resumes operation after the reset signal is released through the reset signal release assertion statement.

[0096] In some embodiments, the signal verification module is further configured to add an assertion enable signal; and operate on the assertion statement through the assertion enable signal, and the operations include: pause, execute, and annotate.

[0097] In some embodiments, the signal verification module is further configured to perform a coverage analysis on the signal verification to obtain an analysis result; and adjust the input signal or the assertion statement based on the analysis result.

[0098] In some embodiments, the signal verification module is further configured to monitor the execution status of the assertion statement in real time; and record information based on the execution status.

[0099] The device provided by the embodiments of the present invention has the same implementation principle and the same technical effects as those of the foregoing method embodiments. For the sake of brief description, for the parts not mentioned in the device embodiments, reference may be made to the corresponding contents in the foregoing method embodiments.

[0100] Embodiment 4

[0101] An embodiment of the present invention further provides an electronic device for running the above-mentioned assertion-based clock reset verification method; see Figure 4 The structural schematic diagram of an electronic device shown in FIG. The electronic device includes a memory 400 and a processor 401. Among them, the memory 400 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 401 to implement the above-mentioned assertion-based clock reset verification method.

[0102] Furthermore, Figure 4 The electronic device shown in FIG. further includes a bus 402 and a communication interface 403. The processor 401, the communication interface 403, and the memory 400 are connected through the bus 402.

[0103] Among them, the memory 400 may include a high-speed random access memory (RAM, Random Access Memory), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 403 (which can be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. can be used. The bus 402 can be an ISA bus, a PCI bus, an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity of representation, Figure 4 only a bidirectional arrow is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0104] The processor 401 may be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 401 or the instructions in the form of software. The above-mentioned processor 401 may be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it may also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), a field-programmable gate array (FPGA for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute each method, step and logic block diagram disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory 400, and the processor 401 reads the information in the memory 400 and combines its hardware to complete the steps of the method in the foregoing embodiments.

[0105] The embodiments of the present invention also provide a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned assertion-based clock reset verification method. For the specific implementation, reference can be made to the method embodiments, and details are not described herein again.

[0106] The computer program product for implementing the assertion-based clock reset verification method provided by the embodiments of the present invention includes a computer-readable storage medium storing non-volatile program code executable by a processor. The instructions included in the program code can be used to execute the method described in the foregoing method embodiments. For the specific implementation, reference can be made to the method embodiments, and details are not described herein again.

[0107] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments, and details are not described herein again.

[0108] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical, or other forms.

[0109] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0110] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0111] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs and other various media that can store program codes.

[0112] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any technician familiar with the technical field of the present invention can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An assertion-based clock reset verification method, characterized in that Applied to a digital circuit, the method includes: Obtaining an input signal generated by an excitation source; the input signal includes at least one of a clock signal and a reset signal; Determining an assertion execution order based on the input signal and a preset assertion priority; Performing signal verification on the input signal based on the preset assertion statements according to the assertion execution order; Wherein, the assertion statements include: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

2. The method according to claim 1, wherein The determining an assertion execution order based on the input signal and a preset assertion priority includes: Determining the parameters to be verified of the input signal; when the input signal is a clock signal, the parameters to be verified include at least one of a clock signal frequency, a clock signal duty cycle, and a clock signal jitter; when the input signal is a reset signal, the parameter to be verified includes one of a reset signal validity and a reset signal release; Performing assertion execution sorting on the parameters to be verified based on the assertion priority to obtain an assertion execution order.

3. The method according to claim 2, characterized in that, The performing signal verification on the input signal based on the preset assertion statements includes: If the assertion statement is a clock signal frequency assertion statement, determining whether the clock signal frequency meets a preset clock signal frequency range through the clock signal frequency assertion statement; If the assertion statement is a clock signal duty cycle assertion statement, determining the ratio of the high-level duration to the period of the clock signal through the clock signal duty cycle assertion statement; Determining whether the ratio meets a preset clock signal duty cycle range; If the assertion statement is a clock signal jitter assertion statement, determining the adjacent period difference based on consecutive clock cycles through the clock signal jitter assertion statement; Determining whether the adjacent period difference conforms to a preset maximum jitter value.

4. The method according to claim 2, wherein The performing signal verification on the input signal based on the preset assertion statements further includes: If the assertion statement is a reset signal validity assertion statement, checking whether a target node in the digital circuit is reset to an initial state when the reset signal is valid through the reset signal validity assertion statement; If the assertion statement is a reset signal release assertion statement, checking whether the digital circuit resumes operation after the reset signal is released through the reset signal release assertion statement.

5. The method according to claim 4, wherein After performing signal verification on the input signal based on the preset assertion statements according to the assertion execution order, the method further includes: Adding an assertion enable signal; Operating on the assertion statements through the assertion enable signal, and the operations include: pausing, executing, and annotating.

6. The method according to claim 1, wherein After performing signal verification on the input signal based on the preset assertion statements according to the assertion execution order, the method further includes: Performing coverage analysis on the signal verification to obtain an analysis result; Adjusting the input signal or the assertion statements based on the analysis result.

7. The method according to claim 1, characterized in that, While performing signal verification on the input signal based on a pre-set assertion statement according to the assertion execution order, the method further includes: Monitoring the execution status of the assertion statement in real time; Recording information based on the execution status.

8. An assertion-based clock reset verification device, characterized in that Applied to a digital circuit, the device includes: An input signal acquisition module, configured to acquire an input signal generated by an excitation source; the input signal includes at least one of a clock signal and a reset signal; An assertion execution order determination module, configured to determine an assertion execution order based on the input signal and a pre-set assertion priority; A signal verification module, configured to perform signal verification on the input signal based on the assertion execution order and a pre-set assertion statement; Wherein, the assertion statement includes: a clock signal frequency assertion statement, a clock signal duty cycle assertion statement, a clock signal jitter assertion statement, a reset signal validity assertion statement, and a reset signal release assertion statement.

9. An electronic device, characterized in that, Comprising a processor and a memory, the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the assertion-based clock reset verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the assertion-based clock reset verification method according to any one of claims 1 to 7.

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