Noise elimination circuit structure, low noise amplifier, chip and electronic equipment

Abstract

The invention discloses a noise elimination circuit structure, a low noise amplifier, a chip and electronic equipment. The noise elimination circuit structure comprises an input matching network; a common source stage amplification path connected with the first differential output end of the input matching network, comprising a first common source stage differential amplifier, and outputting an amplified first signal inverted from the radio frequency input signal to the ground; the common-gate amplification path is connected with the second differential output end of the input matching network, comprises a first common-gate differential amplifier and outputs an amplified second signal which is opposite to the radio frequency input signal to the ground; and the output end of the common-source amplification path and the output end of the common-gate amplification path are connected in parallel to form the output end of the noise elimination circuit structure. The common-source amplification path and the common-gate amplification path required by the noise elimination structure are realized by using one amplifier path, the utilization rate of the layout area is improved, the compactness of the layout is realized, and the amplifier can be widely applied to the field of communication or radar.

Description

Technical Field

[0001] The invention relates to the field of communication or radar, and in particular to a noise elimination circuit structure, a low noise amplifier, a chip and an electronic device. Background Art

[0002] The development of new energy vehicles and autonomous driving is in the ascendant, providing a broad development prospect for automotive radar. Currently, autonomous driving is divided into 6 levels (L0-L5). The higher the level, the higher the driving automation, and the higher the requirements for environmental detection. The current autonomous driving solutions are mainly divided into pure vision solutions and radar solutions, and the radar solutions are divided into laser radar and millimeter wave radar. Among them, millimeter wave radar itself has a higher resolution. Compared with other detection solutions, millimeter wave radar has a long detection distance and can meet all-weather detection scenarios. It is often used in automotive radar as a supplement to other detection solutions. The current operating frequency of automotive radar is 76-81GHz (77 / 79GHz band).

[0003] Traditional millimeter-wave radars are divided into long-range radar (LRR), medium-range radar (MRR) and short-range radar (SRR). In order to achieve a larger detection distance, the receiver needs a higher sensitivity; and the 77 / 79GHz band automotive radar has a higher allowed transmission power than the previous 24GHz band automotive radar, which means that the receiving end needs to withstand greater RF leakage from the transmitting end and requires higher linearity; and in order to meet the increasing detection and imaging requirements, the receiver is also required to have a better signal-to-noise ratio. Currently, the popular automotive radar is 4D millimeter-wave radar. 4D refers to the four dimensions of speed, distance, horizontal angle, and vertical height. The automotive radar is required to have the ability of multiple-receive and multiple-transmit (MIMO), which also means the expansion of chip area, equipment scale and the increase of manufacturing cost. Therefore, realizing a compact chip layout to achieve a smaller chip area has the significance of reducing equipment cost.

[0004] As the first stage in the receiver, the low noise amplifier (LNA) has a great impact on the receiver's signal-to-noise ratio, sensitivity, linearity and other performance. This also means that the LNA used in automotive radar requires high gain, low noise factor, high linearity and the smallest possible chip area. Currently, LNAs used in automotive radars mostly use multi-stage cascaded common-source amplifiers, which are difficult to achieve broadband input matching and require high power consumption to obtain good linearity. How to realize a small area, low noise, and high linearity low noise amplifier in the millimeter wave frequency band, especially in the 77 / 79GHz automotive radar band, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] To at least to some extent solve one of the technical problems existing in the prior art, the object of the present invention is to provide a noise cancellation circuit structure, a low-noise amplifier, a chip and an electronic device.

[0006] The first technical solution adopted by the present invention is:

[0007] A noise cancellation circuit structure, comprising:

[0008] An input matching network, configured to receive a radio frequency input signal and achieve impedance matching from the radio frequency input end to the common-source stage amplification path and the common-gate stage amplification path;

[0009] The common-source stage amplification path is connected to the first differential output end of the input matching network, and includes a first common-source stage differential amplifier, and outputs a first amplified signal that is inverted with respect to the radio frequency input signal to ground;

[0010] The common-gate stage amplification path is connected to the second differential output end of the input matching network, and includes a first common-gate stage differential amplifier, and outputs a second amplified signal that is inverted with respect to the radio frequency input signal to ground;

[0011] The output end of the common-source stage amplification path is connected in parallel with the output end of the common-gate stage amplification path to form the output end of the noise cancellation circuit structure.

[0012] Further, the input matching network includes a first inductor L1, a second inductor L2 and a third inductor L3, and any two of the first inductor L1, the second inductor L2 and the third inductor L3 are mutually coupled;

[0013] One end of the first inductor L1 is connected to the radio frequency input signal, and the other end is grounded; the center tap of the second inductor L2 is connected to the bias voltage V G1 , and both ends are used as the first differential output end of the input matching network; the center tap of the third inductor L3 is grounded, and both ends are used as the second differential output end of the input matching network;

[0014] The two amplification paths share the same chip area to achieve the compactness of the layout.

[0015] It should be noted that the input matching network is configured to receive a radio frequency input signal, input the radio frequency input signal into the common-source stage amplification path and the common-gate stage amplification path respectively, and achieve impedance matching. Specifically, various circuit structures can be used to implement it, and it is not limited to the above circuit structure. For example, a circuit structure with 4 inductors can also be used to implement it.

[0016] Further, the common-source amplification path further includes a first inter-stage matching network and a second common-source differential amplifier; the input end of the first common-source differential amplifier CS1 serves as the input end of the common-source amplification path, and the output end of the second common-source differential amplifier CS2 serves as the output end of the common-source amplification path; the first inter-stage matching network is disposed between the first common-source differential amplifier and the second common-source differential amplifier;

[0017] The first common-source differential amplifier includes a symmetrically arranged first transistor M1 and a second transistor M2; the second common-source differential amplifier includes a symmetrically arranged third transistor M3 and a fourth transistor M4;

[0018] The source electrodes of the first transistor M1 and the second transistor M2 are grounded in common, the gates form the differential input end of the first common-source differential amplifier, and the drains form the differential output end of the common-source differential amplifier;

[0019] The source electrodes of the third transistor M3 and the fourth transistor M4 are grounded in common, the gates form the differential input end of the second common-source differential amplifier, and the drains form the differential output end of the common-source differential amplifier.

[0020] It should be noted that the common-source amplification path adopts the result of a two-stage operational amplifier, and the first inter-stage matching network is used to achieve impedance matching between the two-stage operational amplifiers. However, it is not limited to this structure of the two-stage operational amplifier. For example, a single-stage operational amplifier structure including only the first common-source differential amplifier can also be adopted.

[0021] Further, the first common-source differential amplifier further includes a first neutralization capacitor C n1 and a second neutralization capacitor C n2 ; the second common-source differential amplifier further includes a third neutralization capacitor C n3 and a fourth neutralization capacitor C n4 ;

[0022] One end of the second neutralization capacitor C n2 is connected to the gate of the first transistor M1, and the other end is connected to the drain of the second transistor M2; one end of the first neutralization capacitor C n1 is connected to the gate of the second transistor M2, and the other end is connected to the drain of the first transistor M1;

[0023] One end of the fourth neutralization capacitor is connected to the gate of the third transistor, and the other end is connected to the drain of the fourth transistor; one end of the third neutralization capacitor is connected to the gate of the fourth transistor, and the other end is connected to the drain of the third transistor.

[0024] Further, the common-gate amplification path further includes a second inter-stage matching network and a third common-source differential amplifier CS3; the input end of the first common-gate differential amplifier CG1 serves as the input end of the common-gate amplification path, and the output end of the third common-source differential amplifier CS3 serves as the output end of the common-gate amplification path; the second inter-stage matching network is arranged between the first common-gate differential amplifier and the third common-source differential amplifier;

[0025] The first common-gate differential amplifier CG1 includes symmetrically arranged fifth transistor M5, sixth transistor M6, and symmetrically arranged eighth inductor L8, ninth inductor L9;

[0026] One end of the eighth inductor L8 is connected to the gate of the fifth transistor M5, and the other end is connected to the bias voltage V G3 ; one end of the ninth inductor L9 is connected to the gate of the sixth transistor M6, and the other end is connected to the bias voltage V G3 ;

[0027] The sources of the fifth transistor M5 and the sixth transistor M6 form the differential input end of the first common-gate differential amplifier CG1, and the drains form the differential output end of the first common-gate differential amplifier CG1;

[0028] The third common-source differential amplifier includes symmetrically arranged seventh transistor and eighth transistor;

[0029] The sources of the seventh transistor M7 and the eighth transistor M8 are grounded together, the gates form the differential input end of the second common-source differential amplifier, and the drains form the differential output end of the common-source differential amplifier.

[0030] It should be noted that the common-gate amplification path adopts the result of a two-stage operational amplifier, and the second inter-stage matching network is used to achieve impedance matching between the two-stage operational amplifiers. However, it is not limited to this structure of the two-stage operational amplifier. For example, a single-stage operational amplifier structure only including the first common-gate differential amplifier can also be adopted.

[0031] Further, the first common-gate differential amplifier CG1 further includes symmetrically arranged fifth neutralization capacitor C n5 , sixth neutralization capacitor C n6 ;

[0032] One end of the fifth neutralization capacitor C n5 is connected to the source of the fifth transistor M5, and the other end is connected to the drain of the sixth transistor M6; one end of the sixth neutralization capacitor C n6 is connected to the source of the sixth transistor M6, and the other end is connected to the drain of the fifth transistor M5;

[0033] The third common-source differential amplifier further includes a seventh neutralization capacitor C n7and the eighth neutralizing capacitor C n8 ;

[0034] One end of the seventh neutralizing capacitor is connected to the gate of the eighth transistor, and the other end is connected to the drain of the seventh transistor; one end of the eighth neutralizing capacitor is connected to the gate of the seventh transistor, and the other end is connected to the drain of the eighth transistor.

[0035] Further, the currents and voltages at the drain ends of the third transistor M3 and the seventh transistor M7 are in the same phase, and the drain end of the third transistor M3 is connected to the drain end of the seventh transistor M7;

[0036] The currents and voltages at the drain ends of the fourth transistor M4 and the eighth transistor M8 are in the same phase, and the drain end of the fourth transistor M4 is connected to the drain end of the eighth transistor M8.

[0037] Further, the first inter-stage matching network includes a fourth inductor L4 and a fifth inductor L5 that are mutually coupled, and the second inter-stage matching network includes a sixth inductor L6 and a seventh inductor L7 that are mutually coupled;

[0038] The transformer formed by the coupling of the fourth inductor L4 and the fifth inductor L5 is implemented as an 8-shaped transformer on the layout; the transformer formed by the coupling of the sixth inductor L6 and the seventh inductor L7 is implemented as a square transformer on the layout; the coupling coefficient between the square transformer and the 8-shaped transformer is close to zero.

[0039] The second technical solution adopted by the present invention is:

[0040] A high-linearity noise cancellation low-noise amplifier, comprising:

[0041] The noise cancellation circuit structure as described above;

[0042] A transconductance-enhanced common-gate amplifier structure, the input end of the transconductance-enhanced common-gate amplifier structure is connected to the output end of the noise cancellation circuit structure, and the output end of the transconductance-enhanced common-gate amplifier structure is connected to the radio frequency signal output.

[0043] Further, the transconductance-enhanced common-gate amplifier structure includes a third inter-stage matching network, a second common-gate differential amplifier CG2, and an output matching network;

[0044] The third inter-stage matching network includes a tenth inductor L 10 , an eleventh inductor L 11 and a twelfth inductor L 12 ; the second common-gate differential amplifier includes a ninth transistor M9 and a tenth transistor M 10 that are symmetrically arranged; the output matching network includes a thirteenth inductor L 13 and a fourteenth inductor L 14 ;

[0045] The center tap of the tenth inductor L 10 is connected to the power supply, and both ends are connected to the output terminals of the noise cancellation circuit structure; The center tap of the eleventh inductor L 11 is connected to the bias voltage V G5 , and both ends are respectively connected to the gates of the ninth transistor M9 and the tenth transistor M 10 ; The center tap of the twelfth inductor L 12 is grounded, and both ends are respectively connected to the sources of the ninth transistor M9 and the tenth transistor M 10 ;

[0046] The center tap of the thirteenth inductor L 13 is connected to the power supply, and both ends are respectively connected to the drains of the ninth transistor M9 and the tenth transistor M 10 ; One end of the fourteenth inductor L 14 is connected to the radio frequency output signal, and the other end is grounded; The thirteenth inductor L 13 is coupled with the fourteenth inductor L 14 .

[0047] Furthermore, any two of the tenth inductor L 10 , the eleventh inductor L 11 and the twelfth inductor L 12 in the third inter-stage matching network are mutually coupled; The sources of the ninth transistor M9 and the tenth transistor M 10 are respectively connected to the opposite-named end and the same-named end of the twelfth inductor L 12 , and the gates of the ninth transistor M9 and the tenth transistor M 10 are respectively connected to the same-named end and the opposite-named end of the eleventh inductor L 11 ;

[0048] The common-gate differential amplifier further includes symmetrically arranged ninth neutralizing capacitor C n9 and tenth neutralizing capacitor C n10 ; One end of the tenth neutralizing capacitor C n10 is connected to the gate of the ninth transistor M9, and the other end is connected to the drain of the tenth transistor M 10 ; One end of the ninth neutralizing capacitor C n9 is connected to the gate of the tenth transistor M 10 , and the other end is connected to the drain of the ninth transistor M9.

[0049] Furthermore, the twelfth inductor L 12 in the third inter-stage matching network is formed by paralleling more than 2 turns of inductors, and the tenth inductor L 10 and the eleventh inductor L 11 are both single-turn inductors.

[0050] The third technical solution adopted by the present invention is as follows:

[0051] A chip includes the noise cancellation circuit structure described above, or the high linearity noise cancellation low noise amplifier described above.

[0052] The fourth technical solution adopted by the present invention is as follows:

[0053] An electronic device includes a chip as described above.

[0054] The beneficial effects of the present invention are as follows: The noise cancellation circuit structure proposed by the present invention uses one amplifier path to implement the common source amplifier path and the common gate amplifier path required by the noise cancellation structure. Compared with the circuit implementation of the traditional noise cancellation structure that requires the area of two amplifier paths, it only requires half of its area, improving the utilization rate of the layout area and achieving the compactness of the layout. The high linearity noise cancellation low noise amplifier proposed by the present invention uses a transconductance enhanced common gate amplifier structure in the last stage, achieving an increase in amplifier gain and an improvement in linearity. Description of the Drawings

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following introduces the drawings related to the technical solutions in the embodiments of the present invention or the prior art. It should be understood that the drawings introduced below are only for conveniently and clearly expressing some embodiments of the technical solutions in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0056] Figure 1 is the block diagram of the high linearity noise cancellation low noise amplifier in Embodiment 1 of the present invention;

[0057] Figure 2 is the schematic diagram of the high linearity noise cancellation low noise amplifier in Embodiment 1 of the present invention;

[0058] Figure 3 is the schematic diagram of the decoupling transformer structure in Embodiment 1 of the present invention;

[0059] Figure 4 is the simulation result diagram of the coupling coefficient between the inductance coils of the decoupling transformer in Embodiment 1 of the present invention;

[0060] Figure 5 is the simulation result diagram of the S parameters of the high linearity noise cancellation low noise amplifier in Embodiment 1 of the present invention;

[0061] Figure 6 is the simulation result diagram of the noise figure of the high linearity noise cancellation low noise amplifier in Embodiment 1 of the present invention;

[0062] Figure 7 is the schematic diagram of the high linearity noise cancellation low noise amplifier according to Embodiment 2 of the present invention;

[0063] Figure 8 is the schematic diagram of the high linearity noise cancellation low noise amplifier according to Embodiment 3 of the present invention.

[0064] Reference numerals:

[0065] L1 - first inductor, L2 - second inductor, L3 - third inductor, L4 - fourth inductor, L5 - fifth inductor, L6 - sixth inductor, L7 - seventh inductor, L8 - eighth inductor, L9 - ninth inductor, L 10 - tenth inductor, L 11 - eleventh inductor, L 12 - twelfth inductor, L 13 - thirteenth inductor, L 14 - fourteenth inductor, L 15 - fifteenth inductor, L 16 - sixteenth inductor;

[0066] k in1 - coupling coefficient between L1 and L2, k in2 - coupling coefficient between L1 and L3, k in3 - coupling coefficient between L2 and L3, k a1 - coupling coefficient between L4 and L5, k a2 - coupling coefficient between L6 and L7, k a3 - coupling coefficient between L8, L9 and L 15 、L 16 ; k b1 - L 10 and L 11 ; k b2 - L 11 and L 12 ; k b3 - L 10 and L 12 ; k out - L 13 and L 14 ;

[0067] M1 - first transistor, M2 - second transistor, M3 - third transistor, M4 - fourth transistor, M5 - fifth transistor, M6 - sixth transistor, M7 - seventh transistor, M8 - eighth transistor, M9 - ninth transistor, M 10 - tenth transistor;

[0068] C1 - first capacitor, C2 - second capacitor, C n1 - first neutralization capacitor, Cn2 - The second neutralizing capacitor, C n3 - The third neutralizing capacitor, C n4 - The fourth neutralizing capacitor, C n5 - The fifth neutralizing capacitor, C n6 - The sixth neutralizing capacitor, C n7 - The seventh neutralizing capacitor, C n8 - The eighth neutralizing capacitor, C n9 - The ninth neutralizing capacitor, C n10 - The tenth neutralizing capacitor;

[0069] CS1 - The first common - source differential amplifier, CS2 - The second common - source differential amplifier, CS3 - The third common - source differential amplifier, CG1 - The first common - gate differential amplifier, CG2 - The second common - gate differential amplifier;

[0070] V G1 - The gate bias voltage of CS1, V G2 - The gate bias voltage of CS2, V G3 - The gate bias voltage of CG1, V G4 - The gate bias voltage of CS3, V G5 - The gate bias voltage of CG2. Detailed implementation manners

[0071] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present invention, and should not be construed as a limitation of the present invention. For the step numbers in the following embodiments, they are only set for the convenience of description and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0072] In the description of the present invention, it should be understood that the orientation or positional relationship referred to, such as up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0073] In the description of the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceeding", etc. are understood not to include the recited number, and "above", "below", "within", etc. are understood to include the recited number. If the first and second are described, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0074] In the description of the present invention, unless otherwise clearly defined, terms such as "arrangement", "installation", "connection", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0075] Embodiment 1

[0076] As Figure 1 shown, this embodiment provides a high-linearity noise cancellation low-noise amplifier, which includes a noise cancellation circuit structure and a transconductance-enhanced common-gate amplifier structure.

[0077] The input end of the noise cancellation circuit structure is connected to the RF input signal, and includes an input matching network, a common-source amplification path and a common-gate amplification path; the common-source amplification path includes a first common-source differential amplifier CS1, a first inter-stage matching network, and a second common-source differential amplifier CS2; the common-gate amplification path includes a first common-gate differential amplifier CG1, a second inter-stage matching network, and a third common-source differential amplifier CS3.

[0078] The output end of the transconductance-enhanced common-gate amplifier is connected to the RF output signal, and includes a third inter-stage matching, a second common-gate differential amplifier CG2, and an output matching network.

[0079] (1) Circuit structure description

[0080] As Figure 2 shown, Figure 2 is the circuit diagram of the high-linearity noise cancellation low-noise amplifier, and the specific circuit structure includes:

[0081] The first part is the noise cancellation circuit structure, which includes an input matching network, a common-source amplification path and a common-gate amplification path.

[0082] The input matching network includes inductors L1, L2, L3 and capacitor C1 to achieve impedance matching from the RF input end to the common-source amplification path and the common-gate amplification path; one end of capacitor C1 is connected to the RF input signal and the other end is grounded; one end of inductor L1 is connected to the RF input signal and the other end is grounded; the center tap of inductor L2 is connected to the bias voltage V G1, with its two ends respectively connected to the gates of transistors M1 and M2 in the common-source amplification path; the center tap of inductor L3 is grounded, and its two ends are respectively connected to the sources of transistors M5 and M6 in the common-gate amplification path; inductors L1 and L2 are reversely coupled, and the coupling coefficient is k in1 , inductor L1 and L3 are reversely coupled, and the coupling coefficient is k in2 , inductor L2 and L3 are forwardly coupled, and the coupling coefficient is k in3 .

[0083] The first common-source differential amplifier CS1 of the common-source stage amplification path includes transistors M1 and M2, and neutralization capacitors C n1 、C n2 , the two ends of neutralization capacitor C n1 are respectively connected to the gate of transistor M2 and the drain of transistor M1, and the two ends of neutralization capacitor C n2 are respectively connected to the gate of transistor M1 and the drain of transistor M2; the second common-source differential amplifier CS2 includes transistors M3 and M4, and neutralization capacitors C n1 、C n2 , the two ends of neutralization capacitor C n3 are respectively connected to the gate of transistor M4 and the drain of transistor M3, and the two ends of neutralization capacitor C n4 are respectively connected to the gate of transistor M3 and the drain of transistor M4; the sources of transistors M1, M2, M3, and M4 are commonly grounded; the first inter-stage matching network includes inductors L4 and L5, the center tap of inductor L4 is connected to the power supply, the center tap of inductor L5 is connected to the bias voltage V G2 , inductors L4 and L5 are forwardly coupled, and the coupling coefficient is k a1 , the two ends of inductor L4 are respectively connected to the drains of transistors M1 and M2, and the two ends of inductor L5 are respectively connected to the gates of transistors M3 and M4.

[0084] The first common-gate differential amplifier CG1 of the common-gate stage amplification path includes transistors M5 and M6, neutralization capacitors C n5 、C n6 , inductors L8 and L9, the two ends of neutralization capacitor C n5 are respectively connected to the source of transistor M5 and the drain of transistor M6, the two ends of neutralization capacitor C n6 are respectively connected to the source of transistor M6 and the drain of transistor M5, one ends of inductors L8 and L9 are respectively connected to the gates of transistors M5 and M6, and the other ends are connected to the bias voltage V G3 ; the third common-source differential amplifier CS3 includes transistors M7 and M8, neutralization capacitors C n7 、C n8 , the two ends of neutralization capacitor C n7 are respectively connected to the gate of transistor M8 and the drain of transistor M7, the two ends of neutralization capacitor C n8One end is respectively connected to the gate of transistor M7 and the drain of transistor M8, and the sources of transistors M7 and M8 are grounded together; the second inter-stage matching network includes inductors L6 and L7, and inductors L6 and L7 are reversely coupled with a coupling coefficient of k a2 ; the center tap of inductor L6 is connected to the power supply, and the two ends are respectively connected to the drains of transistors M5 and M6; the center tap of inductor L7 is connected to the bias voltage V G4 , and the two ends are respectively connected to the gates of transistors M7 and M8.

[0085] Preferably, the transformer formed by the coupling of inductors L4 and L5 in the first inter-stage matching network is implemented as an 8-shaped transformer on the layout; the transformer formed by the coupling of inductors L6 and L7 in the second inter-stage matching network is implemented as a square transformer on the layout; the part of the 8-shaped transformer except for the leads required to connect transistors M1 and M2 is surrounded by the square transformer, and the coupling coefficient between the square transformer and the 8-shaped transformer is close to zero.

[0086] The second part is a transconductance-enhanced common-gate stage amplifier structure, including a third inter-stage matching network, a second common-gate stage differential amplifier CG2, and an output matching network.

[0087] The second common-gate stage differential includes transistors M9, M 10 and neutralization capacitors C n9 , C n10 , and the neutralization capacitor C n9 has its two ends respectively connected to the gate of transistor M 10 and the drain of transistor M9, and the neutralization capacitor C n10 has its two ends respectively connected to the gate of transistor M9 and the drain of transistor M 10 .

[0088] The third inter-stage matching network includes inductors L 10 , L 11 and L 12 , inductor L 10 is forward-coupled with L 11 with a coupling coefficient of k b1 , inductor L 10 is reversely coupled with L 12 with a coupling coefficient of k b3 , inductor L 11 is reversely coupled with L 12 with a coupling coefficient of k b2 ; the center tap of inductor L 10 is connected to the power supply, one end is connected to the drains of transistors M3 and M7, and the other end is connected to the drains of transistors M4 and M8, realizing the merging of the signals of the common-source stage amplification path and the common-gate stage amplification path; the center tap of inductor L 11 is connected to the bias voltage V G5, the two ends are connected to transistors M9 and M 10 The gate of the inductor L 12 The center tap of is grounded, and the two ends are connected to transistors M9 and M 10 The source.

[0089] Preferably, the inductance L of the third inter-stage matching network of the transconductance enhanced common-gate amplifier structure is 12 It is composed of more than 2 coils of inductance connected in parallel, and the inductance L 10 , L 11 All are single-turn inductors.

[0090] The output matching network includes an inductor L 13 , L 14 and capacitor C2, inductor L 13 With L 14 Reverse coupling, the coupling coefficient is k out ; Inductance L 13 The center tap of the power supply is connected, and the two ends are connected to transistors M9 and M 10 The drain of 14 One end of capacitor C2 is grounded, and the other end is connected to the RF output.

[0091] (2) Circuit working principle description

[0092] A high linearity noise elimination low noise amplifier of this embodiment is as follows:

[0093] The noise elimination structure is composed of an input matching network, a common gate amplifier path and a common source amplifier path. As for noise, the noise current generated by the transistors M5 and M6 of the first common gate differential amplifier CG1 in the common gate amplifier path generates a noise voltage V at its source. noise0 , V noise0 Through the forward-coupled inductors L2 and L3 in the input matching network, the first common-source differential amplifier CS1, the forward-coupled inductors L4 and L5 in the first inter-stage matching network, and the second common-source differential amplifier CS2, the drain terminals of the transistors M3 and M4 finally obtain the source noise voltage V noise0 The amplified noise V noise1 At the same time, the noise current generated by transistors M5 and M6 will also generate a noise voltage V at their drains. noise2 , V noise2 and source noise voltage V noise0 The phase is inverted and the amplitude is times the gain of CG1, V noise2 Through the reverse-coupled inductors L6 and L7 in the second inter-stage matching network and the third common-source differential amplifier CS3, the drain terminals of transistors M7 and M8 finally obtain the same source noise voltage V noise0Inverted amplified noise V noise3 ; thus, V noise3 is inverted with respect to V noise1 . By connecting the drain terminals of transistors M3 and M4 to the drain terminals of transistors M7 and M8 respectively, the noise of transistors M5 and M6 is eliminated. For the RF input signal (V signal0 ), the signal V signal0 passes through the inductors L1 and L2, CS1 with inverse coupling in the input matching network, the inductors L4 and L5, CS2 with forward coupling in the first inter-stage matching network, and finally an amplified signal V signal1 inverted with respect to the RF input signal to ground is obtained at the drain terminals of transistors M3 and M4; while the signal V signal0 passes through the inductors L1 and L3, CG1 with inverse coupling in the input matching network, the inductors L6 and L7, CS3 with reverse coupling in the second inter-stage matching network, and finally an amplified signal V signal2 inverted with respect to the RF input signal to ground is obtained at the drain terminals of transistors M7 and M8; thus, V signal1 is in phase with respect to V signal2 . By connecting the drain terminals of transistors M3 and M4 to the drain terminals of transistors M7 and M8 respectively, the amplification of the RF input signal is achieved.

[0094] Since, under the condition of good input and output matching, the gain of the common-gate amplifier is smaller than that of the common-source amplifier with a passive degenerated inductor, the gates of transistors M5 and M6 of the first common-gate differential amplifier CG1 are respectively connected to inductors L8 and L9. Taking transistor M5 as an example, the source voltage is divided between the gate-source parasitic capacitance C GS5 of transistor M5 and L8, and the gate terminal obtains a voltage with a phase opposite to that of the source voltage through L8, thereby achieving an increase in the gain of CG1.

[0095] Furthermore, as an optional implementation manner, to reduce the area occupied by the chip layout, the present invention uses two decoupled transformers to implement the first inter-stage matching network and the second inter-stage matching network. The specific layout is as shown in Figure 3As shown, where the ports ①②⑤⑥ are respectively connected to the drains of transistors M5, M6, M1, and M2, and the ports ③④⑦⑧ are respectively connected to the gates of transistors M7, M8, M3, and M4; the port ① is connected to the drain of transistor M5. The inductors L4 and L5 in the first inter-stage matching network are implemented as two coupled figure-eight inductors. According to the current direction, it can be determined that the signals of the differential port formed by ⑤⑥ are in phase with the signals of the differential port formed by ⑦⑧, that is, the inductors L4 and L5 are forward-coupled; the inductors L6 and L7 in the second inter-stage matching network are implemented as two coupled square inductors. According to the current direction, it can be determined that the signals of the differential port formed by ①② are out of phase with the signals of the differential port formed by ③④, that is, the inductors L6 and L7 are reverse-coupled; at the same time, the current directions of the figure-eight inductors in region Ⅰ and region Ⅱ are opposite, generating opposite magnetic fluxes in the region surrounded by the square inductor, thereby canceling the magnetic coupling between the figure-eight inductor and the square inductor, achieving the decoupling effect between the transformer formed by inductors L4 and L5 and the transformer formed by inductors L6 and L7, and realizing two transformers on the area occupied by one transformer.

[0096] The transconductance-enhanced common-gate amplifier structure is composed of a third inter-stage matching network, a second common-gate differential amplifier CG2, and an output matching network. Since the inductor L 10 connected to the output of the previous stage in the third inter-stage matching network is forward-coupled with the inductor L 11 connected to the gate of CG2, and is reverse-coupled with the inductor L 12 connected to the source of CG2, and the inductor L 11 connected to the gate of CG2 is reverse-coupled with the inductor L 12 connected to the source of CG2, the signals obtained at the gate and source of CG2 have opposite phases, realizing transconductance enhancement; and the common-gate amplifier has better linearity than the common-source amplifier, and good linearity can also be obtained through the above transconductance-enhanced common-gate amplifier structure.

[0097] In addition, any differential amplifier in the above noise cancellation structure and transconductance-enhanced common-gate amplifier structure adopts a neutralization capacitor structure, which can effectively improve the isolation between the input end and the output end, improve the stability of the amplifier, and improve the gain to a certain extent.

[0098] (3) Experimental results

[0099] The high-linearity noise cancellation low-noise amplifier LNA of Embodiment 1 of the present invention is used in automotive radars in the 77 / 79 GHz band. After simulation, the coupling coefficient between each square inductor and each figure-eight inductor in the decoupling transformer is as Figure 4 shown. It can be seen that within 70 - 90 GHz, the coupling coefficient between each square inductor and each figure-eight inductor is below 0.12; the S-parameter simulation results are as Figure 5As shown, the 3dB bandwidth of the LNA is 76.5 - 85.5GHz, the highest gain within the band is 22.35dB, the frequency corresponding to the peak gain is 80.5GHz, and within 70 - 90GHz, S 11 <-10dB, and within 73 - 85GHz, S 22 <-10dB, indicating that the input and output matching of the LNA is good; the noise figure simulation of the LNA is as Figure 6 shown. The noise figure within 76 - 90GHz is 5.18 - 6dB; the input 1dB compression point IP of the LNA at 79GHz 1dB is -14.93dBm; the total power consumption of the LNA is 49.15mW, and the core area of the layout is 0.06mm 2 .

[0100] Example 2

[0101] As Figure 7 shown, on the basis of Example 1, the coupling directions of the inductors L4 and L5 in the first inter-stage matching network are changed to reverse coupling, the drain of the transistor M3 in CS2 is changed to be connected to the transistor M8 in CS3, the drain of the transistor M4 in CS2 is changed to be connected to the transistor M7 in CS3, and both the first inter-stage matching network and the second inter-stage matching network are composed of square transformers. In this example, the decoupling square transformer and the figure-eight transformer in Example 1 are not used. Therefore, the inductor can obtain a higher quality factor Q value, which is beneficial to obtaining better gain, noise figure, and linearity. However, it requires occupying the layout area of two transformers. At the same time, on the layout, the positions of the transistors M3, M4 and the transistors M7, M8 are far apart, the drain connection wires of the transistors are long, introducing additional losses, resulting in a decline in the performance of the LNA, and it is also not conducive to the third inter-stage matching network to complete the inter-stage matching from the noise cancellation circuit structure to the transconductance-enhanced common-gate amplifier structure.

[0102] Example 3

[0103] As Figure 8 shown, on the basis of Example 1, one end of the inductors L 15 , L 16 is respectively connected to the sources of the transistors M1 and M2 in CS1, the other ends of the inductors L 15 , L 16 are grounded together, and the inductors L 15 , L 16 are respectively and positively coupled to the gates of the transistors M5 and M6 in CG1 through the inductors L8 and L9, and the coupling coefficient is k a3, in this embodiment, the noise voltages at the source ends of transistors M1 and M2 of CS1 after being amplified by the common-gate amplification path are out of phase with the noise voltages at the drain ends of transistors M1 and M2 of CS1 after being amplified by the common-source amplification path, achieving the elimination of the noise generated by transistors M1 and M2 of CS1. Combining with the noise elimination of transistors M5 and M6 of CG1 in Embodiment 1, a dual-path noise elimination structure is achieved, further reducing the noise figure of the LNA. However, inductors L 15 and L 16 are respectively connected to the source electrodes of transistors M1 and M2 of CS1, which actually constitutes source negative feedback, reducing the gain of the LNA. At the same time, the introduction of additional inductors L 15 and L 16 will also introduce additional noise and require a larger chip area.

[0104] In summary, the present invention proposes a high-linearity noise cancellation low-noise amplifier, including a noise cancellation circuit structure and a transconductance-enhanced common-gate amplifier structure. The noise cancellation circuit structure includes a common-source amplification path and a common-gate amplification path. Compared with the traditional noise cancellation structure that occupies the area of two amplifier paths, the present invention uses a decoupled transformer matching network to implement the two amplifier paths of the noise cancellation circuit structure on the area of one amplifier path, achieving the compactness of the layout. The transconductance-enhanced common-gate amplifier structure adopted in the last stage improves the gain and linearity. The present invention realizes broadband input matching, low noise figure, high gain and high linearity by using the noise cancellation circuit structure and the transconductance-enhanced common-gate amplifier structure.

[0105] In the above description of this specification, the description with reference to terms such as "one embodiment / implementation", "another embodiment / implementation" or "certain embodiments / implementations" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0106] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purposes of the present invention. The scope of the present invention is defined by the claims and their equivalents.

[0107] The above is a specific description of the preferred embodiment of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A noise cancellation circuit structure, characterized in that, Comprising: An input matching network for receiving a radio frequency input signal and achieving impedance matching from the radio frequency input end to the common-source amplification path and the common-gate amplification path; A common-source amplification path connected to the first differential output end of the input matching network, including a first common-source differential amplifier, and outputting an amplified first signal that is inverted with respect to the radio frequency input signal to ground; A common-gate amplification path connected to the second differential output end of the input matching network, including a first common-gate differential amplifier, and outputting an amplified second signal that is inverted with respect to the radio frequency input signal to ground; The output end of the common-source amplification path is connected in parallel with the output end of the common-gate amplification path to form the output end of the noise cancellation circuit structure.

2. A noise cancellation circuit structure according to claim 1, wherein The input matching network includes a first inductor, a second inductor, and a third inductor, and any two of the first inductor, the second inductor, and the third inductor are mutually coupled; One end of the first inductor is connected to the RF input signal, and the other end is grounded; the center tap of the second inductor is connected to the bias voltage V G1 , and both ends are used as the first differential output terminal of the input matching network; the center tap of the third inductor is grounded, and both ends are used as the second differential output terminal of the input matching network; The two amplification paths share the same chip area to achieve layout compactness.

3. A noise cancellation circuit structure according to claim 1, characterized in that, The common-source amplification path further includes a first inter-stage matching network and a second common-source differential amplifier; the input end of the first common-source differential amplifier serves as the input end of the common-source amplification path, and the output end of the second common-source differential amplifier serves as the output end of the common-source amplification path; the first inter-stage matching network is disposed between the first common-source differential amplifier and the second common-source differential amplifier; The first common-source differential amplifier includes a first transistor and a second transistor symmetrically arranged; the second common-source differential amplifier includes a third transistor and a fourth transistor symmetrically arranged; The sources of the first transistor and the second transistor are commonly grounded, the gates form the differential input end of the first common-source differential amplifier, and the drains form the differential output end of the common-source differential amplifier; The sources of the third transistor and the fourth transistor are commonly grounded, the gates form the differential input end of the second common-source differential amplifier, and the drains form the differential output end of the common-source differential amplifier.

4. A noise cancellation circuit structure according to claim 3, characterized in that, The first common-source differential amplifier further includes a first neutralization capacitor and a second neutralization capacitor; the second common-source differential amplifier further includes a third neutralization capacitor and a fourth neutralization capacitor; One end of the second neutralization capacitor is connected to the gate of the first transistor, and the other end is connected to the drain of the second transistor; one end of the first neutralization capacitor is connected to the gate of the second transistor, and the other end is connected to the drain of the first transistor; One end of the fourth neutralization capacitor is connected to the gate of the third transistor, and the other end is connected to the drain of the fourth transistor; one end of the third neutralization capacitor is connected to the gate of the fourth transistor, and the other end is connected to the drain of the third transistor.

5. A noise cancellation circuit structure according to claim 1, characterized in that, The common-gate amplification path further includes a second inter-stage matching network and a third common-source differential amplifier; the input end of the first common-gate differential amplifier serves as the input end of the common-gate amplification path, and the output end of the third common-source differential amplifier serves as the output end of the common-gate amplification path; the second inter-stage matching network is disposed between the first common-gate differential amplifier and the third common-source differential amplifier; The first common-gate differential amplifier includes a fifth transistor, a sixth transistor symmetrically arranged, and an eighth inductor, a ninth inductor symmetrically arranged; One end of the eighth inductor is connected to the gate of the fifth transistor, and the other end is connected to the bias voltage V G3 , one end of the ninth inductor is connected to the gate of the sixth transistor, and the other end is connected to the bias voltage V G3 ; The sources of the fifth transistor and the sixth transistor form the differential input terminals of the first common-gate stage differential amplifier, and the drains form the differential output terminals of the first common-gate stage differential amplifier; The third common-source stage differential amplifier includes a seventh transistor and an eighth transistor which are symmetrically arranged; The sources of the seventh transistor and the eighth transistor are grounded in common, the gates form the differential input terminals of the second common-source stage differential amplifier, and the drains form the differential output terminals of the common-source stage differential amplifier.

6. A noise cancellation circuit structure according to claim 5, characterized in that, The first common-gate stage differential amplifier further includes a fifth neutralization capacitor and a sixth neutralization capacitor which are symmetrically arranged; One end of the fifth neutralization capacitor is connected to the source of the fifth transistor, and the other end is connected to the drain of the sixth transistor; one end of the sixth neutralization capacitor is connected to the source of the sixth transistor, and the other end is connected to the drain of the fifth transistor; The third common-source stage differential amplifier further includes a seventh neutralization capacitor and an eighth neutralization capacitor; One end of the seventh neutralization capacitor is connected to the gate of the eighth transistor, and the other end is connected to the drain of the seventh transistor; one end of the eighth neutralization capacitor is connected to the gate of the seventh transistor, and the other end is connected to the drain of the eighth transistor.

7. A noise cancellation circuit structure according to claim 5, characterized in that The first inter-stage matching network includes a fourth inductor and a fifth inductor which are mutually coupled, and the second inter-stage matching network includes a sixth inductor and a seventh inductor which are mutually coupled; the transformer formed by the coupling of the fourth inductor and the fifth inductor is implemented as an 8-shaped transformer in the layout; the transformer formed by the coupling of the sixth inductor and the seventh inductor is implemented as a square transformer in the layout.

8. A high-linearity noise cancellation low-noise amplifier, characterized in that, Comprising: The noise cancellation circuit structure according to any one of claims 1-7; A transconductance-enhanced common-gate stage amplifier structure, the input terminal of the transconductance-enhanced common-gate stage amplifier structure is connected to the output terminal of the noise cancellation circuit structure, and the output terminal of the transconductance-enhanced common-gate stage amplifier structure is connected to the radio frequency signal output.

9. The high-linearity noise cancellation low-noise amplifier according to claim 8, characterized in that The transconductance-enhanced common-gate stage amplifier structure includes a third inter-stage matching network, a second common-gate stage differential amplifier, and an output matching network; the third inter-stage matching network includes a tenth inductor, an eleventh inductor, and a twelfth inductor; the second common-gate stage differential amplifier includes a ninth transistor and a tenth transistor which are symmetrically arranged; the output matching network includes a thirteenth inductor and a fourteenth inductor; The center tap of the tenth inductor is connected to the power supply, and both ends are connected to the output end of the noise cancellation circuit structure; the center tap of the eleventh inductor is connected to the bias voltage V G5 , and both ends are respectively connected to the gates of the ninth transistor and the tenth transistor; the center tap of the twelfth inductor is grounded, and both ends are respectively connected to the sources of the ninth transistor and the tenth transistor; The center tap of the thirteenth inductor is connected to the power supply, and the two ends are respectively connected to the drains of the ninth transistor and the tenth transistor; one end of the fourteenth inductor is connected to the radio frequency output signal, and the other end is grounded; the thirteenth inductor and the fourteenth inductor are coupled.

10. A high linearity noise cancellation low noise amplifier according to claim 9, characterized in that, Any two of the tenth inductor, the eleventh inductor, and the twelfth inductor in the third inter-stage matching network are mutually coupled; the sources of the ninth transistor and the tenth transistor are respectively connected to the opposite-named end and the same-named end of the twelfth inductor, and the gates of the ninth transistor and the tenth transistor are respectively connected to the same-named end and the opposite-named end of the eleventh inductor; The common-gate stage differential amplifier further includes a ninth neutralization capacitor and a tenth neutralization capacitor which are symmetrically arranged; one end of the tenth neutralization capacitor is connected to the gate of the ninth transistor, and the other end is connected to the drain of the tenth transistor; one end of the ninth neutralization capacitor is connected to the gate of the tenth transistor, and the other end is connected to the drain of the ninth transistor.

11. A high linearity noise cancellation low noise amplifier according to claim 9, characterized in that, The twelfth inductor of the third-stage inter-stage matching network is formed by paralleling more than 2 turns of inductors, and the tenth inductor and the eleventh inductor are both single-turn inductors.

12. A chip, characterized in that, It includes the noise cancellation circuit structure according to any one of claims 1-7, or the high-linearity noise cancellation low-noise amplifier according to any one of claims 8-11.

13. An electronic device, characterized in that, It includes a chip according to claim 12.

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