Three-inductor stray capacitance counteracting network, broadband power amplifier, chip and equipment

Abstract

The invention discloses a three-inductor stray capacitance counteracting network, a broadband power amplifier, a chip and equipment, and the three-inductor stray capacitance counteracting network is arranged at an intermediate node of a differential stacked transistor and is used for eliminating the influence of the equivalent stray capacitance of the differential stacked transistor; comprising a first inductor, a second inductor and a third inductor, the first inductor and the second inductor are matched and are respectively connected in series between the output end of the upper-layer transistor and the input end of the lower-layer transistor, and two ends of the third inductor are respectively connected to the output end of the upper-layer transistor or the input end of the lower-layer transistor. According to the three-inductor parasitic cancellation technology provided by the invention, the output power, the efficiency and the bandwidth of the power amplifier of the wireless communication system are effectively improved by increasing the impedance from a signal path to the ground, reducing the signal loss and eliminating the influence caused by the parasitic capacitance of the transistor at an intermediate node of the differential stacked transistor. The method can be widely applied to the field of radio frequency integrated circuit design.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency integrated circuit design, and in particular, to a three-inductor parasitic capacitance cancellation network, a broadband power amplifier, a chip, and a device. Background Art

[0002] With the rapid development of mobile communication technology, the phased leap from 4G real-time high-definition video calls to the 5G era of Internet of Everything has now been achieved. Compared with 4G wireless enhanced mobile broadband (eMBB), the fifth-generation (5G) communication has achieved a 10-100× increase in data rate. Therefore, wireless communication transceivers need to provide a larger bandwidth to accommodate the increasing data capacity and meet people's requirements for the speed and reliability of communication devices.

[0003] A power amplifier (PA) is a key component in a wireless communication system, located at the end of a radio frequency transmitter, and is responsible for amplifying the modulated signal to a sufficient power level for effective transmission through an antenna. Its performance directly affects the transmission distance, coverage range, and communication quality of the signal. The main function of the power amplifier is to amplify the signal from the previous-stage circuit with high power to ensure that the signal can overcome path loss and interference and is finally correctly received by the receiving end. At the same time, the power amplifier needs to minimize signal distortion during the amplification process and maintain high efficiency. The main indicators of the power amplifier include gain, output power, efficiency, linearity, bandwidth, and stability, etc.

[0004] With the rapid development of 5G communication technology, millimeter-wave frequency bands (such as U-band and V-band) have become a research hotspot due to their wide bandwidth and high data rate. However, millimeter-wave power amplifiers face the following challenges in design: 1) Parasitic capacitance: At high frequency bands, the parasitic capacitance of transistors will significantly reduce the bandwidth and efficiency of the power amplifier. 2) Insertion loss: The insertion loss of traditional output matching networks is large, which limits the output power and efficiency of the power amplifier. 3) Broadband performance: It is difficult for existing technologies to achieve high output power and high efficiency simultaneously within a wide frequency band.

[0005] Currently, common solutions include using complex matching networks or multi-stage amplifier structures, but these methods often increase the design complexity and chip area, and it is difficult to optimize bandwidth, output power, and efficiency simultaneously. Summary of the Invention

[0006] To solve at least one of the technical problems existing in the prior art to a certain extent, an object of the present invention is to provide a three-inductor parasitic capacitance cancellation network, a broadband power amplifier, a chip, and a device.

[0007] The first technical solution adopted by the present invention is:

[0008] A three - inductor parasitic capacitance cancellation network is applied to a differential multi - layer stacked transistor structure, and is set at the intermediate node of the differential stacked transistors to eliminate the influence of the equivalent parasitic capacitance of the differential - circuit transistors.

[0009] The three - inductor parasitic capacitance cancellation network includes a first inductor, a second inductor, and a third inductor. The first inductor and the second inductor are matched and are respectively connected in series between the output terminal of the upper - layer transistor and the input terminal of the lower - layer transistor. The two ends of the third inductor are respectively connected to the output terminal of the upper - layer transistor or the input terminal of the lower - layer transistor.

[0010] Further, the differential multi - layer stacked transistor structure is a differential two - layer stacked transistor structure.

[0011] The differential signal is input to the gates of the common - source transistors M p2 and M n2 . After being amplified, the differential signal is output from the drains of the transistors M p2 and M n2 . Through the three - inductor parasitic capacitance cancellation network, it is input to the sources of the common - gate transistors M p3 and M n3 . After being amplified by the common - gate transistors M p3 and M n3 , the differential signal is output from the drains of the common - gate transistors M p3 and M n3 .

[0012] The two ends of the first inductor are connected between the drain of the common - source transistor M p2 and the source of the common - gate transistor M p3 . The two ends of the second inductor are connected between the drain of the common - source transistor M n2 and the source of the common - gate transistor M n3 . The two ends of the third inductor are connected between the drain of the common - source transistor M p2 and the drain of the common - source transistor M p2 , or are connected between the source of the common - gate transistor M p3 and the source of the common - gate transistor M n3 .

[0013] Further, the differential multi - layer stacked transistor structure is a differential three - layer stacked transistor structure.

[0014] The three - inductor parasitic capacitance cancellation network is set between the output terminal of the second - layer transistor and the input terminal of the third - layer transistor.

[0015] Further, the differential multi - layer stacked transistor structure is a differential three - layer stacked transistor structure.

[0016] The number of the three - inductor parasitic - capacitance cancellation networks is two. The first three - inductor parasitic - capacitance cancellation network is disposed between the output terminal of the first - layer transistor and the input terminal of the second - layer transistor, and the second three - inductor parasitic - capacitance cancellation network is disposed between the output terminal of the second - layer transistor and the input terminal of the third - layer transistor.

[0017] The second technical solution adopted by the present invention is:

[0018] A broadband power amplifier includes the three - inductor parasitic - capacitance cancellation network as described above.

[0019] Further, the broadband power amplifier includes a first circuit and a second circuit with the same and symmetric circuit structures; an input signal is divided into two signals through a power - distribution network and respectively input into the first circuit and the second circuit; after being amplified, the input signals are power - combined by a power - combination network to improve the gain and output power of the circuit.

[0020] Further, the first circuit includes:

[0021] A driver - stage circuit, whose input terminal is connected to the power - distribution network through an input - matching network, adopts a differential common - source amplification structure, and is used to provide sufficient gain for the circuit;

[0022] A power - stage circuit, whose input terminal is connected to the output terminal of the driver - stage circuit through an inter - stage matching network, is composed of a differential double - stacked structure, and is used to provide sufficient output power for the circuit; the three - inductor parasitic - capacitance cancellation network is disposed on the differential double - stacked structure; the output terminal of the power - stage circuit is connected to the power - combination network through an output - matching network;

[0023] The input - matching network, the inter - stage matching network, and the output - matching network are all implemented by transformers.

[0024] Further, the power - distribution network and the power - combination network are both implemented by transmission lines.

[0025] The third technical solution adopted by the present invention is:

[0026] A chip includes the three - inductor parasitic - capacitance cancellation network as described above, or the broadband power amplifier as described above.

[0027] The fourth technical solution adopted by the present invention is:

[0028] An electronic device includes the chip as described above.

[0029] The beneficial effects of the present invention are as follows: The three-inductor parasitic cancellation technology proposed by the present invention increases the impedance from the signal path to the ground and reduces signal loss, eliminates the influence of transistor parasitic capacitance at the intermediate node of the differential stacked transistors, and effectively improves the output power, efficiency, and bandwidth of the power amplifier in the wireless communication system. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following introduces the accompanying drawings related to the technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings introduced below are only for conveniently and clearly expressing some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 is the schematic diagram of the parasitic cancellation network in the embodiment of the present invention;

[0032] Figure 2 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 1 of the present invention;

[0033] Figure 3 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 2 of the present invention;

[0034] Figure 4 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 3 of the present invention;

[0035] Figure 5 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 4 of the present invention;

[0036] Figure 6 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 5 of the present invention;

[0037] Figure 7 is the circuit diagram of the three-inductor parasitic capacitance cancellation network provided in Embodiment 6 of the present invention;

[0038] Figure 8 is the circuit diagram of the broadband power amplifier provided in Embodiment 7 of the present invention;

[0039] Figure 9 is the schematic diagram of the S-parameter performance of the amplifier circuit provided in Embodiment 7 of the present invention;

[0040] Figure 10 is the schematic diagram of the large-signal parameter performance of the amplifier circuit provided in Embodiment 7 of the present invention. Detailed Embodiments

[0041] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and should not be construed as a limitation to the present application. For the step numbers in the following embodiments, they are only set for the convenience of explanation, and no limitation is imposed on the order between steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0042] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. In addition, unless otherwise clearly defined, terms such as "set", "installed", "connected", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0043] In the description of the present application, it should be understood that with respect to the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0044] In the description of the present application, "several" means one or more, "multiple" means two or more, "greater than", "less than", "exceeding", etc. are understood as not including the recited number, and "above", "below", "within", etc. are understood as including the recited number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0045] In the description of the present application, "and / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0046] In a millimeter-wave communication system, there are two reasons for the limited output power of the power amplifier. On the one hand, the higher the millimeter-wave frequency, the closer it is to the cut-off frequency of the transistor, resulting in a decrease in the transconductance of the transistor, which in turn affects the gain of the circuit. On the other hand, as the frequency increases, many parasitics that do not need to be considered at low frequencies become non-negligible, bringing additional losses and further reducing the output power, efficiency, and bandwidth. Currently, the commonly used technical methods to improve the output power of the power amplifier include using a stacked structure, power combining, and active load modulation, which achieve an increase in output power by increasing the output voltage of the power amplifier, increasing the output current of the power amplifier, and regulating the voltage and current through load modulation, respectively.

[0047] With the progress of the process node, the nominal supply voltage of the transistor decreases, resulting in a limited output swing of the power amplifier and thus a limited output power. A common solution is to use a stacked transistor structure to increase the supply voltage of the power amplifier. The first prior art solution proposes a single-ended triple-stack power amplifier based on a 45nm CMOS SOI process, and at the intermediate node, a series inductor resonates with the parasitic capacitance between the transistor gate and source to reduce the loss of the RF signal, thereby increasing the output power and efficiency of the power amplifier. This circuit is powered by a voltage of 4V and can achieve a saturated output power of 19dBm and a peak power-added efficiency of 22% at 45GHz. The second prior art solution also realizes a single-ended double-stack power amplifier based on a 45nm CMOS SOI process, and at the intermediate node, a parallel transmission line is used to achieve the matching of the internal nodes of the transistor, increasing the power-added efficiency (PAE) by more than 6%. This structure uses a supply voltage of 2.7V at 45GHz to achieve an output power of 19.4dBm, and at the same time, the PAE remains above 30% from 42GHz to 45GHz. The third prior art solution is based on a 90nm CMOS process and designs a differential double-stack PA unit. Two series inductors and a parallel capacitor are used inside the unit to match the internal nodes. At 53GHz, it uses a supply voltage of 2.4V to achieve a saturated output power of 22.4dBm and a peak power-added efficiency of 19.1%. The fourth prior art solution designs a differential triple-stack structure based on a 65nm CMOS process, uses neutralization capacitors to achieve the matching of internal nodes, and has a supply voltage of 3.3V, which can achieve a saturated output power of 24.7dBm and a peak power-added efficiency of 30.3% at 22GHz.

[0048] However, these technical solutions still have the following problems: First, both the first and fourth prior art solutions adopt a three-stack structure, with supply voltages of 4V and 3.3V respectively. The excessively high supply voltage requires high process requirements and is prone to causing too large a voltage difference between adjacent ports of the transistor, reducing the lifespan of the transistor and even causing irreversible effects such as breakdown. Second, the matching network of the prior art solution only includes transmission lines, occupying a large area, and distribution parameter effects (such as parasitic capacitance and inductance) need to be considered, being sensitive to process parameters and having great design difficulty in the millimeter-wave frequency band. Third, the prior art solution uses two series inductors and a parallel capacitor for internal node matching of a differential double-stack power amplifier, with high design complexity, and the parallel capacitor exacerbates the influence of the transistor parasitic capacitance to a certain extent, resulting in performance deterioration at some frequency points. In addition, the internal node matching methods used in these four technical solutions are only narrow-band matching, which can only achieve high output power and efficiency at specific frequency points, but it is difficult to achieve broadband matching, greatly limiting the operating frequency and bandwidth of the circuit.

[0049] Based on this, the present invention provides a three-inductor parasitic capacitance cancellation technology for improving the output power, efficiency, and bandwidth of a power amplifier in a wireless communication system; since the main influence of the parasitic capacitance is to provide a low-impedance path to ground for millimeter-wave signals, resulting in signal leakage and thus deteriorating the output power and efficiency, the core of this technology is to suppress the leakage of radio frequency signals by designing a three-inductor parasitic cancellation network. Further based on this three-inductor parasitic capacitance cancellation technology, the present invention also provides a broadband power amplifier to achieve broadband output matching and broadband power signal amplification in the millimeter-wave frequency band.

[0050] As Figure 1 shown, the three-inductor parasitic cancellation technology of the present invention can eliminate the influence of transistor parasitic capacitance at the intermediate node of the differential stack transistors by increasing the impedance from the signal path to ground and reducing signal loss. Figure 1 is a schematic diagram of the three-inductor parasitic cancellation technology, and a bias circuit, a matching circuit, and related circuits for optimizing other performances need to be added to the actual circuit.

[0051] 1) Circuit structure: The differential signals output from the previous stage are input to the gates of the common-source transistors (M p2 and M n2 ) through the matching network. The differential signals input from the gates flow into the drains of M p2 and M n2 after being amplified by the transistors; then they are input to the sources of the common-gate transistors (M p3 and M n3 ) through the parasitic cancellation network. After being amplified by the common-gate transistors, the differential signals are output at the drains of M p3 and M n3 .

[0052] The three - inductor parasitic cancellation network is used to cancel the equivalent parasitic capacitances (C p2 and M n2 ) of the common - source transistors (M p1 ) and the equivalent parasitic capacitances (C p3 and M n3 ) of the common - gate transistors (M p2 ).

[0053] 2) Circuit principle: The main function of this technical solution is to efficiently amplify the input signal in a wide - band frequency range by eliminating the influence of the equivalent parasitic capacitances of the differential - circuit transistors.

[0054] As Figure 1 shown, taking the differential two - layer stacked transistor structure as an example, C p1 and C p2 can be regarded as the equivalent parasitic capacitances at the intermediate nodes of the connections of the common - source transistors (M p2 and M n2 ) and the common - gate transistors (M p3 and M n3 ). Without the parasitic cancellation network, the two parasitic capacitances C p1 and C p2 are in parallel, forming a low - impedance path for the millimeter - wave signal, resulting in signal leakage to the ground and reducing the output power and efficiency of the circuit. After adding the parasitic cancellation network, the grounding paths of the two parasitic capacitances can be designed as high - impedance paths for millimeter - waves to suppress the leakage of millimeter - wave signals; in addition, by reasonably designing the parasitic cancellation network, additional left - half - plane zeros can be introduced and the frequency of the dominant pole can be reduced, thereby achieving the effect of enhancing the bandwidth.

[0055] Compared with the existing technical solutions, the present invention cancels the parasitic capacitances at the intermediate nodes of the stacked transistor connections, realizing high output power and high efficiency while expanding the bandwidth of the circuit.

[0056] Embodiment 1

[0057] Refer to Figure 2 , in this embodiment, a differential two - layer stacked transistor structure is adopted, and three inductors are arranged at the intermediate nodes of the differential stacked transistors to eliminate the influence brought by the transistor parasitic capacitances. Specifically, the first inductor Ls is connected in series between the drain of the transistor M p2 and the source of the transistor M p3 , the second inductor Ls is connected in series between the drain of the transistor M n2 and the source of the transistor M n3 , and both ends of the third inductor Lp are respectively connected between the drains of the transistors M p2 and M n2 .

[0058] Example 2

[0059] Refer to Figure 3 , this example is similar to Example 1. The main difference is that both ends of the third inductor Lp are respectively connected between the source electrodes of transistor M p3 and transistor M n3 .

[0060] Example 3

[0061] Refer to Figure 4 . In this example, a differential three-layer stacked transistor structure is adopted. The number of three-inductor parasitic capacitance cancellation networks is 1, and this three-inductor parasitic capacitance cancellation network is arranged between the output terminal of the second-layer transistor and the input terminal of the third-layer transistor. Specifically, the first inductor Ls is connected in series between the drain electrode of transistor M p3 and the source electrode of transistor M p4 . The second inductor Ls is connected in series between the drain electrode of transistor M n3 and the source electrode of transistor M n4 . Both ends of the third inductor Lp are respectively connected between the drain electrodes of transistor M p3 and transistor M n3 .

[0062] Example 4

[0063] Refer to Figure 5 . This example is similar to Example 3. The main difference is that both ends of the third inductor Lp are respectively connected between the source electrodes of transistor M p4 and transistor M n4 .

[0064] Example 5

[0065] Refer to Figure 6 . This example adopts a differential three-layer stacked transistor structure, and the number of three-inductor parasitic capacitance cancellation networks is 2.

[0066] The first three-inductor parasitic capacitance cancellation network is arranged between the output terminal of the first-layer transistor and the input terminal of the second-layer transistor. Specifically, the first inductor Ls is connected in series between the drain electrode of transistor M p2 and the source electrode of transistor M p3 . The second inductor Ls is connected in series between the drain electrode of transistor M n2 and the source electrode of transistor M n3 . Both ends of the third inductor Lp are respectively connected between the drain electrodes of transistor M p2 and transistor M n2 .

[0067] The second three - inductor parasitic capacitance cancellation network is arranged between the output terminal of the second - layer transistor and the input terminal of the third - layer transistor. Specifically, the first inductor Ls is connected in series between the drain of transistor M p3 and the source of transistor M p4 , the second inductor Ls is connected in series between the drain of transistor M n3 and the source of transistor M n4 , and both ends of the third inductor Lp are respectively connected between the drain of transistor M p3 and the drain of transistor M n3 .

[0068] Embodiment 6

[0069] Refer to Figure 7 , this embodiment is similar to Embodiment 5. The main difference is that in the first three - inductor parasitic capacitance cancellation network, both ends of the inductor Lp are respectively connected between the source of transistor M p3 and the source of transistor M n3 . In the second three - inductor parasitic capacitance cancellation network, both ends of the inductor Lp are respectively connected between the source of transistor M p4 and the source of transistor M n4 .

[0070] As Figures 2 - 7 shown. These circuit structures all satisfy the parasitic capacitance cancellation principle proposed in the embodiments of this invention. The three - inductor structure is adopted to eliminate the parasitic capacitance of the intermediate node of the stacked transistors, and has the ability to realize the amplification of millimeter - wave broadband signals.

[0071] Embodiment 7

[0072] Refer to Figure 8 , based on the above - mentioned three - inductor parasitic capacitance cancellation technology, this embodiment also provides a broadband power amplifier. The circuit structure of this amplifier is specifically as follows:

[0073] The input signal is evenly divided into two paths and input into the upper and lower identical circuits. First, it passes through a transmission line TL1, and then through a transformer to convert the single - ended signal into a differential signal and input it to the gate of the first - stage differential common - source drive circuit. This transformer serves as an input matching network and provides a bias VG1 to the gates of the common - source drive transistors (M p1 and M n1 ); The gates and drains of transistors M p1 and M n1 are connected with neutralization capacitors Cn1, and the drains are also connected with the primary coil of the inter - stage matching transformer. The center tap of the primary coil is connected to the VDD power supply to supply power to the first - stage drive stage, and the secondary coil is connected to the gates of the second - stage power amplifier transistors M p2 and M n2 , and a power supply is given to M at the center tapp2 and M n2 A bias voltage VG2 is applied to the gate of the transistor; M p2 and M n2 A neutralizing capacitor Cn2 is connected between the gate and the drain of the transistor; in M p2 and M n2 A series inductor Ls is connected between the drain of the transistor and the source of M p3 and M n3 and a parallel inductor Lp is connected between the drains; the other end of the inductor Ls is connected to the sources of the transistors M p2 and M n2 A parallel inductor Lp is connected between the drains; the other end of the inductor Ls is connected to the sources of the transistors M p3 and M n3 ; the gate bias of the transistor M p3 and M n3 is connected through a series resistor and a parallel capacitor Cg from VG3; the drains of the transistors M p3 and M n3 are connected to both ends of the primary coil of the output matching transformer, and the center tap is connected to the supply voltage VDD2 to supply power to the power stage circuit; one end of the secondary coil of the output matching transformer is grounded, and the other end is connected to the transmission line TL2. Finally, the two identical circuits are combined at the output end after passing through the transmission line TL2.

[0074] The working principle of the circuit is as follows:

[0075] The power amplifier in this embodiment has two paths. After being amplified by two completely identical and symmetric circuits, the output signals are power combined at the final stage; each path of the circuit has two stages, including a drive stage composed of a differential common-source amplifier and a power stage composed of a differential double-stack structure. The drive stage differential common-source amplifier mainly provides sufficient gain for the circuit, and the power stage circuit mainly provides sufficient output power for the circuit. The purpose of power combination is to further improve the gain and output power of the circuit. The power distribution network and the power synthesis network are completed by the transmission lines TL1 and TL2 respectively; the input matching network, the inter-stage matching network, and the output matching network are all based on transformers; the parasitic cancellation network is mainly composed of two series inductors Ls and a parallel inductor Lp.

[0076] The parasitic cancellation function in this embodiment is mainly completed by the second-stage circuit, and the technology used is the parasitic capacitance cancellation technology proposed in this invention. The power stage circuit adopts a differential double-stack structure. At the connection of the stacked transistors M p2 、M n2 and M p3 、M n3 Three inductors are used, namely two series inductors Ls connecting the drains of M p2 、M n2 and the drains of M p3 、M n3The source of the differential transistor M is connected to a parallel inductor p2 、M n2 At both ends of the drain, a broadband parasitic capacitance cancellation effect is achieved, thereby improving the output power and efficiency of the circuit; at the same time, reasonable design of the values of inductance Ls and Lp can allow the circuit to produce a zero point in the left half plane and a lower-frequency main pole, thereby effectively expanding the bandwidth of the circuit.

[0077] Compared with the prior art, the amplifier of the embodiment of the present invention has the following advantages:

[0078] In the prior art, the first prior art scheme and the fourth prior art scheme both adopt a three-stack structure, and the power supply voltages used are 4V and 3.3V respectively. Excessively high power supply voltages have high requirements on the process and easily lead to excessive voltage differences between adjacent ports of transistors, reducing the life of the transistors and even causing irreversible effects such as breakdown; the matching network of the second prior art scheme only includes transmission lines, which occupies a large area, and needs to consider distributed parameter effects (such as parasitic capacitance and inductance). It is more sensitive to process parameters and is difficult to design in the millimeter wave frequency band; the third prior art scheme uses two series inductors and one parallel capacitor for internal node matching of the differential double-stack power amplifier, which has high design complexity, and the parallel capacitors aggravate the influence of the parasitic capacitance of the transistor to a certain extent, resulting in performance deterioration at some frequency points.

[0079] On the other hand, the internal node matching methods adopted by the above four existing technical solutions are only narrowband matching, which can only achieve high output power and efficiency at specific frequencies, but it is difficult to achieve broadband matching, which greatly limits the operating frequency and bandwidth of the circuit.

[0080] Compared with the published design that uses a three-layer stacked structure to improve the output power architecture, the embodiment of the present invention uses a differential two-layer stacked structure power stage amplifier and a two-way power synthesis architecture, which can use a lower power supply voltage to achieve higher output power, and avoid irreversible effects such as breakdown caused by overvoltage at adjacent ports of the transistor by strictly controlling the gate bias voltage of the stacked transistor; the matching network uses a low-resistance transmission line combined with a transformer for matching, which can achieve a wider bandwidth and more efficient matching compared to the second prior art solution that only uses transmission lines for matching; compared with the internal node matching methods of the above-mentioned four prior art solutions, the embodiment of the present invention uses a three-inductor parasitic cancellation technology to achieve internal node matching within a wider bandwidth range and can be applied to higher frequency designs.

[0081] like Figure 9 As shown, in the embodiment of the present invention, the maximum gain of the circuit is 23.5dB, the -3dB bandwidth is 25.4GHz (42.1GHz-67.5GHz), and the corresponding relative bandwidth is 46.4%.Figure 10 As shown, the embodiments of the present invention can achieve a saturated output power of 19.4 dBm and a peak power combining efficiency of 20.5% at 49 GHz; a saturated output power of 18.9 dBm and a peak power combining efficiency of 19.4% at 55 GHz; and a saturated output power of 18 dBm and a peak power combining efficiency of 16.8% at 63 GHz.

[0082] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0083] The above embodiments are only for illustrating the technical concept and characteristics of the present invention, and the purpose is to enable those of ordinary skill in the art to understand the content of the present invention and implement it accordingly. It is not intended to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the essence of the content of the present invention should be covered within the protection scope of the present invention.

Claims

1. A three-inductor parasitic capacitance cancellation network, characterized in that Applied in a transistor structure of differential multi-layer stacking, it is set at the intermediate node of the differential stacked transistors and is used to eliminate the influence of the equivalent parasitic capacitance of the differential circuit transistors; The three-inductor parasitic capacitance cancellation network includes a first inductor, a second inductor, and a third inductor. The first inductor and the second inductor are matched and are respectively connected in series between the output terminal of the upper-layer transistor and the input terminal of the lower-layer transistor. Both ends of the third inductor are respectively connected to the output terminal of the upper-layer transistor or the input terminal of the lower-layer transistor.

2. The three-inductor parasitic capacitance cancellation network according to claim 1, wherein The transistor structure of the differential multi-layer stacking is a transistor structure of differential two-layer stacking; The differential signal is input to the gates of the common-source transistors M p2 and M n2 . After being amplified, the differential signal is output from the drains of the transistors M p2 and M n2 . It is input to the sources of the common-gate transistors M p3 and M n3 through a three-inductor parasitic capacitance cancellation network. After being amplified by the common-gate transistors M p3 and M n3 , the differential signal is output from the drains of the common-gate transistors M p3 and M n3 . Both ends of the first inductor are connected between the drain of the common-source transistor M p2 and the source of the common-gate transistor M p3 ; both ends of the second inductor are connected between the drain of the common-source transistor M n2 and the source of the common-gate transistor M n3 ; both ends of the third inductor are connected between the drain of the common-source transistor M p2 and the drain of the common-source transistor M p2 , or are connected between the source of the common-gate transistor M p3 and the source of the common-gate transistor M n3 .

3. The three-inductor parasitic capacitance cancellation network according to claim 1, wherein, The transistor structure of the differential multi-layer stacking is a transistor structure of differential three-layer stacking; The three-inductor parasitic capacitance cancellation network is set between the output terminal of the second-layer transistor and the input terminal of the third-layer transistor.

4. A three-inductor parasitic capacitance cancellation network according to claim 1, wherein The transistor structure of the differential multi-layer stacking is a transistor structure of differential three-layer stacking; The number of the three-inductor parasitic capacitance cancellation networks is two. The first three-inductor parasitic capacitance cancellation network is set between the output terminal of the first-layer transistor and the input terminal of the second-layer transistor, and the second three-inductor parasitic capacitance cancellation network is set between the output terminal of the second-layer transistor and the input terminal of the third-layer transistor.

5. A broadband power amplifier, characterized in that, It includes the three-inductor parasitic capacitance cancellation network according to any one of claims 1-4.

6. The broadband power amplifier according to claim 5, characterized in that, The broadband power amplifier includes a first circuit and a second circuit with the same and symmetrical circuit structures; the input signal is divided into two signals through a power distribution network and is respectively input into the first circuit and the second circuit; after being amplified, the input signal is power-combined by a power combination network to improve the gain and output power of the circuit.

7. The broadband power amplifier according to claim 6, characterized in that, The first circuit includes: A driver-stage circuit, the input terminal of which is connected to the power distribution network through an input matching network and adopts a differential common-source amplification structure to provide sufficient gain for the circuit; A power-stage circuit, the input terminal of which is connected to the output terminal of the driver-stage circuit through an inter-stage matching network and is composed of a differential double-stack structure to provide sufficient output power for the circuit; the three-inductor parasitic capacitance cancellation network is set on the differential double-stack structure; the output terminal of the power-stage circuit is connected to the power combination network through an output matching network; The input matching network, the inter-stage matching network, and the output matching network are all implemented by transformers.

8. A broadband power amplifier according to claim 6, characterized in that, The power distribution network and the power combination network are both implemented by transmission lines.

9. A chip, characterized in that, It includes the three-inductor parasitic capacitance cancellation network according to any one of claims 1-4, or the broadband power amplifier according to any one of claims 5-8.

10. An electronic device, characterized in that, It includes the chip according to claim 9.

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