An ultra-wideband power amplifier

Abstract

The present disclosure provides an ultra-wideband power amplifier, comprising: a transistor M1 having a grounded source, a gate serving as an input terminal, and a drain serving as an output terminal; an input matching circuit receiving a radio frequency input signal and configured to match the input impedance of the power amplifier with the output impedance of a radio frequency source; a gate bias circuit configured to provide a DC power supply to the gate of the transistor M1 and control the electrical bias state of the transistor M1; a drain bias circuit configured to control the drain bias voltage of the transistor M1 and provide DC power to the circuit of the power amplifier; an output matching circuit having one end connected to the drain of the transistor M1 and the other end connected to an external load and configured to match the output impedance of the power amplifier with the impedance of the external load; and a negative feedback circuit having one end connected to the drain of the transistor M1 and the other end connected to the gate of the transistor M1 and configured to divide the output signal of the transistor M1 and feed it back to the input terminal of the transistor M1 to improve the gain flatness of the power amplifier circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an ultra-wideband power amplifier with an operating frequency ranging from megahertz (MHz) to gigahertz (GHz). Background Art

[0002] With the rapid development of wireless communication technology, large data transmission and multifunctional communication equipment require communication systems with large bandwidth. Ultra-wideband power amplifiers are an essential component of broadband communication systems and are key to system performance. Their output power directly affects the communication distance, and their efficiency determines the system's endurance.

[0003] Currently, the main structures for implementing ultra-wideband amplifiers include negative feedback amplifiers, distributed amplifiers, and multi-stage impedance gradient amplifiers, each with its own unique characteristics. Negative feedback circuits offer high gain stability and low distortion by adjusting the resistance, capacitance, and inductance of the feedback network to achieve a compromise between gain and bandwidth. Distributed amplifiers achieve very wide bandwidth by integrating the capacitance of transistors into transmission lines. Multi-stage impedance gradient amplifiers utilize stepped transmission lines with different characteristic impedances to create multi-branch transformations, forming a matching circuit for a broadband power amplifier.

[0004] Among the aforementioned ultra-wideband amplifiers, the distributed structure is a common structure for ultra-wideband power amplifiers due to its wide bandwidth and excellent gain flatness. However, the distributed structure has a large circuit area and requires more than one transistor, which not only increases the difficulty of the process but also the design. Existing ultra-wideband power amplifiers suffer from problems such as insufficient bandwidth, low efficiency, and poor gain flatness. Summary of the Invention

[0005] (1) Technical issues to be resolved

[0006] Based on the above problems, the present disclosure provides an ultra-wideband power amplifier to alleviate technical problems in the prior art such as insufficient operating bandwidth, low efficiency, and low gain flatness of power amplifiers.

[0007] (2) Technical solution

[0008] The present disclosure provides an ultra-wideband power amplifier, comprising: a transistor M1, an input matching circuit, a gate bias circuit, a drain bias circuit, an output matching circuit, and a negative feedback circuit.

[0009] The source of transistor M1 is grounded, the gate serves as an input terminal, and the drain serves as an output terminal;

[0010] One end of the input matching circuit is connected to the RF source for receiving the RF input signal, and the other end is connected to the gate of the transistor M1 for matching the input impedance of the power amplifier with the output impedance of the RF source;

[0011] The gate bias circuit is connected to the gate of the transistor M1 and is used to provide a DC power supply to the gate of the transistor M1 to control the electrical bias state of the transistor M1 during operation;

[0012] The drain bias circuit is connected to the drain of the transistor M1 and is used to control the drain bias voltage of the transistor M1 and provide DC power to the power amplifier circuit;

[0013] One end of the output matching circuit is connected to the drain of the transistor M1, and the other end is connected to the external load, for matching the output impedance of the power amplifier with the impedance of the external load; and

[0014] One end of the negative feedback circuit is connected to the drain of the transistor M1, and the other end is connected to the gate of the transistor M1. The negative feedback circuit is used to divide the output signal on the output side of the transistor M1 and feed it back to the input side of the transistor M1 to improve the gain flatness of the power amplifier circuit.

[0015] According to an embodiment of the present disclosure, the input matching circuit includes capacitor C1, capacitor C2, capacitor C3, capacitor C4, inductor L1, inductor L2, resistor R1, and resistor R2; wherein, one end of capacitor C1 is connected to the output end of the RF source, and the other end is respectively connected to the inductor L1 and capacitor C2 arranged in parallel, capacitor C2 and inductor L2 are connected in series and then connected to the gate of transistor M1 together with inductor L1, one end of capacitor C4 is grounded, and the other end is connected in series with resistor R2; one end of capacitor C3 is grounded, and the other end is connected in parallel to the other end of resistor R2 and then in series with one end of resistor R1, and the other end of resistor R1 is connected between the capacitor C2 and inductor L2 connected in series.

[0016] According to an embodiment of the present disclosure, the gate bias circuit includes a capacitor C7, a capacitor C8, a capacitor C9, a resistor R4, and an inductor L4; wherein the capacitor C7, the capacitor C8, and the capacitor C9 are arranged in parallel, and one end of the capacitor C7, the capacitor C8, and the capacitor C9 are grounded and the other end is connected to the power supply V G s; one end of the resistor R4 is connected to the gate of the transistor M1, and the other end is connected in series with the inductor L4 and then connected to the power supply V GS .

[0017] According to an embodiment of the present disclosure, the negative feedback circuit includes a resistor R3, a capacitor C5, and an inductor L6; wherein one end of the resistor R3 is connected to the input end of the transistor M1, and the other end is connected in series with the capacitor C5 and the inductor L6 and then connected to the output end of the transistor M1.

[0018] According to an embodiment of the present disclosure, the output matching circuit includes an inductor L3 and a capacitor C6; wherein, one end of the inductor L3 is grounded, one end of the capacitor C6 is connected to the external load of the power amplifier, and the other ends of the inductor L3 and the capacitor C6 are both connected to the drain of the transistor M1.

[0019] According to an embodiment of the present disclosure, the drain bias circuit includes a capacitor C10, a capacitor C11, a capacitor C12, and an inductor L5; wherein the capacitor C10, the capacitor C11, and the capacitor C12 are arranged in parallel, and one end of the capacitor C10, the capacitor C11, and the capacitor C12 are grounded and the other end is connected to the power supply V DS One end of the inductor L5 is connected to the drain of the transistor M1, and the other end of the inductor L5 is also connected to the power supply V DS .

[0020] According to an embodiment of the present disclosure, the transistor M1 is a FET transistor, including a GaN HEMT or a GaAs HEMT.

[0021] According to an embodiment of the present disclosure, the integration type of the power amplifier circuit is a monolithic microwave integrated circuit or a hybrid microwave integrated circuit.

[0022] According to the embodiment of the present disclosure, the operating frequency of the power amplifier covers megahertz to gigahertz; the megahertz operating frequency range is 1-1000 MHz, and the gigahertz operating frequency range is 1-30 GHz.

[0023] (3) Beneficial effects

[0024] It can be seen from the above technical solutions that the ultra-wideband power amplifier disclosed in the present invention has at least one or part of the following beneficial effects:

[0025] (1) The present disclosure matches the input impedance of transistor M1 to the output impedance of the power supply through an input matching circuit. The input matching circuit has the characteristics of large low-frequency gain loss and small high-frequency gain loss, which is balanced with the large low-frequency gain and small high-frequency gain of transistor M4, thereby improving the gain flatness of the circuit. In addition, the input matching circuit of the present disclosure is very suitable for broadband impedance matching and can provide good return loss performance in the range of megahertz (MHz) to gigahertz (GHz);

[0026] (2) The present disclosure uses a negative feedback circuit to feed back a portion of the output signal to the input of the transistor, thereby improving the gain flatness of the circuit. On the other hand, it can change the input and output impedance of the transistor, thereby reducing the difficulty of input and output matching. In addition, the resistor R3 can improve the circuit stability while improving the gain flatness.

[0027] (3) The gate of the present disclosure uses a resistor R4 and an inductor L4 for RF current. On the one hand, the series connection of the resistor and the inductor can achieve a good RF current effect, and on the other hand, it can also improve the circuit stability.

[0028] (4) The use of a large inductor in the drain of the present disclosure can suppress the leakage of low-frequency signals into the drain bias circuit, thereby improving the output power and efficiency of low-frequency signals;

[0029] (5) The present disclosure solves the problem that existing distributed amplifiers use a large number of transistors, which leads to a large chip area, high production cost, and high manufacturing process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the composition of an ultra-wideband power amplifier provided according to the present disclosure;

[0031] Figure 2 A schematic diagram of the circuit structure of an ultra-wideband power amplifier provided according to the present disclosure;

[0032] Figure 3 A diagram showing the return loss simulation results of the ultra-wideband power amplifier provided by the present disclosure;

[0033] Figure 4 This is a simulation result diagram of the output power (Pin=30dBm) of the ultra-wideband power amplifier provided by the present disclosure;

[0034] Figure 5 This is a diagram showing the efficiency (Pin=30dBm) simulation results of the ultra-wideband power amplifier provided in the present disclosure.

[0035] [Description of the main component symbols of the embodiment of the present disclosure in the accompanying drawings]

[0036] 1- Input matching circuit;

[0037] 2-Gate bias circuit;

[0038] 3- Transistor M1;

[0039] 4-Negative feedback circuit;

[0040] 5-output matching circuit;

[0041] 6-Drain bias circuit. DETAILED DESCRIPTION

[0042] The present disclosure provides an ultra-wideband power amplifier with an operating frequency covering an ultra-wideband range from megahertz (MHz) to gigahertz (GHz). It can effectively alleviate the problems of current distributed amplifiers caused by the large number of transistors used, resulting in large chip area, high production cost, and high manufacturing process requirements.

[0043] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0044] In an embodiment of the present disclosure, an ultra-wideband power amplifier is provided, Figure 1 and Figure 2 As shown, the ultra-wideband power amplifier includes: an input matching circuit 1, a gate bias circuit 2, a transistor M1 (3), a negative feedback circuit 4, an output matching circuit 5, and a drain bias circuit 6. Wherein:

[0045] The source of transistor M1 (3) is grounded, the gate serves as an input terminal, and the drain serves as an output terminal;

[0046] At low frequencies, the input matching circuit has a larger loss, which can be balanced with the larger gain of the transistor at low frequencies, thereby improving the gain flatness of the device and providing good return loss performance in the megahertz (MHz) to gigahertz (GHz) range.

[0047] The gate bias circuit 2 is connected to the gate of the transistor M1 and is used to provide a DC power supply to the gate of the transistor M1 (3) to control the electrical bias state of the transistor M1 (3) when it is working.

[0048] The drain bias circuit 6 is connected to the drain of the transistor M1 and is used to control the drain bias voltage of the transistor M1 (3) and to control the drain bias voltage of the transistor M1 (3) through the power supply V DS Provide DC power to the power amplifier circuit;

[0049] One end of the output matching circuit 5 is connected to the drain of the transistor M1 (3), and the other end is connected to the external load, for matching the output impedance of the power amplifier with the impedance of the external load; and

[0050] One end of the negative feedback circuit 4 is connected to the drain of the transistor M1, and the other end is connected to the gate of the transistor M1. The negative feedback circuit 4 is used to divide the output signal on the output side of the transistor M1 and feed it back to the input side of the transistor M1 to improve the gain flatness of the power amplifier circuit.

[0051] According to the embodiment of the present disclosure, Figure 1 、 Figure 2As shown, the input matching circuit 1 includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an inductor L1, an inductor L2, a resistor R1, and a resistor R2; wherein one end of the capacitor C1 is connected to the output end of the RF source, and the other end is respectively connected to the inductor L1 and the capacitor C2 arranged in parallel, the capacitor C2 and the inductor L2 are connected in series and then connected together with the inductor L1 to the gate of the transistor M1 (3), one end of the capacitor C4 is grounded, and the other end is connected in series with the resistor R2; one end of the capacitor C3 is grounded, and the other end is connected in parallel to the other end of the resistor R2 and then connected in series with one end of the resistor R1, and the other end of the resistor R1 is connected between the capacitor C2 and the inductor L2 connected in series.

[0052] One end of the input matching circuit 1 is connected to the RF source for receiving the RF input signal, and the other end is connected to the gate of the transistor M1 for matching the input impedance of the power amplifier with the output impedance of the RF source;

[0053] According to the embodiment of the present disclosure, Figure 2 As shown, the gate bias circuit 2 includes capacitors C7, C8, C9, resistor R4, and inductor L4; wherein, capacitors C7, C8, and C9 are arranged in parallel, and one end of each of the capacitors C7, C8, and C9 is grounded, and the other end is connected to the power supply V GS One end of the resistor R4 is connected to the gate of the transistor M1 (3), and the other end is connected in series with the inductor L4 and then connected to the power supply V GS The resistor R4 and the inductor L4 act as RF current blockers.

[0054] According to the embodiment of the present disclosure, Figure 2 As shown, the negative feedback circuit 4 includes a resistor R3, a capacitor C5, and an inductor L6; wherein one end of the resistor R3 is connected to the input end of the transistor M1 (3), and the other end is connected in series with the capacitor C5 and the inductor L6 and then connected to the output end of the transistor M1 (3). The negative feedback circuit 4 can feed back a portion of the output signal of the transistor M1 (3) to the input end of the transistor M1 (3), thereby improving the gain flatness of the amplifier circuit. At the same time, the negative feedback circuit can also reduce the difficulty of input-output matching; the resistor R3 can improve the gain flatness and improve the circuit stability.

[0055] According to the embodiment of the present disclosure, Figure 2 As shown, the output matching circuit 5 includes an inductor L3 and a capacitor C6; wherein one end of the inductor L3 is grounded, one end of the capacitor C6 is connected to the external load of the power amplifier, and the other ends of the inductor L3 and the capacitor C6 are both connected to the drain of the transistor M1 (3). The output matching circuit 5 can match the output impedance of the power amplifier with the impedance of the external load.

[0056] According to the embodiment of the present disclosure, Figure 2As shown, the drain bias circuit 6 includes a capacitor C10, a capacitor C11, a capacitor C12, and an inductor L5; wherein the capacitor C10, the capacitor C11, and the capacitor C12 are arranged in parallel, and one end of the capacitor C10, the capacitor C11, and the capacitor C12 are grounded, and the other end is connected to the power supply V DS One end of the inductor L5 is connected to the drain of the transistor M1 (3), and the other end of the inductor L5 is also connected to the power supply V DS The value of the leakage inductor L5 needs to take into account the current flow of very low frequency signals in the circuit.

[0057] According to an embodiment of the present disclosure, the transistor M1 is a FET transistor, including but not limited to a GaN HEMT or a GaAs HEMT, and the source of the transistor M1 is grounded.

[0058] According to an embodiment of the present disclosure, the circuit integration type of the power amplifier of the present disclosure is a monolithic microwave integrated circuit or a hybrid microwave integrated circuit. The types of the resistors, inductors, and capacitors used are selected from chip components, through-hole components, or bare chips.

[0059] According to the embodiment of the present disclosure, the operating frequency of the power amplifier covers megahertz to gigahertz, wherein the megahertz operating frequency range is 1-1000 MHz, and the gigahertz operating frequency range is 1-30 GHz.

[0060] like Figure 3 As shown in FIG, the return loss simulation result of the ultra-wideband power amplifier is shown. It can be seen that in the frequency range of 10-2500MHz, the input return loss of the amplifier is less than -12dB; Figure 4 As shown in FIG, the simulation result of the output power (Pin=30dBm) of the ultra-wideband power amplifier is shown. It can be seen that in the frequency range of 10-2500MHz, the output power of the amplifier is greater than 40dBm; Figure 5 FIG. 4 is a diagram showing the simulation results of the efficiency of the ultra-wideband power amplifier (Pin=30 dBm). It can be seen that within the frequency range of 10-2500 MHz, the power added efficiency (PAE) of the amplifier is greater than 49%.

[0061] The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that any implementations not depicted or described in the drawings or the main text of the specification are known to those skilled in the art and are not described in detail. Furthermore, the above definitions of the various elements and methods are not limited to the various specific structures, shapes, or methods described in the embodiments, and can be easily modified or replaced by those skilled in the art.

[0062] According to the above description, those skilled in the art should have a clear understanding of the ultra-wideband power amplifier disclosed in the present invention.

[0063] In summary, the present disclosure provides an ultra-wideband power amplifier that utilizes a combination of input matching circuits and negative feedback circuits to address the issues of existing distributed amplifiers, such as large chip area, high manufacturing costs, and demanding fabrication processes, resulting from the large number of transistors used. Input matching circuit 1 matches the input impedance of transistor M1 to the output impedance of a power supply. Input matching circuit 1 exhibits high low-frequency gain loss and low high-frequency gain loss, balancing the high low-frequency gain and low high-frequency gain of transistor M4, thereby improving the gain flatness of the circuit. The negative feedback circuit not only feeds back a portion of the output signal to the transistor input, improving the gain flatness of the circuit, but also alters the input and output impedances of the transistor, reducing the difficulty of input-output matching. Furthermore, resistor R3 improves gain flatness while also enhancing circuit stability. Resistor R4 and inductor L4 are used at the gate for RF current conduction, achieving a strong RF current conduction effect through the series connection of the resistor and inductor, while also improving circuit stability. A large inductor is used at the drain to suppress low-frequency signal leakage into the drain bias circuit, thereby increasing low-frequency signal output power and efficiency. The disclosed ultra-wideband power amplifier circuit can operate at frequencies ranging from megahertz (MHz) to gigahertz (GHz), achieving ultra-wideband performance using only a single transistor. It boasts advantages such as small size, low return loss, high output power, and excellent gain flatness. This circuit addresses the issues faced by traditional distributed amplifiers, such as the large number of transistors required, which results in large chip area, high manufacturing costs, and demanding fabrication processes.

[0064] It should also be noted that the above are different embodiments provided by the present disclosure. These embodiments are used to illustrate the technical content of the present disclosure and are not intended to limit the scope of protection of the present disclosure. A feature of one embodiment can be applied to other embodiments through appropriate modification, replacement, combination, or separation.

[0065] It should be noted that, herein, unless otherwise specified, “a” element is not limited to a single element, but may include one or more elements.

[0066] Furthermore, unless otherwise specified, ordinal numbers such as "first" and "second" are used herein solely to distinguish multiple components with the same name and do not imply a hierarchy, level, execution order, or process sequence between them. A "first" component and a "second" component may appear together in the same component or in different components. The presence of a component with a higher ordinal number does not necessarily imply the presence of the other component with a lower ordinal number.

[0067] In this document, unless otherwise specified, the so-called feature A "or" or "and / or" feature B means that A exists alone, B exists alone, or A and B exist at the same time; the so-called feature A "and" or "and" or "and" feature B means that A and B exist at the same time; the so-called "include", "comprise", "have" and "contain" mean including but not limited to these.

[0068] Furthermore, in this document, terms such as "upper," "lower," "left," "right," "front," "back," or "between" are used solely to describe the relative positions of multiple elements and can be interpreted to include translation, rotation, or mirroring. Furthermore, in this document, unless otherwise specified, "an element is on another element" or similar descriptions do not necessarily mean that the element contacts the other element.

[0069] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0070] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. An ultra-wideband power amplifier, operating in the megahertz to gigahertz range, comprising: Transistor M1 (3), with its source connected to the ground, its gate serving as an input terminal, and its drain serving as an output terminal; An input matching circuit (1), one end of which is connected to the radio frequency source for receiving the radio frequency input signal, and the other end of which is connected to the gate of the transistor M1 for matching the input impedance of the power amplifier with the output impedance of the radio frequency source; A gate bias circuit (2) is connected to the gate of the transistor M1 and is used to provide a DC power supply to the gate of the transistor M1 (3) to control the electrical bias state of the transistor M1 (3) when it is working; a drain bias circuit (6), connected to the drain of the transistor M1, for controlling the drain bias voltage of the transistor M1 (3) and providing DC power to the power amplifier circuit; an output matching circuit (5), one end of which is connected to the drain of the transistor M1 (3) and the other end of which is connected to an external load, for matching the output impedance of the power amplifier with the impedance of the external load; as well as a negative feedback circuit (4), one end of which is connected to the drain of the transistor M1 and the other end of which is connected to the gate of the transistor M1, wherein the negative feedback circuit (4) is used to divide the output signal of the output end of the transistor M1 and feed it back to the input end of the transistor M1 to improve the gain flatness of the power amplifier circuit; The input matching circuit (1) includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an inductor L1, an inductor L2, a resistor R1, and a resistor R2; one end of the capacitor C1 is connected to the output end of the radio frequency source, and the other end is connected to the inductor L1 and the capacitor C2 respectively arranged in parallel, the capacitor C2 and the inductor L2 are connected in series and then connected together with the inductor L1 to the gate of the transistor M1 (3), one end of the capacitor C4 is grounded, and the other end is connected in series with the resistor R2; one end of the capacitor C3 is grounded, and the other end is connected in parallel to the other end of the resistor R2 and then connected in series with one end of the resistor R1, and the other end of the resistor R1 is connected between the capacitor C2 and the inductor L2 in series; the gate bias circuit (2) includes a capacitor C7, a capacitor C8, a capacitor C9, a resistor R4, and an inductor L4; the capacitor C7, the capacitor C8, and the capacitor C9 are arranged in parallel, and one end of the capacitor C7, the capacitor C8, and the capacitor C9 are all grounded and the other end is connected to the power supply V GS One end of the resistor R4 is connected to the gate of the transistor M1 (3), and the other end is connected in series with the inductor L4 and then connected to the power supply V GS .

2. The ultra-wideband power amplifier according to claim 1, wherein the negative feedback circuit (4) comprises a resistor R3, a capacitor C5, and an inductor L6; in, One end of the resistor R3 is connected to the input end of the transistor M1 (3), and the other end is connected in series with the capacitor C5 and the inductor L6 and then connected to the output end of the transistor M1 (3).

3. The ultra-wideband power amplifier according to claim 1, wherein the output matching circuit (5) comprises an inductor L3 and a capacitor C6; in, One end of the inductor L3 is grounded, one end of the capacitor C6 is connected to the external load of the power amplifier, and the other ends of the inductor L3 and the capacitor C6 are both connected to the drain of the transistor M1 (3).

4. The ultra-wideband power amplifier according to claim 1, wherein the drain bias circuit (6) comprises a capacitor C10, a capacitor C11, a capacitor C12, and an inductor L5; in, Capacitors C10, C11, and C12 are connected in parallel, with one end of each capacitor C10, C11, and C12 connected to the ground and the other end connected to the power supply V DS One end of the inductor L5 is connected to the drain of the transistor M1 (3), and the other end of the inductor L5 is also connected to the power supply V DS . The ultra-wideband power amplifier according to claim 1 , wherein the transistor M1 is a FET transistor, including a GaN HEMT or a GaAs HEMT. The ultra-wideband power amplifier according to claim 1 , wherein the circuit integration type is a monolithic microwave integrated circuit or a hybrid microwave integrated circuit. 7 . The ultra-wideband power amplifier according to claim 1 , wherein the megahertz operating frequency range is 1-1000 MHz, and the gigahertz operating frequency range is 1-30 GHz.

Images