Delay unit and annular oscillator formed by same
By designing a delay unit of the intermediate Schmitt flip-flop delay stage and upper and lower stacked control stage, combining leakage current suppression and dynamic body bias technology, the problems of insufficient starting and amplitude of the ring oscillator at extremely low voltages are solved, and stable starting and larger amplitudes are achieved at lower power supply voltages.
Patent Information
- Application Number
- CN202510326541.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, an inverter or Smitter trigger delay unit odd-number cascade ring oscillator is difficult to start up at extremely low voltage and has insufficient amplitude. Due to the limitations of standard logic devices, the problems of starting up and amplitude are difficult to solve at extremely low voltages.
The delay unit composed of the first to three inverters is adopted, and the intermediate Schmitt flip-flop delay stage and upper and lower stack control stage design is used, and the leakage current suppression method of pull-down and pull-up nodes is combined to enhance the feedback path length to suppress leakage current, and the dynamic threshold voltage is adjusted through dynamic body bias technology to improve the start-up and amplitude at low voltage.
It realizes stable start-up and increase amplitude at lower supply voltages, improves the on-current and off-current switching ratios, and improves the performance of the ring oscillator at low voltages.
Smart Images
Figure CN120377872A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a delay unit and a ring oscillator composed thereof. Background Art
[0002] With the development and application of sensor networks, Internet of Things, radio frequency front-ends, and wireless power transfer technologies, many electronic sensing systems adopt a wireless power supply design without a power source. However, limited by the power of radio frequency energy transfer, transmission distance, and coupling efficiency, the wireless power supply voltage is generally low and the driving power consumption is limited. Therefore, the system design requires extremely low power consumption and extremely low voltage.
[0003] To reduce costs, the design and implementation process technology generally adopts standard logic device compatibility, and is often limited by power supply, threshold voltage, speed, and leakage. Therefore, extremely low voltage and low power consumption optimization design is required.
[0004] Using a ring oscillator with odd-stage cascading of an inverter or Schmitt trigger delay unit as a basic unit of its analog circuit system is often limited by standard logic devices. As the power supply drops extremely low, the intrinsic gain, on-state and off-state current switching ratio of the delay unit all decrease, making it difficult to achieve oscillation starting under extremely low voltage and having amplitude sacrifice at the same time.
[0005] Please refer to Figure 1 and Figure 2 , which respectively show an inverter and a Schmitt trigger delay unit of the prior art.
[0006] To solve the above problems, a new type of delay unit and a ring oscillator composed thereof need to be proposed. Summary of the Invention
[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a delay unit and a ring oscillator composed thereof, which are used to solve the problem that when using a ring oscillator with odd-stage cascading of an inverter or Schmitt trigger delay unit as a basic unit of its analog circuit system in the prior art, it is often limited by standard logic devices. As the power supply drops extremely low, the intrinsic gain, on-state and off-state current switching ratio of the delay unit all decrease, making it difficult to achieve oscillation starting under extremely low voltage and having amplitude sacrifice at the same time.
[0008] To achieve the above purpose and other related purposes, the present invention provides a delay unit, including:
[0009] The first to third inverters, the first inverter is an intermediate Schmitt trigger delay stage, and the power supply terminal and the ground terminal of the first inverter are respectively connected to the second and third inverters in a structural manner; wherein,
[0010] The input terminals of the first to third inverters are short-circuited to be the input terminal of the delay unit;
[0011] The power supply terminal of the second inverter is connected to the power supply voltage Vdd, the ground terminal is connected to the ground wire, and the output terminal is connected to the power supply terminal of the first inverter;
[0012] The power supply terminal of the third inverter is connected to the power supply voltage Vdd, the ground terminal is connected to the ground wire, and the output terminal is connected to the ground terminal of the first inverter;
[0013] The output terminal of the first inverter serves as the output terminal of the delay unit;
[0014] The second and third inverters are upper and lower stacked control stages, so that the power supply and ground terminals of the intermediate Schmitt trigger delay stage always maintain the same potential state regardless of whether the input at the input terminal is ground or vdd or a signal that flips from ground to vdd or from vdd to ground, there is no potential difference, and it always corresponds to vdd or ground or a flip from vdd to ground or from ground to vdd.
[0015] Preferably, the first inverter uses a method of pulling down a first intermediate node to the ground and pulling up a second intermediate node to the power supply voltage to suppress leakage current.
[0016] Preferably, the first inverter includes: first to third PMOSs and first to third NMOSs. The gates of the first to third PMOSs and the first to third NMOSs are all connected to the input signal IN of the delay unit. The drain of the first PMOS is connected to the drain of the first NMOS and then serves as the output terminal of the delay unit. The source and body terminal of the first PMOS are shorted and then connected to the drain of the second PMOS to form a first intermediate node and are also connected to the drain of the pull-down device, the third NMOS. The source and body terminal of the second PMOS are shorted and then connected to the power supply voltage Vdd. The body and source terminals of the third NMOS are shorted and then pulled down to the ground. The source and body terminal of the first NMOS are shorted and then connected to the drain of the second NMOS to form a second intermediate node and are also connected to the drain of the pull-up device, the third PMOS. The source and body terminal of the second NMOS are shorted and then serve as the ground terminal. The source and body terminal of the third PMOS are shorted and then pulled up to the power supply voltage.
[0017] Preferably, the first intermediate node and the second intermediate node of the first inverter use a method of increasing the path length of the leakage current feedback suppression to suppress leakage current.
[0018] Preferably, the first inverter includes: first to fourth PMOS transistors and first to fourth NMOS transistors. The gates of the first, second, and fourth PMOS transistors and the first, second, and fourth NMOS transistors are all connected to the input signal IN of the delay unit. The drains of the first PMOS transistor, the gate of the third PMOS transistor, the drain of the first NMOS transistor, and the gate of the third NMOS transistor are connected together and used as the output terminal of the delay unit. The source and body of the first PMOS transistor are short-circuited and then connected to the drain of the second PMOS transistor to form a first intermediate node, which is also connected to the short-circuited terminal of the source and body of the third PMOS transistor in the feedback path. The source and body of the second PMOS transistor are short-circuited and then connected to the power supply voltage Vdd. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor. The source and body of the fourth NMOS transistor in the feedback path are short-circuited and pulled down to ground. The source and body of the first NMOS transistor are short-circuited and then connected to the drain of the second NMOS transistor to form a second intermediate node, which is also connected to the short-circuited terminal of the source and body of the third NMOS transistor in the feedback path. The source and body of the second NMOS transistor are short-circuited and used as the ground terminal. The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor. The source and body of the fourth PMOS transistor in the feedback path are short-circuited and pulled up to the power supply voltage.
[0019] The present invention also provides a ring oscillator composed of the above delay units, including:
[0020] A ring structure composed of n delay units, where n is a positive integer not less than 2; the output terminal of an adjacent delay unit in the ring structure is connected to the input terminal of the next-stage delay unit; the body terminal of the first inverter of each delay unit is connected to its input terminal.
[0021] The present invention also provides another ring oscillator composed of the above delay units, including:
[0022] A ring structure composed of n delay units, where n is a positive integer not less than 2; the output terminal of an adjacent delay unit in the ring structure is connected to the input terminal of the next-stage delay unit; the body terminal of the first inverter of each delay unit is connected to the output terminal of the next-stage delay unit.
[0023] As described above, the delay unit of the present invention and the ring oscillator composed thereof have the following beneficial effects:
[0024] The present invention can improve the start-up and amplitude problems at low voltages when the power supply voltage decreases, and has a lower start-up voltage and a larger amplitude. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 Schematic diagram of an inverter shown as the prior art;
[0026] Figure 2 Schematic diagram of the Schmitt trigger delay unit of the present invention;
[0027] Figure 3 Shown is a schematic diagram of the delay unit design of the present invention;
[0028] Figure 4 Shown is a schematic diagram of a first inverter circuit structure of the present invention;
[0029] Figure 5 Shown is another schematic diagram of a first inverter circuit structure of the present invention;
[0030] Figure 6 Shown is a schematic diagram of a ring oscillator composed of cascaded delay units of the present invention;
[0031] Figure 7 Shown is another schematic diagram of a ring oscillator composed of cascaded delay units of the present invention;
[0032] Figures 8 to 10 Shown is a schematic diagram of the simulation effect of applying a ring oscillator composed of cascaded delay units of the present invention. Detailed implementation manners
[0033] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0034] Example 1
[0035] Please refer to Figure 3 , the present invention provides a delay unit, including:
[0036] The first to third inverters, the first inverter 101 serves as an intermediate Schmitt trigger delay stage, and the power supply terminal and the ground terminal of the first inverter 101 are respectively connected to the second and third inverters in a structural manner; the Schmitt trigger has two stable states, but different from a general trigger, the Schmitt trigger uses a potential trigger method, and its state is maintained by the input signal potential; for input signals with two different change directions of negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages. For a standard Schmitt trigger, when the input voltage is higher than the positive threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output does not change, that is, the output changes from a high level to a low level, or from a low level to a high level, and the corresponding threshold voltages are different. Only when the input voltage changes sufficiently will the output change. Therefore, this type of element is named a trigger. Among them,
[0037] The input terminals of the first to third inverters are shorted to form the input terminal of the delay unit;
[0038] The power supply terminal of the second inverter 102 is connected to the power supply voltage Vdd, the ground terminal is grounded, and the output terminal is connected to the power supply terminal of the first inverter 101;
[0039] The power supply terminal of the third inverter 103 is connected to the power supply voltage Vdd, the ground terminal is grounded, and the output terminal is connected to the ground terminal of the first inverter 101;
[0040] The output terminal of the first inverter 101 serves as the output terminal of the delay unit;
[0041] The second and third inverters are upper and lower stacked control stages, such that the power supply and ground terminals of the intermediate Schmitt trigger delay stage always maintain the same potential state regardless of whether the input at the input terminal is ground or vdd or a signal that flips from ground to vdd or from vdd to ground. That is, regardless of whether the input terminal is 0 or 1 or flips from 0 to 1 or from 1 to 0, the power supply and ground terminals of the intermediate Schmitt trigger always maintain the same potential state, there is no potential difference, and they are all 1 or 0 or flip from 1 to 0 or from 0 to 1.
[0042] In an embodiment of the present invention, the first inverter 101 suppresses leakage current by pulling down a first intermediate node to ground and pulling up a second intermediate node to the power supply voltage.
[0043] For example, please refer to Figure 4 , the first inverter 101 includes: first to third PMOSs and first to third NMOSs. The gates of the first to third PMOSs and first to third NMOSs are all connected to the input signal IN of the delay unit. The drain of the first PMOS P1 is connected to the drain of the first NMOS N1 and then serves as the output terminal of the delay unit. The source and body terminal of the first PMOS P1 are shorted and then connected to the drain of the second PMOS P2 to form a first intermediate node and are also connected to the drain of the pull-down device, the third NMOS N3. The source and body terminal of the second PMOS P2 are shorted and then connected to the power supply voltage Vdd. The body and source terminals of the third NMOS N3 are shorted and then pulled down to ground. The source and body terminal of the first NMOS N1 are connected to form a second intermediate node and are also connected to the drain of the pull-up device, the third PMOS P3. The source and body terminal of the second NMOS N2 are shorted and then serve as the ground terminal. The source and body terminal of the third PMOS P3 are shorted and then pulled up to the power supply voltage.
[0044] The third NMOS N3 / third PMOS P3 is used for pull-down / pull-up GND / Vdd design, and an equivalent stacked inverter design is used for the Schmitt trigger to effectively suppress leakage current and improve the oscillation amplitude and start-up problem under low voltage.
[0045] In an embodiment of the present invention, the first intermediate node and the second intermediate node of the first inverter use a method of increasing the leakage current feedback suppression path length to suppress the leakage current.
[0046] For example, please refer to Figure 5 , the first inverter 101 includes: the first to fourth PMOSs and the first to fourth NMOSs. The gates of the first, second, and fourth PMOSs and the first, second, and fourth NMOSs are all connected to the input signal IN of the delay unit. The drain of the first PMOS P1, the gate of the third PMOS P3, the drain of the first NMOS N1, and the gate of the third NMOS N3 are connected together and used as the output terminal of the delay unit. The source and body terminal of the first PMOS P1 are short-circuited and then connected to the drain of the second PMOS P2 to form the first intermediate node, and are also connected to the short-circuited terminal of the source and body terminal of the third PMOS P3 in the feedback path. The source and body terminal of the second PMOS P2 are short-circuited and then connected to the power supply voltage Vdd. The drain of the third PMOS P3 is connected to the drain of the fourth NMOS N4. The source and body terminal of the fourth NMOS N4 in the feedback path are short-circuited and pulled down to ground. The source and body terminal of the first NMOS N1 are short-circuited and then connected to the drain of the second NMOS N2 to form the second intermediate node, and are also connected to the short-circuited terminal of the source and body terminal of the third NMOS N3 in the feedback path. The source and body terminal of the second NMOS N2 are short-circuited and used as the ground terminal. The drain of the third NMOS N3 is connected to the drain of the fourth PMOS P4. The source and body terminal of the fourth PMOS P4 in the feedback path are short-circuited and pulled up to the power supply voltage.
[0047] The leakage current feedback suppression path adopts an N / PMOS series design, and its gates are respectively connected to the input and output terminals, equivalent to the feedback of an inverter, enhancing the feedback path length, further enhancing the leakage current suppression ability, and improving the oscillation amplitude and startup problem under low voltage.
[0048] Compared with a single-stage Schmitt trigger, when the input is 0, the ground terminal GND of the first inverter 101 at the intermediate stage is at the Vdd potential. Its grounded NMOS changes from Vgs = 0, Vds = Vdd to Vgs = -vdd, Vds = 0 in the negative bias switch state, and there are two levels of negative bias NMOS switch stacks in the output-to-ground path; vice versa when the input is Vdd, and there are two levels of negative bias PMOS switch stacks in the output-to-Vdd path. Therefore, its effect of suppressing the off-state leakage current is significantly improved, and it can improve Ion (current under conduction) / Ioff (current in the cut-off state) and increase the oscillation amplitude.
[0049] At the same time, in the stacked design, the impedance of its output node to the ground is higher, and its dynamic intrinsic gain is higher, enabling oscillation at a lower power supply voltage and further improving the problem of reduced amplitude with the power supply voltage.
[0050] Embodiment 2
[0051] Please refer to Figure 6 , the present invention also provides a ring oscillator composed of the above delay units, including:
[0052] A ring structure composed of n delay units, where n is a positive integer not less than 2; the output end of an adjacent delay unit in the ring structure is connected to the input end of the next-stage delay unit. For example, in the n-stage delay unit, the output end of the first-stage delay unit is connected to the input end of the second-stage delay unit; the output end of the second-stage delay unit is connected to the input end of the third-stage delay unit;.....; the output end of the (n - 1)-stage delay unit is connected to the input end of the n-stage delay unit; the output end of the n-stage delay unit is connected to the input end of the first-stage delay unit; the body terminal of the first inverter 101 of each delay unit is connected to its input end.
[0053] Embodiment III
[0054] Please refer to Figure 7 , the present invention also provides another ring oscillator composed of the above delay units, including:
[0055] A ring structure composed of n delay units, where n is a positive integer not less than 2; the output end of an adjacent delay unit in the ring structure is connected to the input end of the next-stage delay unit; for example, in the n-stage delay unit, the output end of the first-stage delay unit is connected to the input end of the second-stage delay unit; the output end of the second-stage delay unit is connected to the input end of the third-stage delay unit;.....; the output end of the (n - 1)-stage delay unit is connected to the input end of the n-stage delay unit; the output end of the n-stage delay unit is connected to the input end of the first-stage delay unit; the body terminal of the first inverter 101 of each delay unit is connected to the output end of the next-stage delay unit.
[0056] A ring oscillator is formed by cascading delay units. To further improve the start-up and amplitude problems when the power supply voltage decreases, a dynamic body biasing technique is adopted. The body terminals of all devices in the delay unit are connected to its input end or the output end of the next-stage cascaded delay unit for dynamic threshold voltage regulation control to improve the dynamic oscillation flip characteristics.
[0057] Please refer to Figures 8 to 10 , which shows the simulation effect of applying cascaded delay units to form a ring oscillator. The present invention can improve the start-up and amplitude problems at low voltage when the power supply voltage decreases, and has a lower start-up voltage and a larger amplitude.
[0058] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0059] In summary, the present invention can improve the startup and amplitude problems at low voltages when the power supply voltage drops, and has a lower startup voltage and a larger amplitude. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0060] The above embodiments only illustratively explain the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A delay unit, characterized in that, Including: The first to third inverters, where the first inverter is an intermediate Schmitt trigger delay stage, and the power supply terminal and the ground terminal of the first inverter are respectively connected to the second and third inverters in a structural manner; among them, The input terminals of the first to third inverters are short-circuited to be the input terminal of the delay unit; The power supply terminal of the second inverter is connected to the power supply voltage Vdd, the ground terminal is connected to the ground wire, and the output terminal is connected to the power supply terminal of the first inverter; The power supply terminal of the third inverter is connected to the power supply voltage Vdd, the ground terminal is connected to the ground wire, and the output terminal is connected to the ground terminal of the first inverter; The output terminal of the first inverter is used as the output terminal of the delay unit; The second and third inverters are upper and lower stacked control stages, so that the power supply and ground terminals of the intermediate Schmitt trigger delay stage always maintain the same potential state regardless of whether the input at the input terminal is ground or vdd or a signal that flips from ground to vdd or from vdd to ground, there is no potential difference, and it always corresponds to vdd or ground or a flip from vdd to ground or from ground to vdd.
2. The delay unit according to claim 1, characterized in that: The first inverter uses the method of pulling down the first intermediate node to the ground and pulling up the second intermediate node to the power supply voltage to suppress leakage current.
3. The delay unit according to claim 2, wherein: The first inverter includes: the first to third PMOSs and the first to third NMOSs. The gates of the first to third PMOSs and the first to third NMOSs are all connected to the input signal IN of the delay unit. The drain of the first PMOS is connected to the drain of the first NMOS and then used as the output terminal of the delay unit. The source and body terminal of the first PMOS are short-circuited and then connected to the drain of the second PMOS to form the first intermediate node and are also connected to the drain of the pull-down device, the third NMOS. The source and body terminal of the second PMOS are short-circuited and then connected to the power supply voltage Vdd. The body and source terminal of the third NMOS are short-circuited and then pulled down to the ground. The source and body terminal of the first NMOS are short-circuited and then connected to the drain of the second NMOS to form the second intermediate node and are also connected to the drain of the pull-up device, the third PMOS. The source and body terminal of the second NMOS are short-circuited and then used as the ground terminal. The source and body terminal of the third PMOS are short-circuited and then pulled up to the power supply voltage.
4. The delay unit according to claim 1, wherein: The first intermediate node and the second intermediate node of the first inverter use the method of increasing the path length of the leakage current feedback suppression to suppress leakage current.
5. The delay unit according to claim 4, wherein: The first inverter includes: first to fourth PMOS transistors and first to fourth NMOS transistors. The gates of the first, second, and fourth PMOS transistors and the first, second, and fourth NMOS transistors are all connected to the input signal IN of the delay unit. The drains of the first PMOS transistor, the gate of the third PMOS transistor, the drains of the first NMOS transistor, and the gate of the third NMOS transistor are connected together and used as the output terminal of the delay unit. The source and body of the first PMOS transistor are short-circuited and then connected to the drain of the second PMOS transistor to form a first intermediate node, and are also connected to the short-circuited terminal of the source and body of the third PMOS transistor in the feedback path. The source and body of the second PMOS transistor are short-circuited and then connected to the power supply voltage Vdd. The drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor. The source and body of the fourth NMOS transistor in the feedback path are short-circuited and pulled down to ground. The source and body of the first NMOS transistor are short-circuited and then connected to the drain of the second NMOS transistor to form a second intermediate node, and are also connected to the short-circuited terminal of the source and body of the third NMOS transistor in the feedback path. The source and body of the second NMOS transistor are short-circuited and used as the ground terminal. The drain of the third NMOS transistor is connected to the drain of the fourth PMOS transistor. The source and body of the fourth PMOS transistor in the feedback path are short-circuited and pulled up to the power supply voltage.
6. The ring oscillator composed of the delay units according to any one of claims 1 to 5, characterized in that, Comprising: A ring structure composed of n delay units, where n is a positive integer not less than 2; The output terminal of an adjacent delay unit in the ring structure is connected to the input terminal of the next-stage delay unit; the body terminal of the first inverter of each delay unit is connected to its input terminal.
7. The ring oscillator composed of the delay units according to any one of claims 1 to 5, characterized in that, Comprising: A ring structure composed of n delay units, where n is a positive integer not less than 2; The output terminal of an adjacent delay unit in the ring structure is connected to the input terminal of the next-stage delay unit; the body terminal of the first inverter of each delay unit is connected to the output terminal of the next-stage delay unit.