Self-adaptive dead time generation circuit based on current mirror load and generation method thereof

Abstract

The invention relates to a self-adaptive dead time generation circuit based on a current mirror load and a generation method thereof, and the circuit comprises a first signal path A which is used for processing a PWMH signal and outputting a signal OUTA with dead time; the second signal path B is used for processing the PWML signal and outputting a signal OUTB with dead time; the biasing circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP5, a PMOS tube MP7, an NMOS (N-channel Metal Oxide Semiconductor) tube MN7 and a temperature coefficient compensation resistor R1, and is used for generating a reference current IREF with stable temperature; the dynamic feedback module comprises NOR gates NOR1 and NOR2, a Schmitt trigger SMIT, a PMOS transistor MP6 and a resistor R2, and the dead time is prolonged by detecting the current state; the first signal path A is connected with the second signal path B, the first signal path A and the second signal path B adopt mirror image design, each path is composed of two stages of delay units, and the biasing circuit and the dynamic feedback module are connected with the first signal path A and the second signal path B respectively. The system reliability is remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of power electronic device driving technology, specifically relating to an adaptive dead time generation circuit and its generation method based on a current mirror load. Background Technology

[0002] In power electronic systems, dead-time generation technology is a crucial step in ensuring the safe operation of power switching devices. Traditional dead-time generation schemes generally face the following problems: First, schemes based on fixed RC delay circuits rely on the charging and discharging characteristics of resistors and capacitors to achieve time control. However, their time constants are significantly affected by process deviations and temperature fluctuations, causing the dead time to deviate from the design value. This may lead to shoot-through risks, such as simultaneous conduction of upper and lower bridge arm power transistors, seriously threatening system reliability. Second, while digital control schemes can achieve precise adjustment of dead time through high-frequency clocks and complex logic, they require additional high-speed clock sources and logic control modules. This not only increases system power consumption and chip area costs but also introduces more severe electromagnetic interference (EMI) problems due to high-frequency signal transmission, worsening the system's electromagnetic compatibility. Third, analog detection circuits use gate voltage detection to monitor the power transistor status in real time. However, their response speed is limited by analog signal processing delays and is susceptible to power supply noise and parasitic parameter interference, leading to a decrease in dead-time calibration accuracy and making it difficult to meet the requirements of high-speed switching scenarios.

[0003] Therefore, there is an urgent need for an adaptive dead-time generation circuit with a full CMOS structure. Summary of the Invention

[0004] This invention overcomes the shortcomings of the prior art and provides an adaptive dead time generation circuit and its generation method based on a current mirror load. This invention achieves process robustness through an asymmetric charge and discharge delay path, and combines temperature compensation bias and dynamic feedback fast triggering mechanism to achieve adaptive calibration and anti-interference capability of dead time without the need for an external clock and complex logic, thus significantly improving system reliability.

[0005] The technical solution adopted by this invention to solve the problems existing in the prior art is: An adaptive dead-time generation circuit based on a current mirror load includes: a first signal path A for processing a PWMH signal and outputting a signal OUTA with a dead time; a second signal path B for processing a PWML signal and outputting a signal OUTB with a dead time; a bias circuit including PMOS transistors MP5, MP7, NMOS transistor MN7, and a temperature coefficient compensation resistor R1 for generating a temperature-stable reference current IREF; and a dynamic feedback module including NOR1, NOR2, Schmitt trigger SMIT, PMOS transistor MP6, and resistor R2 for extending the dead time by detecting the current state. The first signal path A and the second signal path B are connected and the two paths are mirrored, with each path consisting of two stages of delay units. The bias circuit and the dynamic feedback module are respectively connected to the first signal path A and the second signal path B.

[0006] Preferably, the first signal path A specifically comprises: a first-stage NMOS transistor MN1, whose gate receives the PWMH signal, and whose drain is connected to the drain of the PMOS mirror current source MP1, with the charging current I provided by the PMOS transistor MP1. p1 Mirror from I REF , specific I p1 =I REF / n1, the source of NMOS transistor MN1 is connected to ground; the output node V1 of the drain of PMOS transistor MP1 is connected to ground through capacitor C1, and the output node V1 is connected to the gate of the second-stage PMOS transistor MP2. The source of PMOS transistor MP1 is connected to VDD, and the gate of PMOS transistor MP1 is connected to the gate of PMOS current mirror source MP3. The source of the second-stage PMOS transistor MP2 is connected to VDD, and its drain is connected to the drain of NMOS current mirror source MN2, providing discharge current I. n2 Current I n2 Mirror from I REF , specific I n2 =I REF / n2, the drain of the secondary PMOS transistor MP2 is also connected to the A1 port of the NOR gate NOR1 and generates the output terminal OUTA, the source of the NMOS transistor MN2 is connected to the ground terminal, and the gate of the NMOS transistor MN2 is connected to the gate of the NMOS mirror current source MN4.

[0007] Preferably, the second signal path B is as follows: an NMOS transistor MN3, whose gate receives a PWML signal, and whose drain is connected to the drain of a PMOS mirror current source MP3. The source of the NMOS transistor MN3 is connected to ground. One path of the drain of the PMOS transistor MP3 is connected to ground through capacitor C2, and the other path is connected to the gate of the PMOS mirror transistor MP4. The source of the PMOS transistor MP4 is connected to VDD. The drain of the PMOS transistor MP4 is connected to the drain of the NMOS mirror current source MN4. The drain of the NMOS transistor MN4 is also connected to the A1 port of the NOR gate NOR2 to generate the output terminal OUTB. The source of the NMOS transistor MN4 is connected to ground.

[0008] Preferably, the temperature compensation resistor R1 is composed of a positive temperature coefficient resistor and a negative temperature coefficient resistor connected in series, and the absolute values ​​of their temperature coefficients are equal, used to maintain the reference current I. REF Temperature stability.

[0009] Preferably, the transistor sizes and current mirror ratios of the first signal path A and the second signal path B are matched to ensure consistent delay between the two paths. The first-stage NMOS common-source amplifier structure MN1 or MN3 utilizes the fast discharge of NMOS and the constant-current charging characteristics of the PMOS mirror current source MP1 or MP3 to output a slowly rising edge signal, forming an asymmetric delay. The second-stage PMOS common-source amplifier structure MP2 or MP4 uses the gradual turn-off of PMOS and the constant-current discharge characteristics of the NMOS mirror current source MN2 or MN4 to convert the slowly rising edge of the first-stage output into a slowly falling edge of the second-stage output. The dead time DT is the delay t of the falling edge of the second-stage output signal. f Decide.

[0010] Preferably, the dynamic feedback module is as follows: the drain of PMOS transistor MP6 is connected in series with the detection resistor R2 and connected to the ground terminal to form a voltage detection branch; the source of PMOS transistor MP6 is connected to the VDD terminal; the input terminal of Schmitt trigger SMIT is connected to the drain of PMOS transistor MP6; the output terminal of Schmitt trigger SMIT is connected in sequence to the second input terminals of NOR gates NOR1 and NOR2; when the voltage drop of R2 exceeds the threshold, SMIT triggers and forcibly pulls OUTA and OUTB low, extending the dead time.

[0011] Preferably, the bias circuit is specifically configured such that the source of PMOS transistor MP5 is connected to the VDD terminal, the drain of PMOS transistor MP5 is connected to the ground terminal through the temperature coefficient compensation resistor R1, and one gate of PMOS transistor MP5 is connected to the drain of PMOS transistor MP5, one gate is connected to the gate of PMOS mirror current source MP1, and the other gate is connected to the gate of PMOS transistor MP6.

[0012] Preferably, the source of the PMOS transistor MP7 in the bias circuit is connected to the VDD terminal, and its drain is connected to the drain of the NMOS transistor MN7. The gate of MP7 is connected to the gates of MP5, MP6, MP1, and MP3, respectively. The drain and gate of MN7 are shorted and connected to the gates of MN2 and MN4, respectively. The source of MN7 is connected to the ground terminal.

[0013] A dead-time generation method, based on the above circuit, includes the following steps: S1, generating a temperature-compensated reference current I through a bias circuit. REF S2. The first-stage NMOS transistors MN1 and MN3 are used to quickly discharge the PWMH and PWML signals, while the PMOS mirror current sources MP1 and MP3 provide constant current charging, generating intermediate signals with asymmetric delay at nodes V1 and V1M. S3. The second-stage PMOS transistors MP2 and MP4 are used to invert and amplify the V1 and V1M signals, and the NMOS mirror current sources MN2 and MN4 are used to discharge them with constant current, generating signals with controllable falling edge delay at nodes V2 and V2M. The falling edge delay directly determines the dead time. S4. When the dynamic feedback module detects an overcurrent state, the output signal is forcibly pulled low through the Schmitt trigger SMIT and the NOR gates NOR1 and NOR2 to extend the dead time.

[0014] Preferably, the width of the dead time is determined by the first stage charging time and the second stage discharging time, and dynamic calibration is achieved by adjusting the reference current IREF, the capacitance values ​​of capacitors C1 and C2, and the current proportionality coefficients n1 and n2.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The circuit scheme of this invention achieves adaptive and precise control of dead time through the synergistic design of a dynamic feedback path and an asymmetric charging and discharging mechanism. When the system detects a sudden increase in current, the dynamic feedback path can be automatically triggered to extend the dead time by 30%-50%, effectively avoiding the risk of power transistor shoot-through under high temperature or high current conditions. With the help of positive and negative temperature coefficient resistor compensation technology, the overall temperature drift rate of the circuit is significantly reduced from ±15% in the traditional scheme to ±5%. Combined with the asymmetric charging and discharging delay path and the symmetric delay structure, a highly stable and accurate dead time is generated. At the same time, the innovative architecture of sharing a bias network for delay generation, temperature compensation and adaptive adjustment can be compatible with standard CMOS processes without additional compensation modules, achieving functional integration while saving more than 30% of chip area, reducing system power consumption and electromagnetic interference. The method of this invention generates dead time through an asymmetric charge-discharge delay path, utilizing the asymmetric charge-discharge mechanism of common-source amplification and mirror current source. The dead time can be flexibly adjusted by feedback capacitor, bias current, and current ratio. Combined with the dynamic feedback path and temperature compensation design of the circuit, the system reliability is improved while ensuring the flexibility of dead time generation. This provides a solution for high-performance power conversion systems that combines cost advantages and technological advancement. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 This is a schematic diagram of the adaptive dead time generation circuit based on a current mirror load according to the present invention. Figure 2 This is a signal timing diagram of the first signal path A in an adaptive dead-time generation circuit based on a current mirror load according to the present invention. Figure 3 This is a timing diagram of the dead time generation circuit in an adaptive dead time generation circuit based on a current mirror load according to the present invention. Detailed Implementation The specification and claims use certain terms to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The term "comprising" throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." "Approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error.

[0018] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] The multifunctional biological experimental platform of the present invention will be further described in detail below with reference to the accompanying drawings, but this is not intended to limit the invention. An adaptive dead-time generation circuit based on a current mirror load includes: First signal path A: Processes the PWMH signal and outputs a signal OUTA with dead time. Second signal path B: Processes the PWML signal and outputs a signal OUTB with dead time. Bias circuit: Includes PMOS transistors MP5 and MP7, NMOS transistor MN7, and temperature coefficient compensation resistor R1, used to generate a temperature-stable reference current IREF. Dynamic feedback module: Includes NOR gates NOR1 and NOR2, Schmitt trigger SMIT, PMOS transistor MP6, and resistor R2, which triggers dead time extension by detecting abnormal current.

[0021] The first signal path A and the second signal path B adopt a mirror design, with each path consisting of two levels of delay units.

[0022] The first signal path A is specifically as follows: the first-stage NMOS common-source amplifier structure MN1 receives the PWMH signal at its gate, and its drain is electrically connected to the drain of the PMOS mirror current source MP1, with the charging current I provided by the PMOS transistor MP1. p1 Mirror from I REF , specific I p1 =I REF / n1, the source of the NMOS common-source amplifier structure MN1 is connected to the ground terminal. The output node V1 of the PMOS current mirror source MP1 is connected to ground via capacitor C1, and is also connected to the gate of the second-stage PMOS common-source amplifier structure MP2. The source of the PMOS current mirror source MP1 is connected to VDD, the gate of PMOS transistor MP1 is connected to the gate of PMOS current mirror source MP3, the source of the second-stage PMOS transistor MP2 is connected to VDD, and its drain is connected to the drain of NMOS current mirror source MN2, providing discharge current I. n2 Mirror from I REF , specific I n2 =IREF / n2, the drain of the secondary PMOS transistor MP2 is also connected to the A1 port of the NOR gate NOR1 to generate the output terminal OUTA, the source of the NMOS transistor MN2 is connected to the ground terminal, and the gate of the NMOS transistor MN2 is connected to the gate of the NMOS mirror transistor MN4. The first-stage delay unit structure uses an NMOS common-source amplifier MN1 with a PMOS transistor MP1 as the load. A capacitor C1 is connected in parallel to the first-stage output node. Asymmetric delay is achieved by utilizing the fast pull-down of MN1 and the constant-current slow charging of MP1. The second-stage delay unit structure uses a PMOS transistor MP2 with an NMOS transistor MN2 as the load. Through the gradual turn-off characteristic of MP2, combined with the constant-current discharge of MN2, the slow rising edge of the first stage is converted into a slow falling edge, with a delay superimposed at the output signal transition edge. After the two signals are shaped by a NOR1 gate, precise dead-time control is achieved.

[0023] The second signal path B is as follows: NMOS transistor MN3, whose gate is input with the PWML signal, and whose drain is electrically connected to the drain of the PMOS mirror current source MP3. The drain of NMOS transistor MN3 is connected to the ground terminal. One path of the drain of PMOS transistor MP3 is connected to the ground terminal through capacitor C2, and the other path is connected to the gate of NMOS mirror transistor MP4. The source of PNMOS transistor MP4 is connected to the VDD terminal. The drain of PNMOS transistor MP4 is connected to the drain of NMOS mirror transistor MN4. The drain of NMOS transistor MN4 is also connected to the A1 port of NOR gate NOR2 and generates the output terminal OUTB. The source of NMOS transistor MN4 is connected to the ground terminal. The first-stage delay unit structure uses an NMOS transistor MN3 with a PMOS transistor MP3 as the load, and a capacitor C2 connected in parallel at the first-stage output node. Asymmetric delay is achieved by utilizing the fast pull-down of MN3 and the constant-current slow charging of MP3. The second-stage delay unit structure uses a PMOS transistor MP4 with an NMOS mirror current source MN4 as the load. Through the gradual turn-off characteristic of MP4, combined with the constant-current discharge of MN4, the slow rising edge of the first stage is converted into a slow falling edge, and a delay is superimposed at the output signal transition edge. After the two signals are shaped by a NOR2 logic gate, precise dead-time control is achieved.

[0024] Since the first signal path A and the second signal path B are symmetrical, taking the first signal path A as an example, i.e., processing the PWMH signal, the working principle of its two-stage delay unit is as follows: The first stage MN1 acts as the input transistor, with its gate receiving the PWMH signal and its source grounded. The PMOS transistor MP1 acts as a current source load, its gate voltage provided by a current mirror, and its source connected to the VDD port. In this embodiment, the VDD port is specifically 15V. The drain of MP1 is connected to the drain of MN1. When the gate input signal PWM_H = High for MN1, MN1 is turned on, forming a low-impedance path from node V1 at the drain of MP1 to ground. MP1 operates in the saturation region attempting to pull up, but because the on-resistance Ron_MN1 of MN1 is very small, and the current In1 ≫ Ip1, V1 is quickly pulled down to a low level. It can be seen that the delay time is relatively short. Because the second-stage delay unit inverts the output of the first-stage delay unit, it transforms the sudden drop edge of the voltage at node V1 into a fast rising edge at the drain node V2 of MP2. When the voltage at node V1 drops rapidly, the gate voltage of M3 drops sharply, and |VGSMP2| = VDD - V1 increases rapidly. Therefore, the current Ip2 rises rapidly. When the current Ip2 rises to Ip2 ≫ In2, the voltage at V2 rises rapidly. According to... Cload is the parasitic capacitance at port A1 of the NOR1 NOR gate, with a value on the order of approximately femtofarads (fF). Therefore, the delay tr generated at the rising edge of the V2 output signal is approximately equal to t. discharge1 +t charge2 =R on_MN1 *C1+R on_MP2 *C load Specifically, if R on_MP1 =R on_MP2 =560 ohms, C1=1.2pF, C load =50fF, then tr≈0.7ns can be calculated, which is relatively small and can be ignored.

[0025] When the input signal PWM_H = Low, MN1 is turned off, and node V1 is disconnected from the ground. The current I of the constant current source MP1... p1 When capacitor C1 is charged, the voltage at node V1 increases linearly, and the charging rate is specifically dV1 / dt = I. p1 / C. The delay formation process of the rising edge of the signal at node V1 is as follows: When node V1 rises from a low level to a certain voltage amplitude ΔV, the time is approximately: The second-stage delay unit inverts the output of the first-stage delay unit, converting the slow rising edge into a slow falling edge. During the slow rising process of node V1, the moment when node V1 begins to rise is marked as time t1. The gate voltage of MP2 is at the same potential as that at node V1. As the voltage rises, according to |VGSMP2| = VDD - V1, |VGSMP2| slowly decreases, Ip2 slowly decreases, and MP2 gradually turns off. When the voltage at node V1 rises to VDD - |VTHP2|, MP2 turns off. This moment is marked as time t2. At this time, Ip2 = 0, and the rise time of node V1 is t2 - t1. At this point, MN2 is operating in the saturation region, the current In2 is fixed, and the discharge rate is dV2 / dt=I. n2 / C load C load Approximately on the order of fly farads (fF), V2 decreases linearly. When the node voltage V1 rises to I... n2 =I p2 At time t2, the voltage at node V2 has already started to decrease, and at time t2, node V2 decreases to... The time when V2 reaches its lowest point is marked as t3, and the linear descent time of node V2 is specifically t3-t2. Therefore, the delay generated at the falling edge of the output signal of node V2 is tf ≈ t3 - t1 = The specific signal timing diagram of the above process is shown in Figure 2.

[0026] One embodiment is provided, specifically I REF =250uA, I p1 =42uA, I n2 =30uA, |VTHP2|=1.5V, C1=1.2pF, C load =50fF, V X =10V. We can obtain t. f =386ns + 17ns = 403ns. Because t f >>t r , t r It is relatively small and can be ignored. f The dead time DT is obtained after shaping by a NOR1 gate. Additionally, the current I... p1 Mirror from I REF I p1 =I REF / n1, Current I n2 Mirror from I REF I n2 =I REF / n2 , By changing R1, C1, and the transistor width-to-length ratio (W / L)... MP1(W / L) MN2 The specific value can achieve precise control over the dead time (DT).

[0027] Specifically, the bias circuit consists of PMOS transistor MP5 with its source connected to VDD, and its drain connected to ground via a temperature coefficient compensation resistor R1. One gate of MP5 is connected to its drain, another to the gate of PMOS current mirror MP1, and the third to the gate of PMOS current source MP6. PMOS transistor MP7 has its source connected to VDD and its drain connected to the drain of NMOS transistor MN7. The gate of MP7 is connected to the gates of MP5, MP6, MP1, and MP3. The drain and gate of MN7 are shorted and connected to the gates of MN2 and MN4, respectively. The source of MN7 is connected to ground.

[0028] MP5 transistor and R1 form a reference current source. Current formula: R1 consists of a positive temperature coefficient polycrystalline silicon (+3000ppm / ℃) connected in series with a negative temperature coefficient diffusion resistor (-5000ppm / ℃), resulting in a net temperature coefficient of -2000ppm / ℃. Through resistor ratio optimization, I... REF Fluctuations within the temperature range of -40℃ to 125℃ are less than ±3%, and the dead time stability is improved by 40% at high temperatures.

[0029] MP5 is connected to the temperature coefficient complementary resistor R1 in a diode configuration (drain short-circuited) and then connected to VDD. Current I REF Specifically: I REF Since R1 is composed of resistors from positive temperature coefficient (PTC) and negative temperature coefficient (NTC) materials connected in series, as the temperature increases, the PTC resistance increases, the NTC resistance decreases, and the total resistance R1 remains stable, thus ensuring the bias current I. REF Unaffected by temperature drift, thus ensuring temperature stability during dead time.

[0030] The dynamic feedback module is specifically as follows: the PMOS current source MP6 is connected in series with the detection resistor R2 and connected to the ground terminal to form a voltage detection branch. The source of the PMOS current source MP6 is connected to the VDD terminal. The Schmitt trigger SMIT input terminal is connected to the drain of the PMOS current source MP6, and the Schmitt trigger SMIT output terminal is connected in sequence to the second input terminals of the NOR gates NOR1 and NOR2, which is used to forcibly pull down the output signal when an abnormal current is detected, triggering the failure protection mechanism. The bias module provides the reference current, and the mirror current source MP6 generates a voltage drop V across R2. MIIt reflects the power transistor's current state in real time. When the turn-off delay of the switching transistor causes an abnormal increase in current, the dead time decreases, posing a risk of shoot-through. The Schmitt trigger input voltage V... MI The voltage rises to above the threshold of 6.5V. MO When the signal transitions to a high level, output signals OUTA and OUTB are simultaneously forced low, extending the dead time. By using NOR gates NOR1 and NOR2 to force OUTA and OUTB low, the trigger delay is reduced to less than 10ns. The forced low period extends the dead time until V... MI When the value falls below the safety threshold, a closed-loop dynamic protection is formed. For details, refer to the timing diagram of the dead time generation circuit in an adaptive dead time generation circuit based on a current mirror load in Figure 3.

[0031] The PMOS transistor MP6 is matched one-to-one with the bias circuit current, and the drive resistor R2 generates a voltage drop V. MI V MI Feedback V after Schmitt trigger (SMIT) MO When a sudden current change causes the dead time to decrease, the input of the NOR gate is forcibly pulled low to the A2 terminal of NOR1 and NOR2, dynamically adjusting the dead time and reducing the risk of shoot-through. When the circuit experiences I... REF When I suddenly increases n and I p The increase in dead time (DT) and decrease in dead time (DT) pose a risk of passthrough. At this point, V... MI Increasing the dead time forces the NOR1 and NOR2 input terminals A2 to go high, extending the time that OUTA and OUTB are simultaneously low.

[0032] Embodiment 2 is provided, specifically, setting I REF =250uA, R2=15kohm, and (W / L) MP5 and (W / L) MP6 If the ratio is 1:1, then V MI =3.75V. The threshold voltage of the Schmitt trigger is 6.5V. If an abnormal operating condition occurs, such as a 100% sudden increase in current, the dead time DT decreases by 50%, and V MI Triggering the Schmitt threshold, V MO The toggle output is high, forcibly pulling both OUTA and OUTB low.

[0033] Before using the above circuit, parameter adjustments are required. The specific parameter adjustment method is as follows: change the reference current I by adjusting the resistance value of the bias resistor R1. REF This allows for coarse adjustment of the dead time; fine adjustment is achieved by replacing delay capacitors C1 and C2 with different capacitance values; and the charging current I is changed by adjusting the current proportional coefficients n1 and n2. p1 and discharge current In2 It can simultaneously achieve fine-tuning of dead time. A dead-time generation method, using the above circuit, includes the following steps: S1. A temperature-compensated reference current I is generated through a bias circuit. REF ; S2. The first-stage NMOS transistors MN1 and MN3 are used to quickly discharge the PWMH and PWML signals, while the PMOS mirror current sources MP1 and MP3 are used to charge the signals with constant current, generating intermediate signals with asymmetric delay at nodes V1 and V1M. S3. The signals at nodes V1 and V1M are inverted and amplified by the second-stage PMOS transistors MP2 and MP4, and the signals at nodes V2 and V2M are generated by constant current discharge using NMOS mirror current sources MN2 and MN4. The falling edge delay directly determines the dead time. S4. When the dynamic feedback module detects an overcurrent condition, it forcibly pulls the output signal low through the Schmitt trigger (SMIT) and the NOR1 and NOR2 gates to extend the dead time.

[0034] The width of the dead time is determined by the first-stage charging time and the second-stage discharging time, and is adjusted by the reference current I. REF Dynamic calibration is achieved by using the capacitance values ​​of capacitors C1 and C2, as well as the current proportionality coefficients n1 and n2.

[0035] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An adaptive dead-time generation circuit based on a current mirror load, characterized in that, include: First signal path A: Used to process the PWMH signal and output a signal OUTA with dead time; Second signal path B: Used to process PWML signals and output a signal OUTB with dead time; Bias circuit: includes PMOS transistors MP5 and MP7, NMOS transistor MN7, and temperature coefficient compensation resistor R1, used to generate a temperature-stable reference current I. REF ; Dynamic feedback module: includes NOR1 and NOR2, Schmitt trigger SMIT, PMOS transistor MP6 and resistor R2, which extend the dead time by detecting the current state; The first signal path A and the second signal path B are connected, and the first signal path A and the second signal path B adopt a mirror design. Each path consists of two-stage delay units. The bias circuit and the dynamic feedback module are respectively connected to the first signal path A and the second signal path B.

2. The adaptive dead-time generation circuit based on a current mirror load according to claim 2, characterized in that, The first signal path A is specifically as follows: The first-stage NMOS transistor MN1 receives the PWMH signal at its gate, and its drain is connected to the drain of the PMOS current mirror MP1. The charging current, I, is provided by the PMOS transistor MP1. p1 Mirror from I REF , specific I p1 =I REF / n1, the source of NMOS transistor MN1 is connected to the ground terminal. The output node V1 of PMOS transistor MP1 is connected to ground via capacitor C1, and is also connected to the gate of the second-stage PMOS transistor MP2. The source of PMOS transistor MP1 is connected to VDD, and its gate is connected to the gate of PMOS current mirror MP3. The source of the second-stage PMOS transistor MP2 is connected to VDD, and its drain is connected to the drain of NMOS current mirror MN2, providing the discharge current I. n2 Current I n2 Mirror from I REF , specific I n2 =I REF / n2, the drain of the secondary PMOS transistor MP2 is also connected to the A1 port of the NOR gate NOR1 and generates the output terminal OUTA, the source of the NMOS transistor MN2 is connected to the ground terminal, and the gate of the NMOS transistor MN2 is connected to the gate of the NMOS mirror current source MN4.

3. The adaptive dead-time generation circuit based on a current mirror load according to claim 2, characterized in that, The second signal path B is specifically as follows: The NMOS transistor MN3 has a PWML signal input to its gate, and its drain is connected to the drain of the PMOS mirror current source MP3. The source of the NMOS transistor MN3 is connected to the ground terminal. The drain of the PMOS transistor MP3 is connected to the ground terminal through capacitor C2, and the other path is connected to the gate of the PMOS mirror transistor MP4. The source of the PMOS transistor MP4 is connected to the VDD terminal, and the drain of the PMOS transistor MP4 is connected to the drain of the NMOS mirror current source MN4. The drain of the NMOS transistor MN4 is also connected to the A1 port of the NOR gate NOR2 to generate the output terminal OUTB. The source of the NMOS transistor MN4 is connected to the ground terminal.

4. The adaptive dead-time generation circuit based on a current mirror load according to claim 1, characterized in that, The temperature compensation resistor R1 is composed of a positive temperature coefficient resistor and a negative temperature coefficient resistor connected in series, and the absolute values ​​of their temperature coefficients are equal. It is used to maintain the reference current I. REF Temperature stability.

5. The adaptive dead-time generation circuit based on a current mirror load according to claim 3, characterized in that, The transistor sizes and current mirror ratios of the first signal path A and the second signal path B are matched to ensure consistent delay between the two paths. The first-stage NMOS common-source amplifier structure MN1 or MN3 utilizes the fast discharge characteristic of NMOS and the constant-current charging characteristic of PMOS mirror current source MP1 or MP3 to output a slowly rising edge signal, forming an asymmetric delay. The second-stage PMOS common-source amplifier structure MP2 or MP4, through the PMOS gradual turn-off and the constant-current discharge characteristic of NMOS mirror current source MN2 or MN4, converts the slowly rising edge of the first-stage output into a slowly falling edge of the second-stage output. The dead time DT is the delay t of the falling edge of the second-stage output signal. f Decide.

6. The adaptive dead-time generation circuit based on a current mirror load according to claim 3, characterized in that, The dynamic feedback module is specifically: The drain of the PMOS transistor MP6 is connected in series with the detection resistor R2 and then connected to the ground terminal to form a voltage detection branch. The source of the PMOS transistor MP6 is connected to the VDD terminal. The input terminal of the Schmitt trigger SMIT is connected to the drain of the PMOS transistor MP6, and the output terminal of the Schmitt trigger SMIT is connected in sequence to the second input terminals of the NOR gates NOR1 and NOR2. When the voltage drop across R2 exceeds the threshold, SMIT triggers a forced pull-down of OUTA and OUTB, extending the dead time.

7. The adaptive dead-time generation circuit based on a current mirror load according to claim 6, characterized in that, Specifically, the bias circuit consists of the source of PMOS transistor MP5 connected to the VDD terminal, the drain of PMOS transistor MP5 connected to the ground terminal through a temperature coefficient compensation resistor R1, and one gate of PMOS transistor MP5 connected to the drain of PMOS transistor MP5, one gate connected to the gate of PMOS mirror current source MP1, and the other gate connected to the gate of PMOS transistor MP6.

8. The adaptive dead-time generation circuit based on a current mirror load according to claim 7, characterized in that, The source of the PMOS transistor MP7 in the bias circuit is connected to the VDD terminal, and its drain is connected to the drain of the NMOS transistor MN7. The gate of MP7 is connected to the gates of MP5, MP6, MP1, and MP3 respectively. The drain and gate of MN7 are shorted and connected to the gates of MN2 and MN4 respectively. The source of MN7 is connected to the ground terminal.

9. A method for generating dead time, implemented based on the circuit described in any one of claims 1-8, characterized in that, Includes the following steps: S1. A temperature-compensated reference current I is generated through a bias circuit. REF ; S2. Use the first-stage NMOS transistors MN1 and MN3 to quickly discharge the PWMH and PWML signals, while simultaneously charging them with constant current by the PMOS mirror current sources MP1 and MP3, generating intermediate signals with asymmetric delay at nodes V1 and V1M. S3. The signals V1 and V1M are inverted and amplified by the second-stage PMOS transistors MP2 and MP4, and the NMOS mirror current sources MN2 and MN4 are used for constant current discharge to generate signals with controllable falling edge delay at nodes V2 and V2M. The falling edge delay directly determines the dead time. S4. When the dynamic feedback module detects an overcurrent condition, it forcibly pulls the output signal low through the Schmitt trigger (SMIT) and the NOR1 and NOR2 gates to extend the dead time.

10. A dead-time generation method according to claim 9, characterized in that, The width of the dead time is determined by the first-stage charging time and the second-stage discharging time, and is adjusted by the reference current I. REF Dynamic calibration is achieved by using the capacitance values ​​of capacitors C1 and C2, as well as the current proportionality coefficients n1 and n2.

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