Broadband double-layer interconnection structure based on silicon adapter plate technology

Abstract

The invention discloses a broadband double-layer interconnection structure based on a silicon adapter plate technology, and belongs to the technical field of radio frequency microsystems. According to the method, a three-dimensional compensation structure is formed by adding square conductive metal and TSVs into lower-layer metal at one end, close to a transition structure, of an original coplanar waveguide transmission line, and a resonance point with return loss of-51dB is introduced at 17.59 GHz, so that the broadband interconnection effect that the return loss of 0-33GHz is smaller than or equal to-20dB is achieved, and the in-band insertion loss fluctuation value is reduced by 11.6% compared with that of the original structure. Compared with a traditional interconnection structure broadband design, the method has the advantages that on the premise that the plane area is not increased, the broadband interconnection design difficulty is greatly reduced through the three-dimensional structure design.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency microsystems, and particularly relates to a design method for an interconnection structure based on a high-density three-dimensional heterogeneous integration process of a silicon interposer. Background Art

[0002] Traditional single-band architectures are difficult to meet the full-band coverage requirements in multi-task concurrent scenarios. Therefore, radio frequency microsystems urgently need to build T / R components with ultra-wideband characteristics. As the core carrier for multi-band signal transmission in T / R components, the transmission performance of the broadband interconnection transmission structure has become a key factor restricting the performance of radio frequency microsystems. In the packaging architecture of T / R components, the brick-type three-dimensional packaging exhibits significant spatial advantages compared to the traditional tile-type packaging, providing strong support for the miniaturized design of components. Currently, in three-dimensional packaging technologies, the silicon interposer process has been widely used in the design of T / R components due to its high-precision wiring ability and excellent heat dissipation performance. For the design of broadband interconnection transmission structures, existing technologies mostly adopt two-dimensional compensation structures (such as adding raised structures on both sides of the microstrip line near the transition structure) to achieve broadband impedance matching, such as Liu Weiqiang, Wan Tao, Lv Miao, etc. Ultra-wideband T / R components based on silicon-based stacked SIP technology [J]. Journal of Microwaves, 2024, 40(02): 74-78, and Faxin Yu, Xi Guo, Siyuan Ma, et al. Design and Fabrication of a T / R Microsystem in Ka-Band With Si-Based 3-D Heterogeneous Integration [J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2024, 14(5): 862-871. Due to the limited capacitance value of two-dimensional compensation structures, the bandwidth expansion is limited and the planar area increases. This solution innovatively introduces a three-dimensional compensation structure, constructing compensation units in the vertical dimension, which not only significantly broadens the broadband transmission characteristics of the interconnection structure but also does not require additional occupation of planar space. Summary of the Invention

[0003] Aiming at the two problems of insufficient radio frequency bandwidth of the interconnection structure of ultra-wideband T / R components and the increase in area of two-dimensional planar compensation structures, which is not conducive to miniaturization, the present invention proposes a solution using a three-dimensional compensation structure.

[0004] The present invention adopts the following technical solution: A broadband double-layer interconnection structure based on a silicon interposer process, the structure comprising: a top-layer silicon interposer, an interlayer solder ball layer, and a bottom-layer silicon interposer; the top-layer silicon interposer and the bottom-layer silicon interposer are two independent structures;

[0005] The top silicon interposer from top to bottom includes: UM2 layer, UP1 layer, UM1 layer, Usio2 layer, Si layer, Dsio2 layer, DM1 layer, DP1 layer, DM2 layer; the UM1 layer, UM2 layer, DM1 layer, and DM2 layer use Cu as the conductive material, the Usio2 layer and Dsio2 layer are made of Sio2 material, the UP1 layer and DP1 layer are polyimide, and the DM2 layer consists of multiple independent metal pads; an input microstrip and an output microstrip are etched along the midline of the UM2 layer. The left end of the input microstrip is flush with the left end of the UM2 layer, the right end of the input microstrip is connected to a pad, the right end of the output microstrip is flush with the right end of the UM2 layer, the left end of the output microstrip is connected to a pad, and the corresponding pads of the input microstrip and the output microstrip are connected to the corresponding metal pads HP1 and metal pad HP2 in the DM2 layer through silicon vias. An isolation ring is arranged at the position of the silicon vias passing through the DM1 layer; one column of metal vias is arranged on each side of the input microstrip and the output microstrip. The upper end of the metal vias is connected to the UM2 layer, and the lower end is connected to the DM1 layer to prevent the leakage of transmitted electromagnetic waves;

[0006] The top silicon interposer also includes an input compensation structure and an output compensation structure with the same structure. Both the input compensation structure and the output compensation structure include a top cap and metal vertical vias. The top cap is etched from the UM1 layer and is connected to the DM1 layer through the metal vertical vias; the input compensation structure is located below the input microstrip, and the output compensation structure is located below the output microstrip;

[0007] The bottom silicon interposer from top to bottom includes: UM3 layer, UP2 layer, UM2 layer, UP1 layer, UM1 layer, Usio2 layer, Si layer, Dsio2 layer, DM1 layer; the UM3 layer, UM2 layer, UM1 layer, and DM1 layer use Cu as the conductive material, the Usio2 layer and Dsio2 layer are made of Sio2 material, the UP2 layer and UP1 layer are polyimide, and the UM3 layer consists of more than two independent metal pads; a transmission microstrip is etched along the midline of the UM2 layer. The left end and the right end of the transmission microstrip are connected to the corresponding metal pads HP3 and metal pad HP4 of the UM3 layer through metal vias; the positions of the metal pads HP3 and metal pad HP4 correspond to the positions of the metal pads HP1 and metal pad HP2; a circle of metal vias is arranged around the transmission microstrip. The upper end of the metal vias is connected to the UM2 layer, and the lower end is connected to the DM1 layer to prevent the leakage of transmitted electromagnetic waves;

[0008] The interlayer solder ball layer includes more than two metal solder balls. The upper end of each metal solder ball is connected to one metal pad in the DM2 layer of the top silicon interposer, and the lower end is connected to one metal pad in the UM3 layer of the bottom silicon interposer; at least one metal solder ball has its upper end connected to the metal pad HP1 and its lower end connected to the metal pad HP3, and at least one metal solder ball has its upper end connected to the metal pad HP2 and its lower end connected to the metal pad HP4.

[0009] Further, the thicknesses of the UM1 layer, UM2 layer, DM1 layer, and DM2 layer in the top silicon interposer are 5 μm; the line widths of the input microstrip and output microstrip are 0.1 mm, and the distance from the ground plane is 0.05 mm.

[0010] Further, the thicknesses of the UM3 layer, UM2 layer, UM1 layer, and DM1 layer in the bottom silicon interposer are 5 μm; the line width of the transmission microstrip is 0.12 mm, and the distance from the ground plane is 0.05 mm.

[0011] Further, the height of the through-silicon via is 200 μm and the diameter is 30 μm.

[0012] The method of the present invention has the following advantages compared with the prior art:

[0013] The three-dimensional compensation structure of the present invention innovatively integrates three-dimensional integration technology, breaks through the spatial limitation of the traditional two-dimensional plane compensation scheme, and realizes the capacitance compensation effect through the spatial reconstruction in the vertical dimension, thereby realizing broadband interconnect matching from 0 to 33 GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a stacked schematic diagram of the advanced packaging process of the silicon interposer adopted by the present invention.

[0015] Figure 2 It is a 3D schematic diagram of the three-dimensional interconnect structure proposed by the present invention.

[0016] Figure 3 It is a cross-sectional schematic diagram of the three-dimensional interconnect structure.

[0017] Figure 4 It is a three-dimensional schematic diagram of the three-dimensional compensation structure proposed to achieve the broadband interconnect effect.

[0018] Figure 5 It is an explanation of the parameters of the upper layer board in the three-dimensional interconnect structure, where W1 is the transmission line width of the CPW, d0 is the spacing of the outer shield TSV, d1 is the spacing between the CPW signal line and the ground, r1 is the radius of the signal TSV, r2 is the radius of the TSV of the three-dimensional compensation structure, R1 is the radius of the pad connecting the CPW and the vertical via, R2 is the hollowing radius of the coaxial-like structure, R3 is the radius of the pad connecting the solder ball, and L1 is the length of the compensation structure.

[0019] Figure 6 It is an explanation of the parameters of the lower layer board in the three-dimensional interconnect structure, where W2 is the transmission line width of the lower layer CPW, W3 is the width of the silicon interposer, L3 is the length of the silicon interposer, d0 is the spacing of the outer shield TSV, d2 is the spacing between the lower layer CPW signal line and the ground, and R2 is the hollowing radius of the coaxial-like structure.

[0020] Figure 7 S of the interconnect structure with or without a three-dimensional compensation structure 11 and S 22 Parameter comparison

[0021] Figure 8 S of the interconnect structure with or without a three-dimensional compensation structure 21 Parameter comparison Specific implementation manners

[0022] The invention innovatively proposes a broadband double-layer interconnect structure adopting a three-dimensional compensation structure, and realizes three-dimensional integration through the advanced packaging process of a silicon interposer. The designed interconnect structure can be highly compatible with electromagnetic simulation software such as HFSS, providing a reliable solution for high-frequency signal transmission of radio frequency microsystems

[0023] The broadband double-layer interconnect structure of the present invention (as shown in Figure 2 and Figure 3 ) includes two layers of silicon interposers, a solder ball structure between layers, and a three-dimensional compensation structure in the upper layer board. For the radio frequency signal transmission path in this interconnect structure, it specifically shows that: the top coplanar waveguide (CPW) transmits the signal to a quasi-coaxial structure composed of a central signal through-silicon via (TSV) and an annular shield TSV array, and then transmits it to the CPW in the lower silicon interposer through the solder ball structure (diameter 250μm) to complete cross-board signal transmission. Among them, a three-dimensional compensation structure (as shown in Figure 4 ) is integrated at one end of the upper CPW close to the quasi-coaxial transition structure, forms capacitance compensation through the square metal of the UM1 layer and the CPW of the UM2 layer, and cooperates with the TSV array penetrating to the DM1 layer to realize the grounding path. Finally, this broadband double-layer interconnect structure can achieve a broadband interconnect effect with a return loss of ≤ -20 dB from 0 to 33 GHz (as shown in Figure 7 and Figure 8 ), and the fluctuation of the in-band insertion loss is reduced by 11.6% compared with that without the compensation structure

[0024] The broadband double-layer interconnect structure proposed by the present invention is realized based on the silicon interposer process. The silicon interposer uses a high-resistance silicon (Si) material with a dielectric constant of 11.7 and a resistivity > 2000 Ω·cm, and the substrate thickness is 200μm. For the detailed lamination description, see Figure 1As shown, the metal layers UM1, UM2, UM3, DM1, and DM2 use Cu as the conductive material with a thickness of 5 μm. The filling medium between the metal layers uses polyimide (PI), corresponding to the UP1, UP2, and DP1 layers with a thickness of 7 μm. Both sides of the silicon interposer use silicon dioxide (Silicon dioxide, Sio2), corresponding to the Usio2 and Dsio2 layers with a thickness of 3 μm. The vias passing through the high-resistance silicon are through-silicon vias (TSVs) with a height of 200 μm of the silicon substrate height and a diameter of 30 μm.

[0025] The broadband double-layer interconnect structure is as Figure 2 and Figure 3 shown. This double-layer interconnect structure consists of two layers of silicon interposers and interlayer SnAgCu solder balls. The top-layer CPW constructs a coaxial-like vertical transition structure with the central signal TSV and the annular ground TSV array, and is connected to the bottom-layer CPW through solder balls to complete cross-board interconnection. Among them, the coaxial-like transition structure undergoes a transmission mode conversion of CPW - coaxial-like - CPW, resulting in a large impedance change. Therefore, it is necessary to compensate and optimize it to ensure transmission stability and matching performance.

[0026] The present invention realizes broadband impedance matching optimization by integrating a three-dimensional compensation structure at the end of the coplanar waveguide (CPW) in the coaxial-like transition region. As Figure 4 shown, this compensation structure is composed of a square conductive metal and a through-silicon via (TSV) in cooperation: the square metal is located in the UM1 layer, forming a capacitance compensation mechanism with the upper-layer UM2 transmission line; the lower-layer TSV penetrates the Usio2, Si, and Dsio2 layers to the DM1 layer for grounding. Through simulation and optimization with an electromagnetic full-wave numerical analysis software, the detailed parameter design of the three-dimensional interconnect structure can be obtained. Figure 5 and Figure 6 The parameters in are: W1 = 0.1 mm, W2 = 0.12 mm, W3 = 2 mm, L1 = 0.05 mm, L2 = 3.3 mm, d0 = 0.1 mm, d1 = 0.05 mm, d2 = 0.06 mm, r1 = 0.15 mm, r2 = 0.15 mm, R1 = 0.1 mm, R2 = 0.25 mm, D1 = 0.6 mm, D2 = 1.32 mm. Finally, this structure can introduce a resonance point with a return loss of -51 dB at 17.59 GHz. By adding this three-dimensional compensation structure, the bandwidth of the vertical interconnect structure is effectively expanded.

[0027] Finally, the simulation results of this three-dimensional interconnect structure are as Figure 7 and Figure 8 shown. In the range of 10 - 33 GHz, the S 11 and S 22≤ -20 dB, while the original structure is only less than -15 dB, showing a significant improvement of 5 dB. Meanwhile, in the range of 10 - 33 GHz, the insertion loss fluctuation S with capacitive compensation 21 is also significantly improved compared with the original structure, decreasing from 0.302 dB to 0.267 dB, a reduction of 11.6%.

Claims

1. A broadband double-layer interconnection structure based on a silicon interposer process, the structure comprising: Top silicon interposer, interlayer solder ball layer, bottom silicon interposer; The top silicon interposer and the bottom silicon interposer are two independent structures; The top silicon interposer successively includes, from top to bottom: UM2 layer, UP1 layer, UM1 layer, Usio2 layer, Si layer, Dsio2 layer, DM1 layer, DP1 layer, DM2 layer; the UM1 layer, UM2 layer, DM1 layer, and DM2 layer use Cu as the conductive material, the Usio2 layer and the Dsio2 layer are made of Sio2 material, the UP1 layer and the DP1 layer are polyimide, and the DM2 layer consists of multiple independent metal pads; an input microstrip and an output microstrip are etched along the midline of the UM2 layer, the left end of the input microstrip is flush with the left end of the UM2 layer, the right end of the input microstrip is connected to a pad, the right end of the output microstrip is flush with the right end of the UM2 layer, the left end of the output microstrip is connected to a pad, and the pads corresponding to the input microstrip and the output microstrip are connected to the corresponding metal pads HP1 and metal pad HP2 in the DM2 layer through silicon vias, and isolation rings are arranged at the positions of the silicon vias passing through the DM1 layer; one column of metal vias is arranged on each side of the input microstrip and the output microstrip, the upper ends of the metal vias are connected to the UM2 layer, and the lower ends are connected to the DM1 layer to prevent the leakage of transmitted electromagnetic waves; The top silicon interposer also includes an input compensation structure and an output compensation structure with the same structure. The input compensation structure and the output compensation structure both include a top cap and a metal vertical hole. The top cap is etched from the UM1 layer and is connected to the DM1 layer through the metal vertical hole; the input compensation structure is located below the input microstrip, and the output compensation structure is located below the output microstrip; The bottom silicon interposer successively includes, from top to bottom: UM3 layer, UP2 layer, UM2 layer, UP1 layer, UM1 layer, Usio2 layer, Si layer, Dsio2 layer, DM1 layer; the UM3 layer, UM2 layer, UM1 layer, and DM1 layer use Cu as the conductive material, the Usio2 layer and the Dsio2 layer are made of Sio2 material, the UP2 layer and the UP1 layer are polyimide, and the UM3 layer consists of more than two independent metal pads; a transmission microstrip is etched along the midline of the UM2 layer, and the left end and the right end of the transmission microstrip are connected to the corresponding metal pads HP3 and metal pad HP4 of the UM3 layer through metal vias; the positions of the metal pads HP3 and metal pad HP4 correspond to the positions of the metal pads HP1 and metal pad HP2; a circle of metal vias is arranged around the transmission microstrip, the upper ends of the metal vias are connected to the UM2 layer, and the lower ends are connected to the DM1 layer to prevent the leakage of transmitted electromagnetic waves; The interlayer solder ball layer includes more than two metal solder balls. The upper end of each metal solder ball is connected to one metal pad in the DM2 layer of the top silicon interposer, and the lower end is connected to one metal pad in the UM3 layer of the bottom silicon interposer; at least one metal solder ball has its upper end connected to the metal pad HP1 and its lower end connected to the metal pad HP3, and at least one metal solder ball has its upper end connected to the metal pad HP2 and its lower end connected to the metal pad HP4.

2. The broadband double-layer interconnect structure based on the silicon interposer process according to claim 1, wherein The thickness of the UM1 layer, UM2 layer, DM1 layer, and DM2 layer in the top silicon interposer is 5 μm; the line width of the input microstrip and the output microstrip is 0.1 mm, and the line distance from the ground plane is 0.05 mm.

3. A broadband double-layer interconnect structure based on a silicon interposer process according to claim 1, characterized in that, The thickness of the UM3 layer, UM2 layer, UM1 layer, and DM1 layer in the bottom silicon interposer is 5 μm; the line width of the transmission microstrip is 0.12 mm, and the line distance from the ground plane is 0.05 mm.

4. A broadband double-layer interconnect structure based on a silicon interposer process as claimed in claim 1, characterized in that, The height of the through-silicon via is 200 μm, and the diameter is 30 μm.

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