Data processing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium, is suitable for a processor comprising a first integrated circuit unit and a second integrated circuit unit, and comprises the following steps: acquiring to-be-transmitted data and providing the to-be-transmitted data to the first integrated circuit unit; the verification information of the data to be transmitted is generated, the verification information comprises state information of a forward error correction code, data information of the forward error correction code and state information of cyclic redundancy check, and the data information of the forward error correction code and error data in the data to be transmitted have a corresponding relation; and sending the verification information and the to-be-transmitted data to the second integrated circuit unit, so that the second integrated circuit unit sends the to-be-transmitted data to the second integrated circuit unit under the condition that the state information of the forward error correction code is error-free or correctable error and the state information of the cyclic redundancy check is error-free. And a correct cyclic redundancy check code is calculated based on the received data to be transmitted and the data information of the forward error correction code, so that efficient data transmission is realized.

Description

Technical Field

[0001] The present disclosure relates to a data processing method, apparatus, electronic device, and storage medium. Background Art

[0002] With the rapid development of information technology, applications such as big data, cloud computing, and high-performance computing have put forward more urgent requirements for data transmission speed and efficiency. Traditional data transmission methods show many limitations when dealing with these requirements. Especially when performing Forward Error Correction (FEC) verification, the bandwidth limitation and high latency problems in the transmission process become particularly obvious. When performing FEC verification, the system needs additional time to wait for the calculation and verification of error correction codes, which not only reduces the efficiency of data transmission but also increases the latency of the transmission process. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a data processing method applicable to a processor including a first integrated circuit unit and a second integrated circuit unit. The data processing method includes: obtaining data to be transmitted and providing it to the first integrated circuit unit; generating verification information for the data to be transmitted, where the verification information includes the status information of the forward error correction code, the data information of the forward error correction code, and the status information of the cyclic redundancy check. There is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted; sending the verification information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit can calculate the correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or the error can be corrected, and the status information of the cyclic redundancy check is error-free.

[0004] For example, in the data processing method provided by at least one embodiment of the present disclosure, sending the verification information and the data to be transmitted to the second integrated circuit unit together includes: splitting the data to be transmitted into N data packets in units of a preset byte width, where the verification information is placed at the end of the Nth data packet, the Nth data packet is the data with the last transmission order in the data to be transmitted, and N is an integer greater than 1; and sending the N data packets to the second integrated circuit unit.

[0005] For example, in the data processing method provided by at least one embodiment of the present disclosure, the data information of the forward error correction code includes the error position information that needs to be corrected in the data to be transmitted and the correct data corresponding to the error position after correction.

[0006] For example, in the data processing method provided by at least one embodiment of the present disclosure, the preset byte width is either 64 bytes or 128 bytes.

[0007] For example, the data processing method provided by at least one embodiment of the present disclosure, wherein the bit width of the status information of the forward error correction code is 2 bits, the bit width of the status information of the cyclic redundancy check is 1 bit, and the bit widths of the error location information to be corrected and the correct data corresponding to the error location after correction are each 1 byte.

[0008] For example, the data processing method provided by at least one embodiment of the present disclosure, wherein the correct cyclic redundancy check code is calculated at one time based on the received data to be transmitted and the data information of the forward error correction code, including: calculating an intermediate cyclic redundancy check code of the received data to be transmitted, and performing an exclusive OR operation on the intermediate cyclic redundancy check code and the correct data corresponding to the data to be transmitted after correction to obtain the correct cyclic redundancy check code.

[0009] For example, the data processing method provided by at least one embodiment of the present disclosure, wherein the status information of the forward error correction code and the status information of the cyclic redundancy check are represented by different data bits of the same byte; or the status information of the forward error correction code and the status information of the cyclic redundancy check are each represented by one byte.

[0010] For example, the data processing method provided by at least one embodiment of the present disclosure, wherein in response to the number of groups of the error location information to be corrected in the data to be transmitted and the correct data corresponding to the error location after correction being greater than or equal to 0, the data capacity of the data to be transmitted is adjusted to make up the Nth data packet to 64 bytes or 128 bytes.

[0011] For example, the data processing method provided by at least one embodiment of the present disclosure, wherein the status information of the forward error correction code further includes an uncorrectable error, and in response to the status information of the forward error correction code being an uncorrectable error or the status information of the cyclic redundancy check being in error, the check information of the data to be transmitted is regenerated.

[0012] At least one embodiment of the present disclosure further provides a data processing device, which is applicable to a network-on-chip including a first integrated circuit unit and a second integrated circuit unit. The data processing device includes: an acquisition module configured to acquire data to be transmitted and provide it to the first integrated circuit unit; a generation module configured to generate check information of the data to be transmitted, where the check information includes status information of a forward error correction code, data information of the forward error correction code, and status information of a cyclic redundancy check, and there is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted; and a sending module configured to send the check information together with the data to be transmitted to the second integrated circuit unit, so that the second integrated circuit unit can calculate a correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or an error that can be corrected, and the status information of the cyclic redundancy check is error-free.

[0013] At least one embodiment of the present disclosure further provides an electronic device, including: a processor; a memory including one or more computer program modules; wherein, one or more computer program modules are stored in the memory and configured to be executed by the processor, and one or more computer program modules are used to execute the data processing method of any one of the above embodiments.

[0014] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a computer, the data processing method of any one of the above embodiments is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0016] Figure 1A Shows a schematic diagram of the frame structure of a data transmission frame;

[0017] Figure 1B Shows a schematic diagram of the frame structure of another data transmission frame;

[0018] Figure 2 Shows a schematic flowchart of the data processing method of at least one embodiment of the present disclosure;

[0019] Figure 3 Shows a schematic diagram of the frame structure of a data transmission frame of at least one embodiment of the present disclosure;

[0020] Figure 4Shows a schematic diagram of the frame structure of another data transmission frame according to at least one embodiment of the present disclosure;

[0021] Figure 5 Shows a schematic diagram of a data processing device according to at least one embodiment of the present disclosure;

[0022] Figure 6 Shows a schematic diagram of an electronic device according to at least one embodiment of the present disclosure;

[0023] Figure 7 Shows a schematic diagram of the structure of a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0024] Figure 8 Shows a schematic diagram of another electronic device according to at least one embodiment of the present disclosure. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "Connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0027] Forward Error Correction (FEC) is a technique for error control achieved through data redundancy. Its core feature lies in the ability to detect and correct data errors occurring during transmission at the receiving end without relying on a retransmission mechanism. In an FEC system, the sender adds redundant check information to the original data through a predefined coding algorithm (such as Reed-Solomon codes, convolutional codes, or low-density parity-check codes) to form an encoded data packet with error-correction capabilities. The receiving end analyzes the redundant information using a decoding algorithm to locate and correct bit errors within a certain number, thereby enhancing the reliability of the communication link. FEC technology is particularly suitable for high-latency or one-way transmission scenarios (such as satellite communication, broadcast systems) as it avoids the efficiency losses caused by the absence or high latency of the feedback channel in the traditional Automatic Repeat reQuest (ARQ) mechanism.

[0028] For FEC error-correcting codes, the bit width they occupy is not fixed. It depends on the specific FEC scheme selected and the coding rate. Different FEC coding methods and parameter settings will result in different amounts of redundant information, thus affecting the number of bytes occupied by the final FEC data. For example, the bit width of the FEC error-correcting code can be 6 bytes, 8 bytes, 16 bytes, etc. based on the actual design.

[0029] Cyclic Redundancy Check (CRC) is a lightweight error-detection algorithm based on polynomial division. It verifies data integrity by generating a check code of a fixed length. During the CRC process, the sender treats the data to be transmitted as a binary polynomial and performs modulo-2 division with a predefined generating polynomial. The resulting remainder is appended to the end of the original data as the CRC check code. The receiving end performs the same polynomial operation on the data. If the calculated result does not match the received check code, it is determined that there are bit errors during transmission. The CRC algorithm features high computational efficiency and strong error-detection capabilities (it can detect burst errors and random errors) and is widely used in scenarios such as data storage, network protocols (such as Ethernet, Wi-Fi), and serial communication. However, its design goal is error detection rather than correction, and it usually needs to be combined with a retransmission mechanism to achieve complete error control.

[0030] For the bit width of CRC check codes, the common ones mainly include four types: CRC-8, CRC-16, CRC-32, and CRC-64. CRC-8 means generating an 8-bit (1-byte) check value, which is suitable for situations where high computing speed is required, the data volume is small, or the error detection requirement is not so strict, such as some simple internal communication protocols in embedded systems; CRC-16 means generating a 16-bit (2-byte) check value, providing higher reliability than CRC-8, and is suitable for medium-scale data transmission or storage scenarios, such as being used in industrial control networks and some serial communication protocols; CRC-32 means generating a 32-bit (4-byte) check value, which is one of the most widely used CRC standards currently, with high error detection ability, and is applicable to most data transmission environments that require high reliability, such as Ethernet frame check sequence (FCS), checks in ZIP file formats, etc.; CRC-64 means generating a 64-bit (8-byte) check value, providing an extremely high error detection rate, and is mainly used in occasions where very strict requirements for data integrity are needed, such as large data transmission, certain scientific computing fields, etc.

[0031] Although FEC is mainly used to correct errors, for further enhancing reliability, it is often used in combination with CRC. CRC is responsible for quickly detecting errors in data packets, while FEC attempts to repair these errors. If CRC detects errors that cannot be repaired by FEC, a retransmission may be required.

[0032] There are two typical structures for the current data transmission frame structure: one is to send data in units of 128 bytes (Byte), and the other is to send data in units of 64 bytes (Byte). In both of these structures, FEC and CRC calculations are required during the data transmission process. At the sending end, it is necessary to encode the data to generate redundant information so that the receiving end can detect and correct errors. It is also necessary to perform CRC calculations on the data and append the generated check code to the data for transmission together. At the receiving end, if data correction is required, CRC needs to be recalculated.

[0033] The following combines Figure 1A and Figure 1BThe specific execution processes and logics of the above FEC and CRC during data transmission are introduced. And unless otherwise specified, the bit width of the FEC error correction code is 6 bytes and the bit width of the CRC check code is 64 bits (i.e., 8 bytes) in the following description. And by way of example, the following description also takes the data transmission process occurring at the sending end of the first integrated circuit unit and the receiving end of the second integrated circuit unit in the processor as an example. However, it should be noted that each chip has a sending end and a receiving end, and this data transmission process can also occur at the sending end of the second integrated circuit unit and the receiving end of the first integrated circuit unit in the processor, and the present disclosure does not limit this. And the embodiments of the present disclosure are described by taking the first integrated circuit unit as the first chip and the second integrated circuit unit as the second chip as an example. It should be noted that the first integrated circuit unit and the second integrated circuit unit of the present disclosure can also be the first packaging unit and the second packaging unit. Among them, the first packaging unit and the second packaging unit can include 2 or 4 chips, and the embodiments of the present disclosure do not limit this.

[0034] Figure 1A Shows a schematic diagram of the frame structure of a data transmission frame.

[0035] As Figure 1A shown, the unit transmission bit width of each data transmission frame (i.e., data packet) is 128 bytes. For example, if the user data to be transmitted is 242 bytes, then the user data can be divided into the data sub-packet 2 in data packet 1 and data packet 2 (not shown in the figure) as Figure 1A shown. The bit widths of data packet 1 and data packet 2 are both 128 bytes. Among them, on the basis of including 114 bytes of data sub-packet 2, data packet 2 also includes 6 bytes of FEC information and 8 bytes of CRC information at the end. During data transmission, the data link layer sequentially transmits data packet 1 and data packet 2 of 128 bytes.

[0036] For the transmitting end of the first chip, for example, in the data link layer, for the first time, only packet 1 containing 128 bytes of user data is transmitted, without FEC information and CRC information; for the second time, packet 2 containing 114 bytes of user data, 6 bytes of FEC information, and 8 bytes of CRC information is transmitted. During the first transmission, only one clock cycle is required to complete; during the second transmission, first, the CRC information corresponding to the user data of (128 bytes + 114 bytes) needs to be generated and appended to the data tail of data sub-packet 2. Subsequently, the user data of (128 bytes + 114 bytes) and 8 bytes of CRC information are FEC encoded to generate redundant error correction codes (such as parity bits, convolutional codes, etc.) and appended to the tail of the CRC together. Since generating CRC information and FEC information requires additional time overhead, the second transmission process requires two clock cycles to complete, one clock cycle to sequentially generate CRC information and FEC information in order, and another clock cycle to transmit packet 2 containing 114 bytes of user data, 6 bytes of FEC information, and 8 bytes of CRC information to the receiving end of the second chip. Therefore, the transmitting end needs three clock cycles to complete data transmission.

[0037] For the receiving end of the second chip, first, the received packet 1 and packet 2 are decoded to obtain user data, FEC information, and CRC information, which requires two clock cycles; then, the FEC information is decoded and error corrected, and the CRC information is calculated and compared with the CRC information at the transmitting end, which requires one clock cycle. When there is no error in the decoded FEC information and the recalculated CRC information is the same as the CRC information at the transmitting end, this situation indicates that no error has occurred during the data transmission process, and the user data can be directly used or forwarded by the second chip. Therefore, at least three clock cycles are required when no error is detected.

[0038] If the FEC information reports "correctable errors" after decoding, this means that the received user data needs to be error corrected. When the error occurs during the second transmission, the CRC calculation needs to be performed using the error-corrected data. If the CRC calculation is correct (i.e., the same as the CRC information at the transmitting end), the data can be used or forwarded by the second chip. This situation adds an error correction process and requires an additional one clock cycle to perform the error correction operation, and a total of four clock cycles are required to complete data reception; if the CRC calculation is incorrect, it means that the FEC has not fully corrected the error in the second transmission data. Then, the data of the second transmission (i.e., the above-mentioned packet 2) needs to be retransmitted, and then the FEC decoding and error correction and CRC calculation processes are completed. If the CRC calculation is always incorrect, the data will be continuously retransmitted until the CRC calculation is correct and the data can be used or forwarded. This situation greatly increases the time overhead at the receiving end.

[0039] When an error occurs during the first transmission, similarly, the data needs to be corrected before calculating the CRC. If the CRC calculation is correct, the data can be used or forwarded; if the CRC calculation is incorrect, it means that the FEC may not have fully corrected the errors in the first transmission data, or it may not have corrected the errors in the second transmission data. Therefore, it is necessary to retransmit the data of the first and second transmissions (i.e., data packet 1 and data packet 2), and then complete the above-mentioned FEC decoding and error correction and CRC calculation process until the CRC calculation is correct before the data can be used or forwarded. In this case, the amount of retransmitted data becomes larger, and the time overhead for both the sender and the receiver increases significantly.

[0040] Figure 1B Fig. shows a schematic diagram of the frame structure of another data transmission frame.

[0041] As Figure 1B shown, the unit transmission bit width of each data transmission frame (i.e., data packet) is 64 bytes. For example, if the user data to be transmitted is 242 bytes, then the user data can be divided into data sub-packet 4 in data packet 1, data packet 2, data packet 3, and data packet 4 (not shown in the figure) as Figure 1B shown. The bit widths of data packet 1 - data packet 3 are all 64 bytes. Among them, data packet 4 includes 6 bytes of FEC information and 8 bytes of CRC information at the end on the basis of including 50 bytes of data sub-packet 4. During the data transmission process, the data link layer sequentially transmits data packets 1 / 2 / 3 / 4 of 64 bytes.

[0042] Similarly, for the data transmission situation with a unit transmission bit width of 64 bytes, it is similar to the above-mentioned situation with a unit transmission bit width of 128 bytes. For the sender of the first chip, it takes at least five clock cycles to complete the data transmission; for the receiver of the second chip, when the FEC reports a CE, its additional time overhead and the possible amount of retransmitted data become larger.

[0043] The inventors of the present disclosure have noticed that in the related design, if a CE is reported at the receiver, the CRC must obtain all the corrected correct data to calculate the correct CRC information for subsequent use. If the CRC calculation is incorrect, the sender needs to continuously retransmit the data and repeat the FEC decoding and error correction and CRC calculation process until the CRC calculation is correct. On the one hand, this process generates a large amount of time overhead and increases the transmission delay; on the other hand, the CRC needs to be calculated after each data error correction, reducing the transmission bandwidth efficiency.

[0044] At least one embodiment of the present disclosure provides a data processing method, which is applicable to a processor including a first integrated circuit unit and a second integrated circuit unit. The data processing method includes: acquiring data to be transmitted and providing it to the first integrated circuit unit; generating check information for the data to be transmitted, where the check information includes the status information of the forward error correction code, the data information of the forward error correction code, and the status information of the cyclic redundancy check, and there is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted; and sending the aforementioned check information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit can calculate the correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or the error can be corrected and the status information of the cyclic redundancy check is error-free.

[0045] At least one embodiment of the present disclosure further provides a data processing device, an electronic device, and a computer storage medium corresponding to the above data processing method.

[0046] The data processing method provided by at least one embodiment of the present disclosure reduces the additional time overhead caused by waiting for FEC check without sacrificing data reliability, thereby achieving true high-bandwidth transmission. At the same time, by allowing the receiving end to perform error detection and correction while receiving data, the total delay of data transmission is greatly reduced.

[0047] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0048] Figure 2 The flowchart of the data processing method according to at least one embodiment of the present disclosure is shown. As Figure 2 shown, the data processing method provided by the embodiment of the present disclosure includes steps S210 to S230.

[0049] Step S210: Acquire data to be transmitted and provide it to the first integrated circuit unit.

[0050] Step S220: Generate check information for the data to be transmitted, where the check information includes the status information of the forward error correction code, the data information of the forward error correction code, and the correct cyclic redundancy check information, and there is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted.

[0051] Step S230: Send the check information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit can calculate the correct cyclic redundancy check information at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or an error that can be corrected, and the status information of the cyclic redundancy check is error-free.

[0052] For step S220, for example, in a possible implementation manner, the status information of the forward error correction code includes no error or an error CE that can be corrected. For the sending end of the first chip, there is no longer an additional process of forward error correction encoding the data. It only needs to append the status information after forward error correction encoding to the check information. For example, this status information can be understood as a status flag bit of an FEC information, indicating the error situation in the data to be transmitted, so that the receiving end of the second chip can decode the error situation in the received data in a timely manner, saving time overhead. For example, the status information of the forward error correction code can be represented by 2 bits (i.e., 2-bit binary numbers), and "00" can be used to represent no error, and "01" can be used to represent an error that can be corrected.

[0053] For example, in a possible implementation manner, the data information of the forward error correction code includes the error position information that needs to be corrected in the data to be transmitted and the correct data corresponding to the error position after correction. For example, the data to be transmitted is divided into multiple data packets (e.g., 8 packets) according to the unit transmission byte width of the link packet (e.g., 64 bytes). After FEC error correction, it is known that there are three error positions in the data to be transmitted. The first is at the 35th byte, the second is at the 46th byte, and the third is at the 54th byte. Exemplarily, the error position information that needs to be corrected in the data to be transmitted can be represented by one byte (8-bit binary numbers). Among them, the 35th byte can be represented by the binary number "00100011", the 46th byte can be represented by the binary number "00101110", and the 54th byte can be represented by the binary number "00110110". To reduce the total data width in data transmission, for example, the above binary numbers can be converted into hexadecimal numbers for representation. Specifically, "00100011" can be represented as "0x23", "00101110" can be represented as "0x2E", and "00110110" can be represented as "0x36".

[0054] For example, in a possible implementation, the correspondence between the data information of the forward error correction code and the data with errors in the data to be transmitted includes: there is a mapping relationship between the error position information to be corrected in the data to be transmitted and the specific corresponding data packet number in the data to be transmitted. For example, the 35th byte belongs to data packet 2, the 46th byte belongs to data packet 5, and the 54th byte belongs to data packet 1. For the error position information to be corrected in the data to be transmitted, the corresponding data packet number information is mapped and carried.

[0055] Since the data transmission process in the embodiments of the present disclosure uses bytes as the smallest data unit, the above-mentioned correct data corresponding to the error position after correction also occupies the bit width of one byte. To reduce the data width, the corrected correct data is also represented in hexadecimal numbers. For example, if the actual transmitted data of the above 35th byte is "0x24" and the corresponding corrected data is "0x25", then the corresponding data structure in the check information should be represented as "0x23 0x25". For the remaining two error positions, the representation method can be deduced by analogy and will not be elaborated here.

[0056] For example, in a possible implementation, the status information of the cyclic redundancy check in the check information occupies a bit width of 1 bit (i.e., 1 binary digit). Specifically, "0" can be used to indicate that the check passes, and "1" can be used to indicate that the check fails.

[0057] For example, in a possible implementation, the status information of the above forward error correction code and the status information of the cyclic redundancy check are represented by different data bits of the same byte; or the status information of the above forward error correction code and the status information of the cyclic redundancy check are respectively represented by one byte.

[0058] Specifically, since the bit width of the status information of the above forward error correction code is only 2 bits, and the bit width of the status information of the cyclic redundancy check is also only 1 bit, and one byte has 8 data bits, therefore, to make the best use of the data utilization of the check information, the status information of the forward error correction code and the status information of the cyclic redundancy check can be represented by different binary data bits of the same byte. For example, the 2-bit status information of the forward error correction code is placed in the lower 2 bits of the byte (i.e., the 0th bit and the 1st bit, by default, the rightmost side of the byte is the lowest bit and the leftmost side is the highest bit), and the status information of the cyclic redundancy check is placed in the 2nd bit of the byte, and the data of the remaining 3rd bit to 7th bit is filled with "0". It should be noted that the specific positions of the status information of the forward error correction code and the status information of the cyclic redundancy check in the same byte can be adjusted arbitrarily, and the embodiments of the present disclosure do not limit this.

[0059] For another example, the status information of the above forward error correction code and the status information of the cyclic redundancy check can be represented by one byte respectively. If there are at least 2 bytes of remaining data bit widths after placing the data information of the above forward error correction code in the check information, in this case, the 2-bit status information of the forward error correction code and the 1-bit status information of the cyclic redundancy check can be represented by one byte respectively. For example, place the 2-bit status information of the forward error correction code in the lowest 2 bits of one byte (i.e., bit 0 and bit 1), and place the 1-bit status information of the cyclic redundancy check in the lowest bit of another byte (i.e., bit 0). It should be noted that the specific positions of the status information of the forward error correction code and the cyclic redundancy check in their respective different bytes can be adjusted arbitrarily, and the embodiments of the present disclosure do not limit this.

[0060] At least one embodiment of the present disclosure generates the status flag bit information of FEC and CRC on the one hand, and generates the error position in the FEC error correction and the corresponding data to be corrected on the other hand, reducing the waiting process for error correction at the sending end and shortening the transmission delay.

[0061] For step S230, for example, in a possible implementation manner, sending the check information and the data to be transmitted to the second chip together includes: splitting the data to be transmitted into N data packets in units of a preset byte width, where the check information is placed at the end of the Nth data packet, and the Nth data packet is the data with the last transmission order among the data to be transmitted, and N is an integer greater than 1; and sending the N data packets to the second chip.

[0062] For example, the preset byte width can be understood as the data transmission frame length in the inter-chip interconnection communication process. In the chip interconnection communication, the selection of the frame length size is a key design parameter, which affects the system performance, delay, bandwidth utilization rate and error handling ability. For example, the preset byte width is any one of 64 bytes or 128 bytes. However, it should be noted that the preset byte width can be adjusted through the configuration register based on the actual design situation, and the embodiments of the present disclosure do not limit this.

[0063] For example, taking the length of the data to be transmitted as 498 bytes and the preset byte width as 64 bytes as an example, the data to be transmitted is split into 8 data packets. Among them, the 1st data packet is the one with the earliest transmission order, and the 8th data packet is the one with the latest transmission order. The check information is placed at the end of the 8th data packet. As mentioned above, since the FEC information and CRC information in the original related design occupy 14 bytes of data bit width (i.e., the FEC information occupies 6 bytes and the CRC information occupies 8 bytes), the reference data bit width of the check information is 14 bytes. Furthermore, the data bit widths of the 1st data packet - the 7th data packet are all filled with 64 bytes, while the 8th data packet includes 50 bytes of the remaining data to be transmitted and 14 bytes of check information. After splitting the data to be transmitted, the 8 data packets are sequentially sent to the receiving end of the second chip.

[0064] For example, in a possible implementation manner, in response to the number of groups of the error position information to be corrected and the correct data corresponding to the error position in the above-mentioned data to be transmitted being greater than or equal to 0, adjust the data capacity of the data to be transmitted to fill the Nth data packet to 64 bytes or 128 bytes.

[0065] Specifically, still taking the length of the data to be transmitted as 498 bytes and the preset byte width as 64 bytes as an example, if the number of groups of the error position information to be corrected and the correct data corresponding to the error position in the data to be transmitted is 3, then the data information of FEC in the check information occupies 6 bytes of data bit width, and the status information of FEC and the status information of CRC respectively occupy 1 byte of data bit width. For the check information, there are still 6 bytes of data bits in an idle state. For example, the length of the above-mentioned data to be transmitted can be dynamically adjusted to 504 bytes, and then the 8th data packet can contain 56 bytes of the remaining data to be transmitted to fill the preset byte width of 64 bytes.

[0066] For example, in another possible implementation manner, the above-mentioned remaining 6 bytes of idle data bits can be reserved for the system to store some specific information for use, so as to facilitate the system to do things such as storing integrity protection bits, and then some specific applications can be spread.

[0067] For example, in a possible implementation manner, based on the received data to be transmitted and the data information of the forward error correction code, calculate the correct cyclic redundancy check code at one time, including: calculating the intermediate cyclic redundancy check code of the received data to be transmitted, and performing exclusive OR processing on the intermediate cyclic redundancy check code and the correct data corresponding to the received data to be transmitted to obtain the correct cyclic redundancy check code.

[0068] For example, when the receiving end of the second chip decodes and obtains that the status information of the forward error correction code sent by the sending end is CE (i.e., there are errors in the received data), the receiving end does not need to first perform error correction on the received data and then calculate the CRC check code. Instead, it can directly calculate the CRC check code of the received data containing error data (referred to as the "intermediate CRC check code") while receiving the data. Then, based on the corrected correct data corresponding to the data to be transmitted in the forward error correction data information, the intermediate CRC check code is XORed with the corrected correct data to directly obtain the correct CRC check code of the data (i.e., the same as the CRC check code calculated by the sending end). Furthermore, the receiving end can use or forward the received data.

[0069] At least one embodiment of the present disclosure allows the receiving end to perform error detection and correction while receiving data, shortening the number of times the receiving end calculates the CRC check code to only 1 time, greatly reducing the delay of data transmission.

[0070] For example, in a possible implementation manner, the status information of the forward error correction code further includes uncorrectable errors. In response to the status information of the forward error correction code being uncorrectable errors or the status information of the cyclic redundancy check being in error, the check information of the data to be transmitted is regenerated.

[0071] For example, as described above, the status information of the forward error correction code can be represented by a 2-bit binary number. Furthermore, uncorrectable errors can be represented as "10", and "1" is used to indicate that the status information of the cyclic redundancy check is in error. When either of these two pieces of data does not meet the transmission conditions, the overall check information needs to be regenerated.

[0072] For example, in a possible implementation manner, after the second chip receives the data sent by the first chip, the second chip is not the final user end and needs to continue to forward the received data to the next level (such as the third chip). At this time, the second chip serves as the sending end and the third chip serves as the receiving end. When sending data, the second chip can attach the data information of the forward error correction code generated by the first chip that it has received to the check information of the data that it is going to forward to the third chip, without the need to calculate the FEC information again. This greatly saves the additional time overhead generated by the sending end for generating the FEC error correction code and realizes high-bandwidth transmission.

[0073] The data processing method provided by at least one embodiment of the present disclosure can reduce the additional time overhead generated by waiting for the generation of the FEC check at the data sending end without reducing the data reliability, realizing true high-bandwidth transmission. At the same time, at the data receiving end, by allowing error detection and correction while receiving data, the total delay of data transmission is greatly reduced.

[0074] Figure 3 The figure shows a schematic diagram of the frame structure of a data transmission frame according to at least one embodiment of the present disclosure.

[0075] As Figure 3 shown, the total length of the data to be transmitted is 242 bytes, and the unit frame length of the data transmission frame is 128 bytes. The data is split into a data packet 1 of 128 bytes and a data sub-packet 2 of 114 bytes. Among them, the data sub-packet 2 is included in a data packet 2 (not shown in the figure), and the check information is placed at the end of the data packet 2, including FEC status information, CRC status information, and multiple groups of error positions and corresponding error messages. Among them, each group of error positions and corresponding error messages are arranged adjacent to each other. For example, as Figure 3 shown, the error position 1 and the error message 1 are arranged adjacent to each other, the error position 2 and the error message 2 are arranged adjacent to each other, and so on. Figure 3The data bit width reserved for the check information is 14 bytes. The FEC status information occupies 2 bits, the CRC status information occupies 1 bit, and the error location and the corresponding error information each occupy 1 byte. For example, the FEC status information and the CRC status information can be represented by different data bits in 1 byte. In this way, the remaining 13-byte data bit width can accommodate at most 6 groups of error locations and error information, and the remaining 1-byte free space can be used to place some other specific information; or the FEC status information and the CRC status information are each represented by 1 byte. In this way, the remaining 12-byte data bit width can accommodate at most 6 groups of error locations and error information without remainder. Among them, to minimize the data length of each byte as much as possible, hexadecimal numbers can be used to represent each byte. For example, taking the case where the FEC status information and the CRC status information are each represented by 1 byte as an example, the FEC status information includes three types, namely no error, correctable error, and uncorrectable error. The low 2 bits in 1 byte are used to represent the FEC status information. Furthermore, no error is represented as "00000000" corresponding to hexadecimal "0x0"; the correctable error is represented as "00000001" corresponding to hexadecimal "0x1"; the uncorrectable error is represented as "00000010" corresponding to hexadecimal "0x2". The CRC status information includes two types, namely no error and error. Furthermore, no error can be represented as "00000000" corresponding to hexadecimal "0x0"; error can be represented as "00000010" corresponding to hexadecimal "0x1". For each error location 1, 2, …, n, on the basis of representing the specific byte number where the error occurs, it is also mapped to include the number of the specific data packet it belongs to. Thus, the specific location where the error occurs can be accurately located, and the correct data after correction follows each error location. It should be noted that if the number of groups of error locations and error information in the data to be transmitted is less than the above 6 groups, there will be free data bits in the check information. In this case, on the one hand, these free data bits can be used to store some specific information in the system to facilitate the system to do things such as storing integrity protection bits; on the other hand, the total capacity of the data to be transmitted can also be increased. For high-speed data (such as synchronous data) transmission, its corresponding total data transmission volume is generally in units of MB or GB. Therefore, we can adjust the total capacity of the data to be transmitted by configuring the register to fill the free data bits. For example, Figure 3 in which the FEC status information and the CRC status information each occupy 1 byte, and the number of groups of error locations and error information is only 3 groups. Thus, the check information only occupies 8 bytes out of 14 bytes, and there are 6 bytes of free space. Therefore, the data to be transmitted can be increased to 250 bytes. Correspondingly, data sub-packet 2 contains 120 bytes of data.

[0076] This disclosureFigure 3 In the illustrated embodiment, the status flag information of FEC and CRC, as well as the specific positions and data information corresponding to FEC error correction, are appended to the end of the data packet, reducing the additional time overhead generated at the sending end due to waiting for the calculation of the FEC error correction code and achieving high-bandwidth data transmission.

[0077] Figure 4 The frame structure diagram of another data transmission frame of at least one embodiment of the present disclosure is shown.

[0078] As Figure 4 As shown, the total length of the data to be transmitted is 242 bytes, and the unit frame length of the data transmission frame is 64 bytes. The data is split into data packets 1 / 2 / 3 of 64 bytes and a data sub-packet 4 of 50 bytes. Among them, the data sub-packet 4 is included in data packet 4 (not shown in the figure), and the check information is placed at the end of data packet 4, including FEC status information, CRC status information, and multiple groups of error positions and corresponding error information. For the frame structure of the 64-byte data transmission frame, its execution logic is similar to that of the above 128-byte data transmission frame and will not be elaborated here.

[0079] At least one embodiment of the present disclosure further provides a data processing device, which is applicable to a processor including a first integrated circuit unit and a second integrated circuit unit. The data processing device includes: an acquisition module configured to acquire the data to be transmitted and provide it to the first integrated circuit unit; a generation module configured to generate check information for the data to be transmitted, where the check information includes the status information of the forward error correction code, the data information of the forward error correction code, and the status information of the cyclic redundancy check, and there is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted; and a sending module configured to send the check information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit can calculate the correct cyclic redundancy check information at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or an error that can be corrected and the status information of the cyclic redundancy check is error-free.

[0080] Figure 5 The schematic diagram of the data processing device of at least one embodiment of the present disclosure is shown.

[0081] As Figure 5As shown in the figure, the data processing device 500 includes an acquisition module 510, a generation module 520, and a transmission module 530. For example, these units can be implemented by hardware (such as circuits) modules or software modules, etc. The same applies to the following embodiments and will not be elaborated here. For example, these units can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a field programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, as well as corresponding computer instructions.

[0082] The acquisition module 510 is configured to acquire the data to be transmitted and provide it to the first integrated circuit unit.

[0083] The generation module 520 is configured to generate check information for the data to be transmitted. The check information includes the status information of the forward error correction code, the data information of the forward error correction code, and the status information of the cyclic redundancy check. There is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted. For example, the generation module 520 can implement the above step S220, and its specific implementation method can refer to the relevant description of the above step S220 and will not be elaborated here.

[0084] The transmission module 530 is configured to transmit the check information together with the data to be transmitted to the second integrated circuit unit, so that the second integrated circuit unit can calculate the correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or the errors can be corrected, and the status information of the cyclic redundancy check is error-free. For example, the transmission module 530 can implement the above step S230, and its specific implementation method can refer to the relevant description of the above step S230 and will not be elaborated here.

[0085] The data processing device provided by at least one embodiment of the present disclosure can reduce the additional time overhead caused by waiting for the generation of FEC checks at the data sending end without reducing the data reliability, and achieve true high-bandwidth transmission. At the same time, at the data receiving end, by allowing error detection and correction while receiving data, the total delay of data transmission is greatly reduced.

[0086] It should be noted that for the sake of clarity and conciseness, the embodiments of the present disclosure do not show all the constituent units of the data processing device 500. To implement the necessary functions of the data processing device 500, those skilled in the art can provide and set other constituent units not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0087] At least one embodiment of the present disclosure also provides an electronic device. Figure 6A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0088] For example, as Figure 6 shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 is used to store non-transitory computer-readable instructions (such as one or more computer program modules). The processor 610 is used to run the computer program instructions, and when the computer program instructions are run by the processor 610, a data processing method provided by any embodiment of the present disclosure is executed. The memory 620 and the processor 610 may be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0089] The processor 610 may be a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), etc., which have data processing capabilities and / or program execution capabilities, and may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. For example, the central processing unit (CPU) may be of the X86 or ARM architecture, etc. The processor 610 may be a general-purpose processor or a special-purpose processor, and may control other components in the electronic device 600 to perform desired functions.

[0090] For example, the memory 620 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage media, and the processor 610 may run one or more computer program modules to implement various functions of the electronic device 600. Various application programs and various data, as well as various data used and / or generated by the application programs, etc., may also be stored in the computer-readable storage media.

[0091] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 600 may refer to the description of the data processing method in the above text, and will not be elaborated here.

[0092] At least one embodiment of the present disclosure also provides a non-transitory storage medium. Figure 7 A schematic structural diagram of a non-transitory storage medium according to at least one embodiment of the present disclosure is shown. For example, asFigure 7 As shown, the storage medium 700 non - temporarily stores computer - executable instructions 710, which can execute the data - processing method of any embodiment of the present disclosure when executed by a computer (including a processor).

[0093] For example, one or more computer instructions can be stored on the storage medium 700. Some of the computer instructions stored on the storage medium 700 can be, for example, instructions for implementing one or more steps in the above - mentioned data - processing method.

[0094] For example, the storage medium can include the storage component of a tablet computer, the hard disk of a personal computer, random access memory (RAM), read - only memory (ROM), erasable programmable read - only memory (EPROM), compact disc read - only memory (CD - ROM), flash memory, or any combination of the above - mentioned storage media, and can also be other applicable storage media. For example, the storage medium 700 can include the memory 620 in the aforementioned electronic device 600.

[0095] For the technical effects of the storage medium provided by the embodiments of the present disclosure, reference can be made to the corresponding descriptions of the data - processing method in the above embodiments, and details are not repeated here.

[0096] Figure 8 The figure shows a schematic diagram of another electronic device according to at least one embodiment of the present disclosure. Figure 8 The shown electronic device 800 is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0097] As Figure 8 shown, in some examples, the electronic device 800 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 810, which can include the data - processing device of any of the above embodiments. It can perform various appropriate actions and processes according to the program stored in the read - only memory (ROM) 820 or the program loaded from the storage device 880 into the random access memory (RAM) 830. In the RAM 830, various programs and data required for the operation of the computer system are also stored. The processor 810, the ROM 820, and the RAM 830 are connected to each other through a bus 840. The input / output (I / O) interface 850 is also connected to the bus 840.

[0098] For example, the following components can be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, such as, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; a communication device 890 which can also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 890 can allow the electronic device 800 to communicate with other devices wirelessly or wireline to exchange data and perform communication processing via a network such as the Internet. A driver (not shown in the figure) is also connected to the I / O interface 850 as needed. A removable medium (not shown in the figure), such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver as needed so that a computer program read from it can be installed into the storage device 880 as needed.

[0099] Although Figure 8 the electronic device 800 including various devices is shown, it should be understood that it is not required to implement or include all the shown devices. Instead, more or fewer devices can be implemented or included.

[0100] For example, the electronic device 800 can further include a peripheral interface (not shown in the figure), etc. The peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 890 can communicate with the network and other devices via wireless communication. The network can be, for example, the Internet, an intranet, and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any one of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), WiMAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0101] For example, the electronic device 800 can include any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or can be any combination of a data processing device and hardware. The embodiments of the present disclosure are not limited thereto.

[0102] For the present disclosure, the following points need to be noted:

[0103] (1) In the attached drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0104] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0105] The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data processing method, applicable to a processor including a first integrated circuit unit and a second integrated circuit unit, the data processing method comprising: Obtaining data to be transmitted and providing it to the first integrated circuit unit; Generating check information for the data to be transmitted, wherein the check information includes the status information of the forward error correction code, the data information of the forward error correction code, and the status information of the cyclic redundancy check, and there is a corresponding relationship between the data information of the forward error correction code and the data with errors in the data to be transmitted; Sending the check information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit, when the status information of the forward error correction code is error-free or an error that can be corrected, and the status information of the cyclic redundancy check is error-free, calculates the correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code.

2. The data processing method according to claim 1, wherein The sending the check information and the data to be transmitted to the second integrated circuit unit together includes: Splitting the data to be transmitted into N data packets in units of a preset byte width, wherein the check information is placed at the end of the Nth data packet, the Nth data packet is the data with the last transmission order in the data to be transmitted, and N is an integer greater than 1; and Sending the N data packets to the second integrated circuit unit.

3. The data processing method according to claim 2, wherein, The data information of the forward error correction code includes the error position information that needs to be corrected in the data to be transmitted and the correct data corresponding to the error position after correction.

4. The data processing method according to claim 3, wherein The preset byte width is either 64 bytes or 128 bytes.

5. The data processing method according to claim 3, wherein, The bit width of the status information of the forward error correction code is 2 bits, the bit width of the status information of the cyclic redundancy check is 1 bit, and the bit widths of the error position information that needs to be corrected and the correct data corresponding to the error position after correction are each 1 byte.

6. The data processing method according to claim 3, wherein, The calculating the correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code includes: Calculating an intermediate cyclic redundancy check code for the received data to be transmitted, and performing an exclusive OR operation on the intermediate cyclic redundancy check code and the correct data corresponding to the correction in the data to be transmitted to obtain the correct cyclic redundancy check code.

7. The data processing method according to claim 5, wherein, The status information of the forward error correction code and the status information of the cyclic redundancy check are represented by different data bits of the same byte; or The status information of the forward error correction code and the status information of the cyclic redundancy check are each represented by one byte.

8. The data processing method according to claim 4, wherein, In response to the number of groups of the error position information that needs to be corrected in the data to be transmitted and the correct data corresponding to the error position after correction being greater than or equal to 0, adjusting the data capacity of the data to be transmitted to fill the Nth data packet to 64 bytes or 128 bytes.

9. The data processing method according to claim 2, wherein, The status information of the forward error correction code further includes an error that cannot be corrected. In response to the status information of the forward error correction code being an uncorrectable error or the status information of the cyclic redundancy check being in error, the check information of the data to be transmitted is regenerated.

10. A data processing device, applicable to a processor including a first integrated circuit unit and a second integrated circuit unit, the data processing device comprising: An acquisition module configured to acquire data to be transmitted and provide it to the first integrated circuit unit; A generation module configured to generate check information of the data to be transmitted, wherein the check information includes status information of a forward error correction code, data information of the forward error correction code, and status information of a cyclic redundancy check, and wherein there is a correspondence between the data information of the forward error correction code and the data with errors in the data to be transmitted; and A sending module configured to send the check information and the data to be transmitted to the second integrated circuit unit together, so that the second integrated circuit unit can calculate a correct cyclic redundancy check code at one time based on the received data to be transmitted and the data information of the forward error correction code when the status information of the forward error correction code is error-free or a correctable error and the status information of the cyclic redundancy check is error-free.

11. An electronic device, comprising: A processor; A memory including one or more computer program modules; Wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules are used to execute the data processing method according to any one of claims 1-9.

12. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein, When the computer-executable instructions are executed by a computer, the data processing method according to any one of claims 1-9 is executed.

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