Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The manufacturing method comprises the steps that a substrate is provided, a gate structure and side wall structures on the two sides are formed on the substrate, and a lightly doped region and a heavily doped region are formed in the portions, on the two sides of the gate structure, of the substrate; forming a first etching stop layer covering the substrate, the gate structure and the side wall structure on the substrate; forming an opening in the first etching stop layer by etching, wherein the opening exposes a part of the heavily doped region and at least a part of the gate structure; forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a part of the heavily doped region; at least metallizing the compensation epitaxial layer to form a metal silicide layer; forming an interlayer dielectric layer on the substrate and the metal silicide layer; etching the interlayer dielectric layer to the metal silicide layer to form a connecting hole; and forming a barrier layer and a conductive structure in the connecting hole. According to the semiconductor device and the manufacturing method thereof, the saturation current can be improved, and the performance and the yield of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity, and more functions, integrated circuit chips are developing towards higher semiconductor device density and higher integration. As the feature size of semiconductor devices continues to shrink, in order to optimize the threshold voltage or leakage current, the sizes of the gate structure and the spacer structure are increased, but the distance between adjacent gate structures is reduced, resulting in insufficient etching windows for metal silicide and contact holes (CTs), which may cause damage to the lightly doped region, resulting in high resistance in the horizontal direction and failure of semiconductor devices under high voltage; or the contact holes may not be etched into the active region, resulting in CT open circuit and affecting the yield of semiconductor devices. Moreover, when the physical gate length enters below 30 nm, the parasitic resistance of the source and drain cannot be ignored relative to the channel resistance, and the parasitic resistance of the source and drain cannot be reduced by ion implantation. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof. By the semiconductor device and the manufacturing method provided by the present invention, when forming contact holes, damage to the heavily doped region and the lightly doped region can be avoided, consumption of doped ions in the heavily doped region and the lightly doped region can be effectively avoided, the saturation current can be increased, and the hot carrier effect can be eliminated. The barrier between the metal silicide layer and the substrate contact can be reduced, enabling bidirectional conduction of the channel. The etching height of the contact holes can be reduced, thereby reducing the etching difficulty of the contact holes, avoiding open circuit of the contact holes, and improving the performance and yield of semiconductor devices.

[0004] To solve the above technical problems, the present invention provides a manufacturing method of a semiconductor device, which at least includes the following steps: Provide a substrate, on which a gate structure and spacer structures on both sides of the gate structure are formed, and a lightly doped region and a heavily doped region are formed in the substrate on both sides of the gate structure; Form a first etch stop layer covering the substrate, the gate structure, and the spacer structures on the substrate; Through etching, form an opening in the first etch stop layer, and the opening exposes part of the heavily doped region and at least part of the gate structure; Form a compensation epitaxial layer in the opening, and the compensation epitaxial layer covers part of the heavily doped region and at least part of the gate structure; At least metallize the compensation epitaxial layer to form a metal silicide layer; Form an interlayer dielectric layer on the substrate and the metal silicide layer; Etch the interlayer dielectric layer to the metal silicide layer to form a via hole; and Form a barrier layer and a conductive structure in the via hole.

[0005] In an embodiment of the present invention, the manufacturing method further includes the following steps: Form a bottom anti-reflection layer and a first photoresist layer on the first etch stop layer; Expose and develop the first photoresist layer and the bottom anti-reflection layer through a mask to form a first opening, and the first opening exposes part of the first etch stop layer; Dry-etch the first etch stop layer at the bottom of the first opening to form a second opening; Laterally etch the first etch stop layer exposed by the second opening to form a third opening; and Remove the first photoresist layer and the bottom anti-reflection layer to form a fourth opening, and the fourth opening exposes part of the heavily doped region and at least part of the gate structure.

[0006] In an embodiment of the present invention, the mask for forming the first opening is the same as the mask for forming the via hole.

[0007] In an embodiment of the present invention, the manufacturing method further includes the following steps: After forming the compensation epitaxial layer, remove the first etch stop layer; and Metalize the compensation epitaxial layer and part of the substrate to form the metal silicide layer.

[0008] In an embodiment of the present invention, the metal silicide layer on the heavily doped region includes a first part and a second part. The first part is obtained by metalizing the compensation epitaxial layer and protrudes on the substrate. The second part is obtained by metalizing the heavily doped region outside the compensation epitaxial layer and extends from the surface of the substrate into the substrate, and the connection between the first part and the second part is arc-shaped.

[0009] In an embodiment of the present invention, the sidewall structure starts from the side close to the gate structure and includes a stacked first sub-layer, second sub-layer, third sub-layer and fourth sub-layer. After forming the metal silicide layer, remove the fourth sub-layer and the third sub-layer, and form a compensation doping region in the bottom of the second part and in the substrate between the heavily doped region and the second sub-layer.

[0010] In an embodiment of the present invention, the depth of the compensation doping region is greater than the depth of the second part.

[0011] In an embodiment of the present invention, the manufacturing method further includes: After forming the compensation doping region, a second etch stop layer is formed on the substrate; An interlayer dielectric layer, a hard mask layer, and a photolithography mask layer are sequentially formed on the second etch stop layer, and a recess is formed in the photolithography mask layer; and Using the photolithography mask layer as a mask, the hard mask layer, the interlayer dielectric layer, the second etch stop layer, and a part of the metal silicide layer exposed by the recess are etched to form the via hole.

[0012] In an embodiment of the present invention, the manufacturing method further includes: After forming the metal silicide layer, an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer are formed on the substrate and the metal silicide layer, and a recess is formed in the photolithography mask layer; and Using the photolithography mask layer as a mask, the hard mask layer, the interlayer dielectric layer, and a part of the metal silicide layer exposed by the recess are etched to form the via hole.

[0013] The present invention also provides a semiconductor device obtained by using the above manufacturing method, which at least includes A substrate, on which a gate structure and sidewall structures on both sides of the gate structure are provided, and lightly doped regions and heavily doped regions are provided in the substrate on both sides of the gate structure; An etch stop layer, which is at least provided on the substrate and the sidewall structures; A metal silicide layer, which is at least provided on the heavily doped regions and the gate structure, and protrudes from the surfaces of the substrate and the gate structure; An interlayer dielectric layer, which is provided on the substrate and the metal silicide layer; A via hole, which is provided in the interlayer dielectric layer; and A barrier layer and a conductive structure, which are provided in the via hole.

[0014] In summary, the present invention provides a semiconductor device and a manufacturing method thereof. By improving the semiconductor device and its manufacturing method, the unexpected technical effect of this application is that it can ensure that the range of the metal silicide layer formed is larger than the range of the via hole formation. When forming the via hole, in the case of problems such as an increase in the critical dimension of the via hole, overlay shift, or over-etching of the via hole, damage to the heavily doped and lightly doped regions can be avoided, and the device quality can be improved. It can reduce the difficulty of photomasks and etching, and by using the mask plate for forming the via hole subsequently to etch the first etch stop layer, the development of the mask plate can be reduced and the cost can be lowered. By forming a compensation epitaxial layer, when forming the metal silicide layer, the height of the active region and the gate structure can be prevented from being consumed, and at the same time, the consumption of the doped ions in the heavily doped region and the lightly doped region can be effectively avoided, the saturation current can be increased, and the device performance can be ensured. The metal silicide layer on the heavily doped region can play a role in voltage division and current shunting, and can prevent the hot carrier effect. The manufacturing process can be adjusted in a timely manner to make up for the consumption of the lightly doped region by the formation of the metal silicide layer, thereby reducing the barrier between the metal silicide layer and the substrate contact, enabling the channel to conduct bidirectionally. It can effectively prevent the semiconductor device from failing under a high supply voltage and avoid the high-voltage failure caused by the high resistance in the channel width direction of the device. It can reduce the stress on the gate structure and reduce the leakage current from the gate to the source and drain. It can reduce the etching height of the contact hole, thereby reducing the etching difficulty of the contact hole, avoiding the open circuit of the contact hole, and improving the performance and yield of the semiconductor device.

[0015] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0017] Figure 1 It is a schematic diagram of a semiconductor device after forming a gate structure, a sidewall structure, and a heavily doped region on a substrate in an embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram after forming a first etch stop layer, a bottom anti-reflection layer, and a first photoresist layer in an embodiment of the present invention.

[0019] Figure 3 It is a schematic diagram of forming a first opening in the bottom anti-reflection layer and the first photoresist layer in an embodiment of the present invention.

[0020] Figure 4Schematic diagram of forming a second opening by etching a first etch stop layer at the bottom of a first opening in an embodiment of the present invention.

[0021] Figure 5 Schematic diagram of forming a third opening by laterally etching a first etch stop layer exposed in a second opening in an embodiment of the present invention.

[0022] Figure 6 Schematic diagram of forming a fourth opening by removing a bottom anti-reflection layer and a first photoresist layer in an embodiment of the present invention.

[0023] Figure 7 Schematic diagram of forming a compensation epitaxial layer in an embodiment of the present invention.

[0024] Figure 8 Schematic diagram after removing the first etch stop layer in an embodiment of the present invention.

[0025] Figure 9 Schematic diagram of forming a metal silicide layer in an embodiment of the present invention.

[0026] Figure 10 Schematic diagram after removing a fourth sub-layer and a third sub-layer in a sidewall structure in an embodiment of the present invention.

[0027] Figure 11 Schematic diagram of forming a first compensation doping region in an embodiment of the present invention.

[0028] Figure 12 Schematic diagram of forming a second compensation doping region in an embodiment of the present invention.

[0029] Figure 13 Schematic diagram after forming a second etch stop layer, an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer in an embodiment of the present invention.

[0030] Figure 14 Schematic diagram after forming a via hole in an embodiment of the present invention.

[0031] Figure 15 Schematic diagram after forming a barrier layer and a conductive structure in an embodiment of the present invention.

[0032] Figure 16 Schematic diagram of forming a compensation epitaxial layer in another embodiment of the present invention.

[0033] Figure 17 Schematic diagram of forming a metal silicide layer in another embodiment of the present invention.

[0034] Figure 18 Schematic diagram after forming an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer in another embodiment of the present invention.

[0035] Figure 19Schematic diagram after forming a barrier layer and a conductive structure in another embodiment of the present invention.

[0036] Reference numeral description: 10. Substrate; 100. First region; 200. Second region; 101. First well region; 102. Second well region; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. First lightly doped region; 14. Second lightly doped region; 15. Gate structure; 16. Sidewall structure; 161. First sub-layer; 162. Second sub-layer; 163. Third sub-layer; 164. Fourth sub-layer; 17. First heavily doped region; 18. Second heavily doped region; 19. First etch stop layer; 20. Bottom anti-reflection layer; 21. First photoresist layer; 211. First opening; 212. Second opening; 213. Third opening; 214. Fourth opening; 22. Compensating epitaxial layer; 23. Metal silicide layer; 231. First section; 232. Second section; 24. First patterned photoresist layer; 25. First compensating doped region; 26. Second patterned photoresist layer; 27. Second compensating doped region; 28. Second etch stop layer; 29. Interlayer dielectric layer; 30. Hard mask layer; 31. Photolithography mask layer; 311. Recess; 312. Via hole; 32. Barrier layer; 33. Conductive structure. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific implementation manners, and are not intended to limit this application.

[0039] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this solution and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this solution. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0040] A semiconductor device and a manufacturing method thereof provided by the present invention can avoid damaging the heavily doped and lightly doped regions when forming connection holes, effectively avoid consuming the doped ions in the heavily doped region and the lightly doped region, improve the saturation current, and eliminate the hot-carrier effect. It can reduce the barrier at the contact between the metal silicide layer and the substrate, enabling the channel to conduct bidirectionally. It can reduce the etching height of the contact hole, thereby reducing the etching difficulty of the contact hole, avoiding the disconnection of the contact hole, and improving the performance and yield of the semiconductor device. Moreover, the manufacturing method of the present invention can be widely applied to the preparation of different semiconductor devices, and the obtained semiconductor devices can be applied to various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

[0041] Please refer to Figure 1 As shown, a substrate 10 is provided. The substrate 10 can be any material suitable for forming a semiconductor device. For example, the substrate 10 is silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed by III / V compounds, etc. It also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanide on insulator, and germanium on insulator, etc. The present invention does not limit the type of the substrate 10, which can be flexibly set according to requirements, and the substrate 10 can be set according to the type of the semiconductor device. In this embodiment, the substrate 10 is, for example, a doped silicon wafer, and the doping type can be P-type or N-type.

[0042] Please refer to Figure 1As shown, in an embodiment of the present invention, a plurality of semiconductor devices are formed on a substrate 10. The present invention does not limit the types of semiconductor devices. The semiconductor devices are, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a thyristor, a charge coupled device (CCD image sensor), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate turn-off thyristor (GTO), a digital signal processor (DSP), a fast recovery diode (FRD), a high-efficiency diode (HED), a light-triggered thyristor (LTT), a photo relay, or a microprocessor, etc. One or several of these semiconductor devices can be specifically selected during the manufacturing process. In this embodiment, the substrate 10 includes a first region 100 and a second region 200. Among them, the first region 100 is used to form an NMOS transistor, and the second region 200 is used to form a PMOS transistor. The NMOS transistor and the PMOS transistor are isolated by a shallow trench isolation structure 11.

[0043] Please refer to Figure 1 As shown, in an embodiment of the present invention, a first well region 101 and a second well region 102 are provided in the substrate 10. The first well region 101 is disposed within the first region 100, and the doping examples of the first well region 101 are, for example, P-type doping ions such as boron (B) or gallium (Ga). The second well region 102 is disposed within the second region 200, and the doping examples of the second well region 102 are, for example, N-type doping ions such as phosphorus (P) or arsenic (As). In this embodiment, the implantation depths of the first well region 101 and the second well region 102 are, for example, equal, or less than or equal to the depth of the shallow trench isolation structure 11.

[0044] Please refer to Figure 1As shown, in an embodiment of the present invention, a semiconductor device includes a gate structure 15 protruding on a substrate 10, and a gate dielectric layer 12 is disposed between the gate structure 15 and the substrate 10. Among them, the gate dielectric layer 12 is, for example, a silicon dioxide layer or a high-k dielectric layer, and the gate structure 15 is, for example, a polysilicon gate or a metal gate, etc. Sidewall structures 16 are disposed on both sides of the gate structure 15, and the sidewall structures 16 are, for example, a nitride layer or a stack of an oxide layer and a nitride layer, and the outermost layer of the sidewall structures 16 is a nitride layer. In this embodiment, the sidewall structures 16 are, for example, a stack structure of silicon oxide and silicon nitride. Starting from the side close to the gate structure 15, the sidewall structures 16 include, for example, stacked first sub-layer 161, second sub-layer 162, third sub-layer 163, and fourth sub-layer 164. Among them, the first sub-layer 161 and the third sub-layer 163 are, for example, silicon oxide layers, and the second sub-layer 162 and the fourth sub-layer 164 are, for example, silicon nitride layers. By setting the first sub-layer 161 as a silicon oxide layer, the stress of the sidewall structures 16 on the gate structure can be reduced, and the leakage current from the gate to the source and drain can be reduced.

[0045] Please refer to Figure 1 As shown, in an embodiment of the present invention, a semiconductor device includes a lightly doped region and a heavily doped region. Among them, the lightly doped region includes a first lightly doped region 13 and a second lightly doped region 14. The first lightly doped region 13 is disposed in the first region 100, and the second lightly doped region 14 is disposed in the second region 200. The edge of the lightly doped region partially overlaps with the gate structure 15, and the lightly doped region is formed after the gate structure is formed. The heavily doped region includes a first heavily doped region 17 and a second heavily doped region 18. The first heavily doped region 17 is disposed in the first region 100, and the second heavily doped region 18 is disposed in the second region 200. The edge of the heavily doped region is aligned with the edge of the sidewall structure 16 on the side away from the gate structure 15, and the heavily doped region is formed after the sidewall structure is formed to serve as the source and drain of the semiconductor device. The doping types of the first lightly doped region 13 and the first heavily doped region 17 are the same and opposite to the doping type of the first well region 101. The doping types of the second lightly doped region 14 and the second heavily doped region 18 are the same and opposite to the doping type of the second well region 102. The doping concentration of the heavily doped region is greater than that of the lightly doped region, and the doping depth of the heavily doped region is greater than that of the lightly doped region.

[0046] Please refer to Figures 1 to 2As shown, in an embodiment of the present invention, after forming the heavily doped region, a first etch stop layer 19 is formed on the substrate 10. The first etch stop layer 19 covers, for example, the sidewall structure 16, the gate structure 15, the substrate 10, and the shallow trench isolation structure 11. Among them, the first etch stop layer 19 is, for example, a silicon nitride layer, and the first etch stop layer 19 is obtained by methods such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition, and the thickness of the first etch stop layer 19 is, for example, 25 nm to 40 nm.

[0047] Please refer to Figures 2 to 3 As shown, in an embodiment of the present invention, after forming the first etch stop layer 19, a bottom anti-reflection coating (BARC) 20 and a first photoresist layer 21 are formed on the first etch stop layer 19. Among them, the bottom anti-reflection coating 20 and the first photoresist layer 21 are formed by methods such as spin coating or blade coating, and the surfaces of the bottom anti-reflection coating 20 and the first photoresist layer 21 are flat. Among them, the bottom anti-reflection coating is, for example, a resin-based composite material. By forming a mask plate for subsequent formation of vias and performing processes such as exposure and development, a first opening 211 is formed in the first photoresist layer 21 and the bottom anti-reflection coating 20. The first opening 211 is located on the heavily doped region and the gate structure 15 and exposes a part of the first etch stop layer 19.

[0048] Please refer to Figures 3 to 5 As shown, in an embodiment of the present invention, after forming the first opening 211, the first etch stop layer 19 at the bottom of the first opening 211 is removed by, for example, dry etching to form a second opening 212. After forming the second opening 212, the first etch stop layer 19 exposed by the second opening 212 is laterally etched by, for example, wet etching to form a third opening 213. Among them, the wet etching solution is, for example, phosphoric acid, and the mass fraction of phosphoric acid is 80% to 95%, and the etching temperature is 155 °C to 165 °C. The lateral etching amount of the first etch stop layer 19 is controlled by controlling the concentration of phosphoric acid, the etching temperature, and the etching time. In this embodiment, for example, the first etch stop layer 19 on the gate structure 15 is removed, and at this time, a part of the first etch stop layer 19 remains on the heavily doped region. By developing to form the first opening, the etching difficulty can be reduced, and by using the mask plate for subsequent formation of vias to achieve etching of the first etch stop layer, the development of the mask plate can be reduced and the cost can be lowered.

[0049] Please refer to Figures 5 to 6As shown, in an embodiment of the present invention, after the lateral etching, the first photoresist layer 21 and the bottom anti-reflection layer 20 are removed, and a fourth opening 214 is formed on the gate structure 15 and the heavily doped region. The fourth opening 214 exposes a part of the heavily doped region and at least a part of the gate structure 15. In this embodiment, the fourth opening 214 exposes all of the gate structure 15 and a part of the heavily doped region. Among them, the first photoresist layer 21 and the bottom anti-reflection layer 20 are removed, for example, by an ashing process and a wet etching process. Among them, in the ashing process, oxygen or a mixed gas of oxygen, nitrogen, and hydrogen is introduced at 200°C to 300°C for plasma treatment, and the first photoresist layer 21 and the bottom anti-reflection layer 20 are removed by oxygen plasma. Then, through wet etching, and the etching solution for wet etching is, for example, an organic solvent such as isopropyl alcohol, to ensure that there is no residue of the photoresist and the bottom anti-reflection layer, so as to improve the yield of the semiconductor manufacturing process. And after forming the third opening 213 on the basis of the mask plate for forming the via hole subsequently, the fourth opening 214 is etched laterally on both sides, for forming a compensation epitaxial layer and a metal silicide layer subsequently, to ensure that the range of forming the metal silicide layer is larger than the range of forming the via hole. When problems such as an increase in the critical dimension (CD) of the via hole, overlay shift, or over-etching of the via hole occur during the subsequent formation of the via hole using this mask plate, damage to the heavily doped and lightly doped regions can be avoided, and the device quality can be improved.

[0050] Please refer to Figures 6 to 7 As shown, in an embodiment of the present invention, after forming the fourth opening 214, a compensation epitaxial layer 22 is formed in the fourth opening 214, that is, the compensation epitaxial layer 22 covers a part of the heavily doped region and at least a part of the gate structure 15, and the compensation epitaxial layer 22 is, for example, a single crystal silicon layer, and the thickness is, for example, equal to the thickness of the first etch stop layer 19. Specifically, the compensation epitaxial layer 22 is formed, for example, by selective epitaxial growth. Among them, the epitaxial growth gas source is, for example, one or several mixtures of silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), or dichlorosilane (SiH2Cl2), and for example, dichlorosilane. The flow rate of dichlorosilane is, for example, 200 sccm to 400 sccm, and the epitaxial growth temperature is, for example, 700°C to 900°C. During the formation of the compensation epitaxial layer 22, due to the presence of the first etch stop layer 19, the compensation epitaxial layer 22 is formed only on the substrate 10 and the gate structure 15 exposed by the fourth opening 214.

[0051] Please refer to Figures 7 to 8As shown, in an embodiment of the present invention, after the compensation epitaxial layer 22 is formed, the first etch stop layer 19 is removed. In this embodiment, the first etch stop layer 19 is removed by wet etching, for example, and the wet etching solution is phosphoric acid, for example, and the mass fraction of phosphoric acid is 80% - 95%, and the etching temperature is 155°C - 165°C.

[0052] Please refer to Figures 8 to 9 As shown, in an embodiment of the present invention, after the first etch stop layer 19 is removed, the compensation epitaxial layer 22 and a part of the substrate 10 are metallized to form a metal silicide layer 23 to reduce the subsequent contact resistance with the conductive plug. Specifically, a silicon oxide layer and a silicon nitride layer (not shown in the figure) are deposited on the substrate 10, the shallow trench isolation structure 11, the compensation epitaxial layer 22, and the sidewall structure 16, and then the area where the metal silicide layer 23 needs to be formed is exposed by etching, and SiCoNi pre-cleaning is performed to remove possible contaminants on the substrate 10 to improve the quality of the formed metal silicide layer 23. Then a layer of metal material (not shown in the figure) is deposited. The metal material is at least one of titanium, cobalt, or nickel, etc. In this embodiment, for example, a mixed material of nickel and titanium is deposited. The thickness of the metal material is, for example, 10 nm - 15 nm. A layer of titanium nitride layer (not shown in the figure) is formed on the metal material. The thickness of the titanium nitride layer is, for example, 3 nm - 8 nm to prevent the metal material from oxidizing. By means of rapid annealing treatment, such as annealing at 260°C - 300°C for 30 s - 40 s, the exposed substrate 10 and the compensation epitaxial layer 22 are metallized to form a high-resistance metal silicide Ni2PtSi, and then annealed at 400°C - 900°C for 30 s - 40 s to form a low-resistance NiPtSi2, that is, the metal silicide layer 23. Finally, the unreacted metal material is removed.

[0053] Please refer to Figures 8 to 9As shown, in an embodiment of the present invention, the metal silicide layer 23 on the heavily doped region includes a first portion 231 and a second portion 232. The first portion 231 is obtained by reacting the compensation epitaxial layer 22 with a metal material and protrudes from the substrate 10. The second portion 232 is obtained by reacting the substrate 10 outside the compensation epitaxial layer 22 with a metal material and extends from the surface of the substrate 10 into the substrate 10. The connection between the first portion 231 and the second portion 232 is arc-shaped. In this embodiment, the width of the compensation epitaxial layer 22 is the same as that of the gate structure 15. Therefore, the metal silicide layer 23 on the gate structure 15 protrudes from the surface of the gate structure 15. In other embodiments, if the width of the compensation epitaxial layer 22 on the gate structure 15 is less than the width of the gate structure 15, that is, when forming the fourth opening, the width of the fourth opening on the gate structure 15 is less than the width of the gate structure 15. At this time, the shape of the metal silicide layer 23 on the gate structure 15 is the same as that on the heavily doped region, and this application does not elaborate specifically. By forming the compensation epitaxial layer 22, when forming the metal silicide layer 23, it is possible to avoid the consumption of the height of the active region and the gate structure, and at the same time effectively avoid the consumption of the doped ions in the heavily doped region and the lightly doped region, reduce the source-drain parasitic resistance, and ensure the device performance. At the same time, the metal silicide layer 23 on the heavily doped region can play a role in voltage division and current shunting, and can prevent the hot carrier effect.

[0054] Please refer to Figures 9 to 10 As shown, in an embodiment of the present invention, according to the wafer acceptance test (WAT) data of the substrates of the previous batch, such as determining whether the doping concentration in the lightly doped region meets the performance requirements based on the drain-source saturation current (IDSat). If the doping concentration is too low and cannot meet the electrical requirements, after forming the metal silicide layer 23, the fourth sub-layer 164 and the third sub-layer 163 in the sidewall structure 16 are removed. Among them, for example, the removal process is carried out by wet etching. The etching solution for the fourth sub-layer 164 is, for example, phosphoric acid, and the mass fraction of phosphoric acid is 80% - 95%, and the etching temperature is 155°C - 165°C. The etching solution for the third sub-layer 163 is, for example, hydrofluoric acid or buffered oxide etch (BOE).

[0055] Please refer to Figures 9 to 11As shown, in an embodiment of the present invention, after removing the fourth sub-layer 164 and the third sub-layer 163, a first patterned photoresist layer 24 is formed on the substrate 10. The first patterned photoresist layer 24 covers the first region 100. Ion implantation is performed on the second region 200, and a first compensation doping region 25 is formed in the substrate 10 at the bottom of the second segment 232 and between the second heavily doped region 18 and the second sub-layer 162. That is, the depth of the first compensation doping region 25 is greater than the depth of the second segment 232. Among them, the doping ions in the first compensation doping region 25 are, for example, boron or boron fluoride ions (BF2 + ) and other P-type ions. The specific doping dose is confirmed according to the IDSat of the previous batch.

[0056] Please refer to Figures 11 to 12 As shown, in an embodiment of the present invention, after forming the first compensation doping region 25, the first patterned photoresist layer 24 is removed, for example, by ashing or wet etching. A second patterned photoresist layer 26 is formed on the substrate 10. The second patterned photoresist layer 26 covers the second region 200. Ion implantation is performed on the first region 100, and a second compensation doping region 27 is formed in the substrate 10 at the bottom of the second segment 232 and between the first heavily doped region 17 and the second sub-layer 162. That is, the depth of the second compensation doping region 27 is greater than the depth of the second segment 232. Among them, the doping ions in the second compensation doping region 27 are, for example, N-type ions such as phosphorus or arsenic. The specific doping dose is confirmed according to the IDSat of the previous batch. In other embodiments, according to the IDSat data, a compensation doping region can also be formed only in the first region or the second region to improve IDSat and the performance of semiconductor devices. In this embodiment, the depth of the compensation doping region is greater than the depth of the second segment, which can make up for the consumption of the lightly doped region caused by the formation of the metal silicide layer 23, reduce the barrier at the contact between the metal silicide layer 23 and the substrate 10, and enable the channel to conduct bidirectionally. At the same time, it can effectively avoid the failure of semiconductor devices under high supply voltage (High Voltage Current Condense, HVCC), and avoid the high-voltage failure caused by the high resistance in the channel width direction (source to drain) of the device.

[0057] Please refer to Figures 12 to 13 As shown, in an embodiment of the present invention, after forming the second compensation doping region 27, the second patterned photoresist layer 26 is removed, for example, by ashing or wet etching. A second etch stop layer 28 is formed on the substrate 10. The second etch stop layer 28 covers, for example, the metal silicide layer 23, the sidewall structure, the substrate 10, and the shallow trench isolation structure 11. Among them, the second etch stop layer 28 is, for example, a silicon nitride layer. The second etch stop layer 28 is obtained, for example, by methods such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and the thickness of the second etch stop layer 28 is, for example, 15 nm to 25 nm.

[0058] Please refer to Figure 13 As shown, in an embodiment of the present invention, an interlayer dielectric layer 29 is formed on the second etch stop layer 28. Among them, the interlayer dielectric layer 29 is, for example, silicon oxide, and for example, a silicon oxide layer covering the metal silicide layer 23 is first formed by High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) until the region between adjacent gate structures 15 is completely filled. For example, the silicon oxide layer is planarized by Chemical Mechanical Polish (CMP) to improve the filling energy of the interlayer dielectric layer, avoid voids affecting the manufacturing yield of conductive plugs, and at the same time obtain a planarized surface, which is beneficial to subsequent operations. Then, a silicon oxide layer is formed by plasma enhanced chemical vapor deposition and chemical vapor deposition in sequence to obtain the interlayer dielectric layer 29. The present application does not limit the thickness of the silicon oxide layer formed by various deposition methods. In this embodiment, the thickness of the interlayer dielectric layer 29 on the substrate 10 is, for example, 250 nm to 280 nm. The interlayer dielectric layer 29 is formed by combining different methods to improve the deposition quality of the interlayer dielectric layer 29 and reduce the deposition cost at the same time.

[0059] Please refer to Figure 13 As shown, in an embodiment of the present invention, a hard mask layer 30 is formed on the interlayer dielectric layer 29 to protect the interlayer dielectric layer 29, improve the etch selectivity, reduce the microtrench effect, and improve the quality of the subsequent formed vias. In this embodiment, the hard mask layer 30, for example, includes an amorphous carbon layer, a silicon oxynitride layer, a silicon oxide layer, etc. sequentially disposed on the interlayer dielectric layer 29. The present application does not limit the thickness of each layer such as the amorphous carbon layer, the silicon oxynitride layer, and the silicon oxide layer, and is selected according to the manufacturing requirements. In a specific embodiment of the present invention, the thickness of the amorphous carbon layer is, for example, 160 nm to 240 nm, the thickness of the silicon oxynitride layer is, for example, 30 nm to 40 nm, and the thickness of the silicon oxide layer is, for example, 5 nm to 10 nm. By setting a hard mask layer with a multi-layer structure, the quality of the subsequent formed vias is improved.

[0060] Please refer to Figure 13As shown, in an embodiment of the present invention, a photolithography mask layer 31 is formed on the hard mask layer 30. In this embodiment, the photolithography mask layer 31 includes, for example, an anti-reflection layer and a photoresist layer sequentially disposed on the hard mask layer 30. Among them, the anti-reflection layer is a resin-based composite material. In this application, the thicknesses of each layer such as the anti-reflection layer and the photoresist layer are not limited and are selected according to the manufacturing requirements. In a specific embodiment of the present invention, the thickness of the anti-reflection layer is, for example, 20 nm to 30 nm, and the thickness of the photoresist layer is, for example, 90 nm to 110 nm. By forming a mask plate for the connection hole and performing processes such as exposure and development, a recess 311 is formed in the photolithography mask layer 31. The recess 311 is located on the heavily doped region and the gate structure 15 and exposes the underlying hard mask layer 30 to locate the position of the connection hole.

[0061] Please refer to Figures 13 to 14 As shown, in an embodiment of the present invention, using the photolithography mask layer 31 as a mask, the hard mask layer 30, the interlayer dielectric layer 29, the second etch stop layer 28, and a part of the metal silicide layer 23 are etched through a process of dry etching, wet etching, or a combination of dry etching and wet etching to form a connection hole 312. In this embodiment, for example, dry etching is used for etching. During the etching process, according to the different etching materials, they are used as etch stop layers in turn. After etching to the same material at different positions, the etching gas is replaced to obtain the connection hole 312 and make the depth of the connection hole 312 stopped in the metal silicide layer 23 the same. During the etching process, since the metal silicide layer 23 protrudes from the surface of the substrate 10 or the gate structure 15, it is equivalent to reducing the etching height of the connection hole 312. Therefore, the etching difficulty of the connection hole 312 can be reduced, thereby avoiding the disconnection of the connection hole 312 and improving the yield of the semiconductor device.

[0062] Please refer to Figures 14 to 15As shown, in an embodiment of the present invention, after the connection hole 312 is formed, a barrier layer 32 is formed on the sidewall and bottom of the connection hole 312. The barrier layer 32 is formed, for example, by electroplating or physical vapor deposition, and the barrier layer 32 is, for example, a material with good adhesion such as tantalum, tantalum nitride, or titanium nitride. The thickness of the barrier layer 32 is, for example, 5 nm to 15 nm. Metal is deposited on the barrier layer 32 to form a conductive structure 33, and the barrier layer 32 and the conductive structure 33 constitute a conductive plug. Specifically, for example, a metal material is deposited by physical vapor deposition or electroplating. The metal material is, for example, copper, aluminum, or tungsten, etc. Deposition stops until the connection hole 312 is completely filled with the metal material, and then chemical mechanical polishing is performed for planarization treatment so that the conductive structure 33 is flush with the interlayer dielectric layers 29 on both sides. In this embodiment, the conductive structure 33 is, for example, tungsten, and the barrier layer 32 is, for example, a combination of a titanium layer and a titanium nitride layer. The titanium layer is disposed on the sidewall and bottom of the connection hole 312, and the titanium nitride layer is disposed on the titanium layer. The thickness of the titanium layer is, for example, 8 nm to 10 nm, and the thickness of the titanium nitride layer is, for example, 3 nm to 5 nm. By setting the combination of the titanium layer and the titanium nitride layer, it is possible to avoid the reaction of the raw material with the titanium layer during the deposition of the conductive structure 33, prevent the conductive structure 33 from falling off, and at the same time, relieve the stress of the titanium nitride layer and improve the bonding force between the titanium nitride layer and the interlayer dielectric layer 29. By setting the barrier layer 32, the adhesion between the metal material and the sidewall of the connection hole 312 is enhanced, the diffusion of metal ions is blocked, the electromigration phenomenon is reduced, and the reliability of the semiconductor device is improved.

[0063] Please refer to Figures 16 to 17As shown, in another embodiment of the present invention, based on the wafer acceptance test data of the substrates in the previous batch, for example, the doping concentration in the lightly doped region is determined to meet the performance requirements according to the saturation current IDSat. After forming the compensation epitaxial layer 22, without removing the first etch stop layer 19, a metal silicide layer 23 is directly formed to reduce the subsequent contact resistance with the conductive plug. Specifically, a silicon oxide layer and a silicon nitride layer (not shown in the figure) are deposited on the first etch stop layer 19 and the compensation epitaxial layer 22, and then the region where the metal silicide layer 23 needs to be formed is exposed by etching, and SiCoNi pre-cleaning is performed to remove possible contaminants on the substrate 10 to improve the quality of the formed metal silicide layer 23. Then a layer of metal material (not shown in the figure) is deposited. The metal material is, for example, at least one of titanium, cobalt, or nickel, etc. In this embodiment, for example, a mixed material of nickel and titanium is deposited. The thickness of the metal material is, for example, 10 nm to 15 nm. A layer of titanium nitride layer (not shown in the figure) is formed on the metal material, and the thickness of the titanium nitride layer is, for example, 3 nm to 8 nm to prevent the metal material from oxidizing. By means of rapid annealing treatment, such as annealing at 260°C to 300°C for 30 s to 40 s, the metal material reacts with the silicon in the exposed substrate 10 and the compensation epitaxial layer 22 to form a high-resistance metal silicide Ni2PtSi, and then annealing at 400°C to 900°C for 30 s to 40 s to form a low-resistance NiPtSi2, that is, the metal silicide layer 23. Finally, the unreacted metal material is removed. In this embodiment, since the first etch stop layer 19 is not removed, the metal material only reacts with the compensation epitaxial layer 22 to form the metal silicide layer 23, and the formed metal silicide layer 23 protrudes above the substrate 10 or the gate structure 15.

[0064] Please refer to Figures 17 to 19 As shown, in another embodiment of the present invention, after forming the metal silicide layer 23, an interlayer dielectric layer 29, a hard mask layer 30, and a photolithography mask layer 31 are directly formed on the first etch stop layer 19 and the metal silicide layer 23, and the forming method and structure are the same as those in the previous embodiment, and will not be elaborated here. During the process of forming the via hole 312, the hard mask layer 30, the interlayer dielectric layer 29, and a part of the metal silicide layer 23 are etched in sequence to form the via hole 312, and then a barrier layer 32 and a conductive structure 33 are formed, and the forming method and structure are the same as those in the previous embodiment, and will not be elaborated here. In this embodiment, the formation process of the metal silicide layer 23 is different from that in the previous embodiment, which can simplify the manufacturing process and at the same time has the beneficial effects of the previous embodiment, and can improve the performance and yield of the semiconductor device.

[0065] In summary, the present invention provides a semiconductor device and a manufacturing method thereof. By improving the semiconductor device and its manufacturing method, the unexpected technical effect of this application is that it can ensure that the range of the metal silicide layer formed is larger than the range of the via formation. When forming the via, in the case of problems such as an increase in the critical dimension of the via, overlay shift, or over-etching of the via, damage to the heavily doped and lightly doped regions can be avoided, and the device quality can be improved. It can reduce the difficulty of photomasks and etching, and by using the mask plate for subsequent via formation to etch the first etch stop layer, the development of mask plates can be reduced, and the cost can be lowered. By forming a compensation epitaxial layer, when forming the metal silicide layer, the heights of the active region and the gate structure can be prevented from being consumed, and at the same time, the doping ions in the heavily doped region and the lightly doped region can be effectively prevented from being consumed, the saturation current can be increased, and the device performance can be ensured. The metal silicide layer on the heavily doped region can play a role in voltage division and current shunting, and can prevent the hot carrier effect. According to the wafer acceptance test data, the manufacturing process is adjusted in a timely manner, which can make up for the consumption of the lightly doped region by the formation of the metal silicide layer, can reduce the barrier at the contact between the metal silicide layer and the substrate, and enable the channel to conduct bidirectionally. It can effectively prevent the semiconductor device from failing under high supply voltage and avoid the high-voltage failure caused by the high resistance in the channel width direction of the device. It can reduce the stress on the gate structure and reduce the leakage current from the gate to the source and drain. It can reduce the etching height of the contact hole, thereby reducing the etching difficulty of the contact hole, avoiding the open circuit of the contact hole, and improving the performance and yield of the semiconductor device.

[0066] The foregoing description of the embodiments shown in the present invention (including what is described in the abstract of the specification) is not intended to be exhaustive or to limit the present invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as will be recognized and understood by those skilled in the art, various equivalent modifications are within the spirit and scope of the present invention. As noted, these modifications to the present invention can be made in accordance with the foregoing description of the embodiments of the present invention, and these modifications will be within the spirit and scope of the present invention.

[0067] The above description is only a preferred embodiment of the present application and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features having similar functions disclosed in the present application. Except for the technical features described in the specification, the remaining technical features are well-known to those skilled in the art. To highlight the innovative features of the present invention, the remaining technical features are not described herein again.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, At least the following steps are included: Provide a substrate, on which a gate structure and sidewall structures on both sides of the gate structure are formed, and lightly doped regions and heavily doped regions are formed in the substrate on both sides of the gate structure; Form a first etch stop layer covering the substrate, the gate structure and the sidewall structures on the substrate; Form an opening in the first etch stop layer by etching, the opening exposing part of the heavily doped region and at least part of the gate structure; Form a compensation epitaxial layer in the opening, the compensation epitaxial layer covering part of the heavily doped region and at least part of the gate structure; At least metallize the compensation epitaxial layer to form a metal silicide layer; Form an interlayer dielectric layer on the substrate and the metal silicide layer; Etch the interlayer dielectric layer to the metal silicide layer to form a via hole; And Form a barrier layer and a conductive structure in the via hole.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that The manufacturing method further includes the following steps: Form a bottom anti-reflection layer and a first photoresist layer on the first etch stop layer; Expose and develop the first photoresist layer and the bottom anti-reflection layer through a mask to form a first opening, the first opening exposing part of the first etch stop layer; Dry-etch the first etch stop layer at the bottom of the first opening to form a second opening; Laterally etch the first etch stop layer exposed by the second opening to form a third opening; and Remove the first photoresist layer and the bottom anti-reflection layer to form a fourth opening, the fourth opening exposing part of the heavily doped region and at least part of the gate structure.

3. The manufacturing method of the semiconductor device according to claim 2, wherein, The mask for forming the first opening is the same as the mask for forming the via hole.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The manufacturing method further includes the following steps: After forming the compensation epitaxial layer, remove the first etch stop layer; and Metallize the compensation epitaxial layer and part of the substrate to form the metal silicide layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein The metal silicide layer on the heavily doped region includes a first part and a second part. The first part is obtained by metallizing the compensation epitaxial layer and protrudes on the substrate. The second part is obtained by metallizing the heavily doped region outside the compensation epitaxial layer and extends from the surface of the substrate into the substrate, and the connection between the first part and the second part is arc-shaped.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The sidewall structure starts from the side close to the gate structure and includes stacked first, second, third, and fourth sub-layers. After forming the metal silicide layer, remove the fourth sub-layer and the third sub-layer, and form a compensation doped region at the bottom of the second part and in the substrate between the heavily doped region and the second sub-layer.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The depth of the compensation doped region is greater than the depth of the second part.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The manufacturing method further includes: After forming the compensation doped region, form a second etch stop layer on the substrate; Successively form the interlayer dielectric layer, a hard mask layer and a photolithography mask layer on the second etch stop layer, and a recess is formed in the photolithography mask layer; and Using the photolithography mask layer as a mask, etch the hard mask layer, the interlayer dielectric layer, the second etch stop layer, and a part of the metal silicide layer exposed by the recess to form the via hole.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The manufacturing method further includes: After forming the metal silicide layer, form an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer on the substrate and the metal silicide layer, and a recess is formed in the photolithography mask layer; and Using the photolithography mask layer as a mask, etch the hard mask layer, the interlayer dielectric layer, and a part of the metal silicide layer exposed by the recess to form the via hole.

10. A semiconductor device, characterized in that, Obtained by using the manufacturing method according to any one of claims 1-9, at least including a substrate, on which a gate structure and sidewall structures on both sides of the gate structure are provided, and lightly doped regions and heavily doped regions are provided in the substrate on both sides of the gate structure; an etch stop layer, disposed at least on the substrate and the sidewall structures; a metal silicide layer, disposed at least on the heavily doped regions and the gate structure, and protruding from the surfaces of the substrate and the gate structure; an interlayer dielectric layer, disposed on the substrate and the metal silicide layer; a via hole, disposed in the interlayer dielectric layer; and a barrier layer and a conductive structure, disposed in the via hole.

Images