Dynamic reconfiguration method and device of FPGA chip, terminal equipment and storage medium

Abstract

The invention discloses a dynamic reconfiguration method and device for an FPGA chip, terminal equipment and a storage medium, and the method comprises the steps: segmenting a configuration file in a target FPGA chip into a static configuration file and a reconfigurable file; after the static configuration file is loaded, the reconfigurable file is converted into a binary data format file, and configuration information in the binary data format file is written into a PCIe expansion register in the target FPGA chip; according to the FPGA chip reconfiguration method and device, the configuration information in the PCIe expansion register is analyzed, after all the configuration information in the PCIe expansion register is obtained through analysis, the user logic of the target FPGA chip is updated through the internal configuration access port according to the configuration information, and the technical problem that in the prior art, extra logic and storage resources need to be occupied, and consequently the reconfiguration efficiency of the FPGA chip is low can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA, and particularly to a method, device, terminal device and storage medium for dynamically reconfiguring an FPGA chip. Background Art

[0002] With the rapid development of electronic technology, FPGA (Field Programmable Gate Array) has been widely used in many fields. FPGA has the advantages of strong programmability, high flexibility, short development cycle, etc., and can be customized according to different application requirements. In some application scenarios, it is necessary to dynamically reconfigure the FPGA to meet different functional requirements. In traditional designs, common methods for reconfiguring FPGA include reconfiguration through the JTAG interface, reconfiguration through on-board FLASH, reconfiguration through PCIE, etc.

[0003] The existing reconfiguration methods for FPGA chips usually call the interfaces provided by the driver, and transfer content such as configuration information to the target FPGA chip through the DMA (Direct Memory Access) method to achieve reconfiguration. However, it is necessary to develop DMA-related drivers and logics to complete the transmission of configuration information and reconfiguration, which requires additional logic and storage resources, resulting in low reconfiguration efficiency of the FPGA chip. Summary of the Invention

[0004] The present invention provides a method, device, terminal device and storage medium for dynamically reconfiguring an FPGA chip, which can solve the technical problem that additional logic and storage resources are required in the prior art, resulting in low reconfiguration efficiency of the FPGA chip.

[0005] The present invention provides a method for dynamically reconfiguring an FPGA chip, including:

[0006] Dividing the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file;

[0007] After loading the static configuration file, converting the reconfigurable file into a binary data format file, and writing the configuration information in the binary data format file into the PCle expansion register in the target FPGA chip;

[0008] Parsing the configuration information in the PCle expansion register, and after parsing all the configuration information in the PCle expansion register, updating the user logic of the target FPGA chip according to the configuration information through the internal configuration access port.

[0009] Further, splitting the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file includes:

[0010] Using an EDA tool to pre-define the area of the static configuration file and the area of the reconfigurable file in the target FPGA chip;

[0011] Generating two independent bitstream files based on the area of the static configuration file and the area of the reconfigurable file respectively to obtain the static configuration file and the reconfigurable file.

[0012] Further, writing the configuration information in the binary data format file into the PCIe extended register in the target FPGA chip includes:

[0013] Writing the configuration information in the binary data format into the PCIe extended register in the target FPGA chip in the format of 32-bit data units;

[0014] After writing all the configuration information in the binary data format into the PCIe extended register, writing 0 to the address 0X804 of the PCIe extended register to disable the internal configuration access port enable.

[0015] Further, writing the configuration information in the binary data format into the PCIe extended register in the target FPGA chip includes:

[0016] Writing the configuration information in the binary data format to the address 0X800 of the PCIe extended register in the target FPGA chip.

[0017] Further, updating the user logic of the target FPGA chip according to the configuration information through the internal configuration access port further includes:

[0018] Writing the configuration information into the reconfigurable file in the target FPGA chip through the internal configuration access port to update the user logic of the target FPGA chip.

[0019] Further, the static configuration file is a PCIe configuration file, and the reconfigurable file is a user logic configuration file.

[0020] The present invention provides a dynamic reconfiguration device for an FPGA chip, including:

[0021] A configuration file splitting module, configured to split the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file;

[0022] A configuration information writing module, which is used to convert the reconfigurable file into a binary data format file after loading the static configuration file, and write the configuration information in the binary data format file into the PCIe expansion register in the target FPGA chip;

[0023] A reconfiguration module, which is used to parse the configuration information in the PCIe expansion register. After parsing all the configuration information in the PCIe expansion register, update the user logic of the target FPGA chip according to the configuration information through the internal configuration access port.

[0024] Furthermore, the configuration information writing module is further used for:

[0025] Write the configuration information in the binary data format into the PCIe expansion register of the target FPGA chip in a 32-bit data unit format;

[0026] After writing all the configuration information in the binary data format into the PCIe expansion register, write 0 to the address 0X804 of the PCIe expansion register to disable the internal configuration access port enable.

[0027] The present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the dynamic reconfiguration method of the FPGA chip as described above is implemented.

[0028] The present invention provides a computer-readable storage medium, including: a stored computer program, wherein when the computer program runs, it controls the device where the computer-readable storage medium is located to execute the dynamic reconfiguration method of the FPGA chip as described above.

[0029] In the present invention, the configuration file in the target FPGA chip is divided into a static configuration file and a reconfigurable file, and the reconfigurable file is converted into a binary data format file. The configuration information in the binary data format file is written into the PCIe expansion register in the target FPGA chip, and the information in the PCIe expansion register is parsed to complete the reconfiguration of the FPGA chip. It is not necessary to enable the PCIe BAR space, nor to develop the MDA-related driver and logic, and it does not occupy additional logic resources and storage resources, thereby effectively improving the reconfiguration efficiency of the FPGA chip. Description of the Drawings

[0030] To more clearly illustrate the technical solutions of this application, the following will briefly introduce the attached drawings required for the implementation. Obviously, the attached drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other attached drawings can also be obtained based on these drawings.

[0031] Figure 1 is a schematic flowchart of the dynamic reconfiguration method of the FPGA chip provided by an embodiment of the present invention;

[0032] Figure 2 is another schematic flowchart of the dynamic reconfiguration method of the FPGA chip provided by an embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of the dynamic reconfiguration system of the FPGA chip provided by an embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of the dynamic reconfiguration device of the FPGA chip provided by an embodiment of the present invention. Specific Embodiments

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following will clearly and completely describe the technical solutions in this application in combination with the attached drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above attached drawing descriptions are intended to cover non-exclusive inclusion.

[0037] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order, or primary-secondary relationship of the indicated technical features. In the description of the embodiments of this application, "a plurality" means more than two unless otherwise clearly and specifically defined.

[0038] References herein to "embodiments" mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0039] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0040] In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two). Similarly, "multiple groups" refers to two or more groups (including two groups), and "multiple pieces" refers to two or more pieces (including two pieces).

[0041] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0042] See Figure 1 , to solve the technical problem in the prior art that additional logic and storage resources need to be occupied, resulting in low reconfiguration efficiency of the FPGA chip, the present invention provides a dynamic reconfiguration method for an FPGA chip, including:

[0043] S1. Split the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file;

[0044] In the embodiments of the present invention, the FPGA configuration file can be split into a static configuration file and a reconfigurable file through an EDA tool. Among them, the static configuration file can include a configuration file for static logic containing a PCIe subsystem (such as a PHY, DMA controller, etc.) to ensure that the PCIe interface continues to work during the reconfiguration process; the reconfigurable file can be a configuration file including user algorithms or data processing logic, and function switching is achieved through partial reconfiguration. In the embodiments of the present invention, the static configuration file can be a PCle configuration file, and the reconfigurable file can be a user logic configuration file.

[0045] In the embodiment of the present invention, by splitting the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file, during subsequent reconfiguration, only the reconfigurable file needs to be used to reconfigure some logic, without reconfiguring the entire logic space of the target FPGA chip, effectively reducing the reconfiguration time, and thus effectively improving the reconfiguration efficiency.

[0046] S2. After loading the static configuration file, convert the reconfigurable file into a binary data format file, and write the configuration information in the binary data format file into the PCle extended register in the target FPGA chip;

[0047] In the embodiment of the present invention, before loading the static configuration file, the host computer can be powered on and enter the linux operating system, and the reconfiguration of the target FPGA chip can be completed based on this linux operating system.

[0048] In the embodiment of the present invention, the static file can be loaded through the FLASH, and the PCle subsystem in the target FPGA chip can start working within 100 ms and establish a link with the host computer.

[0049] In the embodiment of the present invention, after obtaining the ROOT permission of the linux operating system, convert the reconfigurable file into a binary data format file that meets the ICAP timing requirements, and then write it into the PCle register in the target FPGA chip.

[0050] In the embodiment of the present invention, all the configuration information in the reconfigurable file is written into the PCle register in the target FPGA chip, the memory space is released, and 0 is written to the 0X804 address in the PCle register to disable the internal configuration access port (ICAP).

[0051] S3. Parse the configuration information in the PCle extended register. After parsing all the configuration information in the PCle extended register, update the user logic of the target FPGA chip according to the configuration information through the internal configuration access port.

[0052] In an embodiment of the present invention, after the configuration information is written into the PCle extended register in the target FPGA chip, the content of the PCle extended register is updated. After the PCle subsystem in the FPGA chip receives the update of the content of the PCle extended register, it transmits the received configuration information to the configuration information parsing module in the FPGA chip through the external extended register bus interface. The configuration information in the PCle extended register and the enable information of the internal configuration access port are parsed by the configuration information parsing module. After the parsed configuration information is written into the internal configuration access port of the FPGA chip, the enable of the internal configuration access port is turned off, and the dynamic reconfiguration of the FPGA is completed through the internal configuration port, updating the user logic and implementing function switching.

[0053] In the embodiment of the present invention, by writing the configuration information in the binary data format file into the PCle extended register in the target FPGA chip and parsing the information in the PCle extended register to complete the reconfiguration of the FPGA chip, it is not necessary to enable the PCIe BAR space, nor to develop the drivers and logics related to MDA, and no additional logic resources and storage resources are occupied, thus effectively improving the efficiency of the FPGA chip reconfiguration.

[0054] Furthermore, in the embodiment of the present invention, the external extended register bus interface is used to transfer the configuration information, and there is no need to additionally use the MUX to select the TX / RX interface data to connect to the ICAP or the user logic, which is beneficial to timing convergence.

[0055] In one embodiment, step S1: splitting the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file, includes:

[0056] S11: Using EDA tools to pre-define the areas of the static configuration file and the user logic configuration file in the target FPGA chip;

[0057] In the embodiment of the present invention, EDA tools can be used to draw the area boundaries through the create_pblock command or the graphical interface, to divide the area of the static configuration file (such as the area containing non-reconfigurable modules such as PCIe interfaces and clock management) and the area of the user logic configuration file (such as the area containing user logic modules) in the FPGA configuration file.

[0058] S12: Generating two independent bitstream files based on the area of the static configuration file and the area of the user configuration file, to obtain the static configuration file and the reconfigurable file.

[0059] In an embodiment of the present invention, a Vivad tool or a custom script can be used to extract a static configuration frame and a user logic frame from the complete bitstream data in the area where the static configuration file belongs and the area where the user configuration file belongs, and encapsulate them into a static configuration file and a reconfigurable file respectively.

[0060] By separating the static configuration file and the reconfigurable file in the embodiment of the present invention and performing FPGA chip reconfiguration with the reconfigurable file, the memory occupancy can be reduced, the PCle fast startup can be achieved, and the efficiency of FPGA chip reconfiguration can be effectively improved.

[0061] In one embodiment, step S2, writing the configuration information in the binary data format file into the PCle extended register in the target FPGA chip, includes:

[0062] S21: Write the configuration information in the binary data format into the PCle extended register in the target FPGA chip in the format of 32-bit data units;

[0063] S22: After writing all the configuration information in the binary data format into the PCle extended register, write 0 to the address 0X804 of the PCle extended register to disable the internal configuration access port enable.

[0064] In the embodiment of the present invention, after all the configuration information is written into the PCle extended register, disabling the internal configuration access port enable can effectively prevent the configuration tampering problem caused by malicious or misoperation, and improve the security and reliability of FPGA reconfiguration.

[0065] In one embodiment, writing the configuration information in the binary data format into the PCle extended register in the target FPGA chip includes:

[0066] Write the configuration information in the binary data format into the address 0X800 of the PCle extended register in the target FPGA chip.

[0067] In the embodiment of the present invention, by writing the configuration information into a specific address such as 0X800 in the PCle extended register, the configuration information for reconfiguration can be obtained by parsing the configuration information in the specific address, and efficient reconfiguration can be achieved.

[0068] In one embodiment, step S3, updating the user logic of the target FPGA chip according to the configuration information through the internal configuration access port, further includes:

[0069] Write the configuration information into the reconfigurable file in the target FPGA chip through the internal configuration access port to update the user logic of the target FPGA chip.

[0070] In an embodiment of the present invention, all configuration information can be written into the reconfigurable file area to update the user logic of the target FPGA chip.

[0071] Please refer to Figure 2 , which is another schematic flowchart of a dynamic reconfiguration method for an FPGA chip provided by an embodiment of the present invention. In Figure 2 , first, an EDA tool is used to split the configuration file to obtain a PCle configuration file and several reconfigurable files. The FLASH loads the PCle configuration file to implement PCle startup and link establishment. Then, the software selects and loads any reconfigurable file that needs to be reconfigured, so that the user logic completes the reconfiguration and realizes function switching.

[0072] Implementing the embodiments of the present invention has the following beneficial effects:

[0073] In the embodiments of the present invention, the configuration information in the binary data format file is written into the PCle extended register in the target FPGA chip, and the information in the PCle extended register is parsed to complete the reconfiguration of the FPGA chip. There is no need to enable the PCIe BAR space, nor to develop the drivers and logic related to MDA, and no additional logic resources and storage resources are occupied, thereby effectively improving the reconfiguration efficiency of the FPGA chip.

[0074] Please refer to Figure 3 , in an embodiment, a dynamic reconfiguration system for an FPGA chip is provided. The above embodiments can be executed in the dynamic reconfiguration system of the FPGA chip shown in Figure 3 . The dynamic reconfiguration system of the FPGA chip includes a software test platform and an FPGA test platform. The software test platform includes an application program, as well as a system interface and tools; the FPGA test platform includes a PCle subsystem, a configuration information parsing module, and a FLASH. The PCIe subsystem consists of SERDES and PCIe. The configuration information parsing module is connected to the external extended register bus interface (ERI) and the internal configuration access port (ICAP) of the PCIe respectively, and the FLASH is connected to the configuration information parsing module. The two configuration stages completed based on the dynamic reconfiguration system of the FPGA chip are: the first configuration stage loads the PCle configuration file from the FLASH to complete the link establishment with the peer computer; the second configuration stage is for the software to record the user logic configuration file. After the configuration is completed, the dynamic reconfiguration of the user logic function is realized through the PCle and the ICAP.

[0075] In the embodiments of the present invention, the FLASH only needs to store the PCIe configuration file, and the user logic configuration file exists on the software side. Only when needed, the user logic configuration file is dynamically loaded through the software side to achieve reconfiguration, reducing the risk of the user logic configuration file being exposed to physical or network attacks for a long time, which is beneficial to improving the reconfiguration security.

[0076] Please refer to Figure 4 , the present invention provides a dynamic reconfiguration device for an FPGA chip, including:

[0077] A configuration file splitting module 10, configured to split the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file;

[0078] A configuration information writing module 20, configured to convert the reconfigurable file into a binary data format file after loading the static configuration file, and write the configuration information in the binary data format file into the PCle extended register in the target FPGA chip;

[0079] A reconfiguration module 30, configured to parse the configuration information in the PCle extended register. After all the configuration information in the PCle extended register is parsed, the user logic of the target FPGA chip is updated according to the configuration information through the internal configuration access port.

[0080] In one embodiment, the configuration file splitting module 10 is further configured to:

[0081] Pre - define the area where the static configuration file in the target FPGA chip belongs and the area where the reconfigurable file belongs by using an EDA tool;

[0082] Generate two independent bitstream files based on the area where the static configuration file belongs and the area where the reconfigurable file belongs, to obtain the static configuration file and the reconfigurable file.

[0083] In one embodiment, the configuration information writing module 20 is further configured to:

[0084] Write the configuration information in the binary data format into the PCle extended register of the target FPGA chip in a 32 - bit data unit format;

[0085] After all the configuration information in the binary data format is written into the PCle extended register, write 0 to the 0X804 address of the PCle extended register to disable the internal configuration access port enable.

[0086] In one embodiment, writing the configuration information in the binary data format into the PCle extended register of the target FPGA chip includes:

[0087] Write the configuration information in the binary data format to the address 0X800 in the PCle expansion register of the target FPGA chip.

[0088] In one embodiment, the reconfiguration module 30 is further configured to:

[0089] Write the configuration information to the reconfigurable file in the target FPGA chip through the internal configuration access port to update the user logic of the target FPGA chip.

[0090] In one embodiment, the static configuration file is a PCle configuration file, and the reconfigurable file is a user logic configuration file.

[0091] It can be understood that the above device item embodiments correspond to the method item embodiments of the present invention, and can implement the dynamic reconfiguration method of the FPGA chip provided in any one of the above method item embodiments of the present invention.

[0092] It should be noted that the device embodiments described above are only illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement without creative work.

[0093] Based on the embodiments of the above dynamic reconfiguration method of the FPGA chip, another embodiment of the present invention provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the dynamic reconfiguration method of the FPGA chip according to any embodiment of the present invention is implemented.

[0094] Exemplarily, in this embodiment, the computer program can be divided into one or more modules, and one or more modules are stored in the memory and executed by the processor to complete the present invention. One or more module elements can be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

[0095] The terminal device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The terminal device may include, but is not limited to, a processor and a memory.

[0096] The so-called processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and connects various parts of the entire terminal device through various interfaces and lines.

[0097] Based on the above method item embodiments, another embodiment of the present invention provides a computer-readable storage medium, including a stored computer program, wherein when the computer program runs, it controls the device where the computer-readable storage medium is located to execute the dynamic reconfiguration method of the FPGA chip in any of the above method item embodiments of the present invention.

[0098] Among them, if the modules / units integrated in the device / terminal device are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0099] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A dynamic reconfiguration method for an FPGA chip, characterized in that including: splitting a configuration file in a target FPGA chip into a static configuration file and a reconfigurable file; after loading the static configuration file, converting the reconfigurable file into a binary data format file, and writing configuration information in the binary data format file into a PCIe extended register in the target FPGA chip; parsing the configuration information in the PCIe extended register, and after obtaining all the configuration information in the PCIe extended register, updating user logic of the target FPGA chip according to the configuration information through an internal configuration access port.

2. The dynamic reconfiguration method of the FPGA chip according to claim 1, wherein, The splitting of the configuration file in the target FPGA chip into a static configuration file and a reconfigurable file includes: predefining areas where the static configuration file and the reconfigurable file in the target FPGA chip are located by using an EDA tool; generating two independent bitstream files respectively based on the areas where the static configuration file and the reconfigurable file are located, to obtain the static configuration file and the reconfigurable file.

3. The dynamic reconfiguration method of the FPGA chip according to claim 1, characterized in that, The writing of the configuration information in the binary data format file into the PCIe extended register in the target FPGA chip includes: writing the configuration information in the binary data format into the PCIe extended register in the target FPGA chip in a 32-bit data unit format; after writing all the configuration information in the binary data format into the PCIe extended register, writing 0 to the 0X804 address of the PCIe extended register to disable the internal configuration access port.

4. The dynamic reconfiguration method of the FPGA chip according to claim 3, wherein The writing of the configuration information in the binary data format into the PCIe extended register in the target FPGA chip includes: writing the configuration information in the binary data format into the 0X800 address of the PCIe extended register in the target FPGA chip.

5. The dynamic reconfiguration method of the FPGA chip according to claim 1, characterized in that, The updating of the user logic of the target FPGA chip according to the configuration information through the internal configuration access port further includes: writing the configuration information into the reconfigurable file in the target FPGA chip through the internal configuration access port to update the user logic of the target FPGA chip.

6. The dynamic reconfiguration method of the FPGA chip according to claim 1, wherein The static configuration file is a PCIe configuration file, and the reconfigurable file is a user logic configuration file.

7. A dynamic reconfiguration device for an FPGA chip, characterized in that, including: a configuration file splitting module, configured to split a configuration file in a target FPGA chip into a static configuration file and a reconfigurable file; a configuration information writing module, configured to convert the reconfigurable file into a binary data format file after loading the static configuration file, and write the configuration information in the binary data format file into a PCIe extended register in the target FPGA chip; a reconfiguration module, configured to parse the configuration information in the PCIe extended register, and after obtaining all the configuration information in the PCIe extended register, update user logic of the target FPGA chip according to the configuration information through an internal configuration access port.

8. A dynamic reconfiguration device for an FPGA chip, characterized in that The configuration information writing module is further configured to: Write the configuration information in the binary data format to the PCle extended register of the target FPGA chip in a 32-bit data unit format; After writing all the configuration information in the binary data format to the PCle extended register, write 0 to the address 0X804 of the PCle extended register to disable the internal configuration access port enable.

9. A terminal device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the dynamic reconfiguration method of the FPGA chip according to any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, It includes: A stored computer program, wherein when the computer program runs, it controls the device where the computer-readable storage medium is located to execute the dynamic reconfiguration method of the FPGA chip according to any one of claims 1-6.

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