Method and system for realizing DSMC communication interface between RK3576ARM and FPGA

Abstract

The invention relates to an implementation method and system based on a DSMC communication interface between an RK3576 ARM (Advanced RISC Machines) and an FPGA (Field Programmable Gate Array). According to the system, DMA transmission is started through an ARM end, a data reading position is specified, and an input port and a bidirectional data bus are initialized through an FPGA end. The ARM end sends a read address, the FPGA end performs clock conversion, chip selection signal processing and clock counting, detects a read operation mark and switches a bus into an output mode, the DRAM module reads data and returns the data to the FPGA end, and the ARM end receives the data through the DMA. And the FPGA end dynamically identifies the transmission data length and ensures clock synchronization to complete data transmission. According to the method, the problems of high protocol overhead and low transmission bandwidth of the DSMC bus are solved, the utilization rate of the bus bandwidth is remarkably improved, the transmission delay is reduced, the flexibility of the system and the data transmission efficiency are enhanced by optimizing the clock management and data transmission process, and the method is suitable for a high-speed data transmission scene.

Description

Technical Field

[0001] The present invention relates to the technical field of implementing high-speed parallel transmission using the DSMC bus and FPGA, and specifically to a method and system for implementing the DSMC communication interface between RK3576 ARM and FPGA. Background Art

[0002] For common buses of ARM, data sampling is usually performed at the rising edge or falling edge of the clock within a unit sampling clock cycle.

[0003] The DSMC bus is different from other buses. It can achieve dual-edge sampling within a unit sampling clock cycle. In this case, at the same bus frequency, the communication rate will be twice as high as that of a single-edge sampling bus.

[0004] For example, the SPI bus is single-edge sampling, while DSMC samples at both the rising edge and falling edge of the clock.

[0005] However, the DSMC bus has a large protocol overhead. Within 8 clock cycles, only two clock cycles are valid data bits, and the rest are protocol overhead, which will result in a low data transmission bandwidth of the bus, far from reaching the theoretical bandwidth value of the bus. Moreover, due to the complexity of the protocol overhead and the timing synchronization mechanism, the data transmission delay of the DSMC bus is relatively high, making it difficult to meet application scenarios with high real-time requirements.

[0006] In addition, the DSMC bus requires precise timing synchronization during data transmission. The complex clock management mechanism in the prior art increases the complexity of hardware design and may lead to data transmission delay and instability. Summary of the Invention

[0007] The purpose of the present invention is to provide a method and system for implementing the DSMC communication interface between RK3576 ARM and FPGA to solve the technical problems raised in the above background art.

[0008] To achieve the above purpose, the present invention provides the following technical solution: A method for implementing the DSMC communication interface between RK3576 ARM and FPGA, including the following steps: The ARM side sends an address and corresponding multiple data through the DMA burst transmission characteristic; The DSMC bus control module responds to the transmission request, controls the DSMC chip select signal to be pulled low to start the transmission, generates the DSMC differential clock signal, and after re-encoding the data transmitted by the DMA, sends it to the FPGA input / output port module through the ARM input / output port module in burst mode; The direction control signal generation module on the FPGA side detects the read or write operation flag and generates a direction control signal to indicate the bus direction; The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to the input or output mode according to the direction control signal; In the input mode, the sampled data is transferred to the internal signal after passing through the data double-edge decoding module; in the output mode, the prepared data is transferred to the input / output port after passing through the data double-edge encoding module.

[0009] Preferably, the method further includes the following steps: The data clock conversion module on the FPGA side converts the DSMC differential clock into a single-ended clock, which is used as the internal main clock for data encoding and signal processing; The chip select signal inversion module on the PGA side inverts the DSMC chip select signal to generate the cs_n signal to clearly identify the data transmission status; The clock counter module on the FPGA side starts counting, records the valid clock cycles, and strictly controls the data reception timing.

[0010] Preferably, the method further includes the following steps: The ARM side receives the returned data through DMA to complete the data read operation; the data length identification module on the FPGA side monitors the DMA transfer completion status and dynamically identifies the transferred data length to adapt to different data transfer length requirements.

[0011] Preferably, step 3 includes the following sub-steps: Sub-step 31: The ARM side sends the address and corresponding multiple data through the DMA burst length feature; Sub-step 32: Detect the completion status of the DMA transfer. When the transfer is completed, trigger an interrupt and enter the DMA transfer completion interrupt service function; Sub-step 33: When the DMA transfer is completed, the ARM side raises the DSMC chip select signal to end this communication; Sub-step 34: When the DMA transfer is completed, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM of the transfer completion; Sub-step 35: The data length identification module on the FPGA side dynamically identifies the data length of this transfer through the change of the DSMC chip select signal; Sub-step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS; Sub-step 37: The data length identification module updates the data length value according to the status of the clock counting module.

[0012] Preferably, the timing calibration module on the FPGA side finely tunes the clock signal to ensure clock synchronization. When the bidirectional data bus is in the input mode, the timing calibration module synchronously adjusts the sampling timing of the data line, compensates for the transmission delay difference between the clock and the data by advancing or delaying the data sampling point, and ensures that the data is sampled at the correct clock edge.

[0013] The present invention also provides a system based on the DSMC communication interface between RK3576 ARM and FPGA. The system includes: an ARM side and an FPGA side; the ARM side includes: a user logic module, a DMA burst transmission module, a DSMC bus control module, and an ARM input / output port module; The FPGA side includes: an FPGA top-level module, a timing calibration module, a data double-edge decoding module, a data decoding module, a DRAM module, a data double-edge encoding module, a dynamic bus direction switching module, a data length identification module, a chip select signal inversion module, a data clock conversion module, a clock counter module, and an FPGA input / output port module.

[0014] Compared with the prior art, the beneficial effects of the present invention are: The present invention combines DMA and DSMC to send data to the ARM input / output port module in burst mode; on the FPGA side, the DSMC bus control module dynamically adjusts the bus direction (read / write), switches the working mode of the bidirectional data line (DSMC_DQ / DSMC_DQ1), and ensures accurate data transmission through clock synchronization and signal sampling; at the same time, the DRAM module directly processes the read / write requests on the FPGA side, reducing protocol latency. Thus, the bus bandwidth utilization rate is significantly improved (close to the theoretical value), the transmission delay is reduced, and the flexibility and data transmission efficiency of the system are enhanced. Description of the Drawings

[0015] Figure 1 : is a flowchart of a method for implementing a DSMC communication interface between RK3576 ARM and FPGA provided by the present invention; Figure 2 : is a block diagram of a system for implementing a DSMC communication interface between RK3576 ARM and FPGA provided by the present invention. Detailed Embodiments

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] Please refer to Figure 1-2 , the present invention provides a technical solution: a system based on the DSMC communication interface between RK3576 ARM and FPGA, the system includes: an ARM side and an FPGA side; the ARM side includes: a user logic module, which is used to access the / dev / ttySX node through ioctl, request to transmit data and send DMA transmission commands; A DMA burst transmission module, which is used to receive commands from the / dev / dma_memcpy node, obtain data from the DDRRAM, and start the DMA to control the DSMC bus control module to transmit data in burst mode; A DSMC bus control module, which is used to respond to the transmission request, control the DSMC chip select signal to be pulled low to start the transmission, generate a DSMC differential clock signal, re-encode the data transmitted by the DMA, and send it to the FPGA input / output port module through the ARM input / output port module; ARM input / output port module: used to communicate with the FPGA input / output port module; The FPGA side includes: An FPGA top-level module, which is used to control the operation of the entire FPGA side; A timing calibration module, which is used to convert the DSMC differential clock into a single-ended clock as the internal master clock; A data double-edge encoding module, which is used to perform double-edge encoding on the data; A data decoding module, which is used to decode the received data; A data double-edge decoding module, which is used to perform double-edge decoding on the data; A DRAM module, which is used to store and access data; A dynamic bus direction switching module, which is used to switch the working mode of the bidirectional data buses DSMC_DQ and DSMC_DQ1 according to the direction control signal; A data length identification module, which is used to dynamically identify the length of the transmitted data; A chip select signal inversion module, which is used to invert the DSMC chip select signal to generate the cs_n signal; A data clock conversion module, which is used to convert the DSMC differential clock signal into a single-ended clock signal for internal use in the FPGA; A clock counter module, which is used to record the effective clock cycles and control the timing of data reception; An FPGA input / output port module, which is used to communicate with the ARM input / output port module.

[0018] Based on the above system, the present invention also provides a method for implementing a DSMC communication interface between RK3576 ARM and FPGA, and the method includes the following steps: Step 11: The upper-layer application on the ARM side accesses the / dev / dma_memcpy node through ioctl, requests to transfer data, and sends a DMA transfer command.

[0019] Step 12: The DMA burst transfer module on the ARM side receives the command from the / dev / dma_memcpy node, parses the command content, obtains data from the DDR RAM, and starts the DMA to control the DSMC bus control module to transfer data in burst mode.

[0020] Step 13: The DSMC bus control module on the ARM side responds to the transfer request, controls the DSMC chip select signal to be pulled low to indicate the start of the transfer; controls the DSMC differential clock to generate a 100 MHz clock signal; re-encodes the data transmitted by the DMA according to the user logic, and sends the data to the ARM input / output port module in burst mode, and sends it to the FPGA input / output port module through the ARM input / output port module, such as sending data address addr_0 and data data_0 ~ data_1024.

[0021] Step 14: The direction control signal generation module detects the read or write operation flag and generates a direction control signal to indicate that the bus direction is "receiving data" or "sending data".

[0022] Step 15: The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to input or output mode according to the direction control signal.

[0023] Step 16: When in the input mode, the dynamic bus direction switching module passes the sampled data data_0 to the internal signal after passing through the data double-edge decoding module.

[0024] Step 17: When in the output mode, the dynamic bus direction switching module passes the prepared data to the input / output port after passing through the data double-edge encoding module.

[0025] Step 18: The DRAM module receives the read address and read enable signal from the FPGA side and reads data from the specified address of the DRAM and returns it to the FPGA side to implement the data reading operation; This solution combines DMA and DSMC to send data to the ARM input / output port module in burst mode. On the FPGA side, the DSMC bus control module dynamically adjusts the bus direction (read / write) and switches the working mode of the bidirectional data lines (DSMC_DQ / DSMC_DQ1), and ensures accurate data transmission through clock synchronization and signal sampling. At the same time, the DRAM module directly processes the read / write requests from the FPGA side, reducing protocol latency. Thus, the bus bandwidth utilization is significantly improved (close to the theoretical value), the transmission latency is reduced, and the flexibility and data transmission efficiency of the system are enhanced.

[0026] To solve the timing misalignment and data reliability problems caused by the incompatibility of the DSMC differential clock and chip select signal in the communication between the FPGA and external devices (such as ARM), this method further includes the following steps: Step 19: The data clock conversion module on the FPGA side converts the DSMC differential clock into a single-ended clock, which is used as the internal main clock for the data encoding module and internal signal assignment.

[0027] Step 20: The chip select signal inversion module on the FPGA side inverts the DSMC chip select signal to generate the cs_n signal, indicating that data transmission is currently in progress.

[0028] Step 21: The clock counter module starts counting, records the number of valid clock cycles, and controls the timing of data reception.

[0029] Through the above steps: First, the data clock conversion module on the FPGA side converts the DSMC differential clock into a single-ended clock as the internal main clock to ensure that data encoding and signal processing are strictly synchronized with the clock. Second, the chip select signal inversion module inverts the DSMC chip select signal to generate cs_n to clearly identify the data transmission status. Finally, the clock counter module accurately records the valid clock cycles and strictly controls the data reception timing. After optimization, the system realizes efficient synchronous communication between the FPGA and external devices, significantly improves the data reception reliability, timing stability and overall performance, and is suitable for high-speed data transmission scenarios.

[0030] To solve the lack of flexibility and variable-length data adaptation problems caused by the fixed data length limit in traditional DMA transmission, this method further includes the following steps: Step 31: The ARM side sends an address addr_0 and multiple data (assuming only one data data_0 is sent currently) through the DMA burst length feature.

[0031] Step 32: Detect the completion status of the DMA transmission. When the transmission is completed, trigger an interrupt and enter the DMA transmission completion interrupt service function.

[0032] Step 33: After the DMA transfer is completed, the ARM side raises the DSMC chip select signal to end this communication.

[0033] Step 34: After the DMA transfer is completed, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM that the transfer is completed.

[0034] Step 35: The data length identification module on the FPGA side dynamically identifies the data length of this transfer (currently 1 data) through the change of the DSMC chip select signal.

[0035] Step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS.

[0036] Step 37: The data length identification module updates the data length value according to the status of the clock counting module.

[0037] Through the above steps: A dynamic identification mechanism is implemented through the data length identification module on the FPGA side. The ARM side uses the DMA burst transfer characteristic to send data (such as one address corresponding to multiple data, and currently in the example, it is 1 data data_0). After the transfer is completed, an interrupt is triggered and the DSMC chip select signal (DSMC_CS) is raised to end the communication. At the same time, the upper-layer application is notified through the / dev / input / eventX node. The data length identification module on the FPGA side continuously monitors the change of the DSMC_CS signal and dynamically calculates the data length of this transfer in combination with the status of the clock counting module (identified as 1 data in the current example). Therefore, the system can adapt to any variable-length transfer requirement without presetting a fixed data length, simplifies the protocol design and reduces the hardware complexity. At the same time, data truncation or overflow problems are avoided through accurate identification, significantly improving the communication reliability, flexibility and system scalability, and are applicable to diverse data interaction requirements in high-performance embedded scenarios.

[0038] Regarding the problem of inconsistent transmission delays of the DSMC bus clock and data signals caused by PCB trace differences, this method further includes the following steps: Step 41: The timing calibration module on the FPGA side ensures clock synchronization and fine-tuning to ensure that data is sent to the ARM side within the correct clock cycle, ensuring the real-time and accurate data transmission.

[0039] Step 42: When the bidirectional data buses (DSMC_DQ and DSMC_DQ1) are inputs, they are connected to the timing calibration module and are advanced and delayed according to a specified number of clock cycles (each cycle is 25 ps), so as to achieve the synchronization and alignment of data and clock, ensuring that data is sent and received at the correct clock edge.

[0040] The timing calibration module on the FPGA side ensures data transmission synchronization through a dynamic adjustment mechanism: when the bidirectional data bus is in the input mode, the module finely tunes the clock signal in 25ps steps and synchronously adjusts the sampling timing of the data lines (DSMC_DQ / DSMC_DQ1), compensating for the transmission delay difference between the clock and data by advancing or delaying the data sampling points, so that the data is sent to the ARM side within an accurate clock cycle or sampled at the correct clock edge. Therefore, the system effectively eliminates the clock-data skew problem caused by inconsistent PCB traces, significantly improves the accuracy and reliability of high-speed data transmission, and at the same time enhances the adaptability to complex PCB layouts and multi-rate transmission scenarios, ensuring the stability of data transmission in burst mode and providing reliable data interaction guarantee for high-performance embedded systems.

[0041] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing the DSMC communication interface between RK3576 ARM and FPGA, characterized in that It includes the following steps: The ARM side sends the address and corresponding multiple data through the DMA burst transmission feature; The DSMC bus control module responds to the transmission request, controls the DSMC chip select signal to be pulled low to start the transmission, generates the DSMC differential clock signal, and after re-encoding the data transmitted by DMA, sends it to the FPGA input / output port module in burst mode through the ARM input / output port module; The direction control signal generation module on the FPGA side detects the read or write operation flag and generates a direction control signal to indicate the bus direction; The dynamic bus direction switching module sets the bidirectional data buses DSMC_DQ and DSMC_DQ1 to input or output mode according to the direction control signal; In the input mode, the sampled data is passed to the internal signal after passing through the data double-edge decoding module; in the output mode, the prepared data is passed to the input / output port after passing through the data double-edge encoding module.

2. The implementation method of the DSMC communication interface between RK3576 ARM and FPGA according to claim 1, characterized in that The method further includes the following steps: The data clock conversion module on the FPGA side converts the DSMC differential clock into a single-ended clock, which is used as the internal main clock for data encoding and signal processing; The chip select signal inversion module on the PGA side inverts the DSMC chip select signal to generate the cs_n signal to clearly identify the data transmission status; The clock counter module on the FPGA side starts counting, records the effective clock cycles, and strictly controls the data reception timing.

3. The implementation method of the DSMC communication interface between RK3576 ARM and FPGA according to claim 2, wherein The method further includes the following steps: The ARM side receives the return data through DMA to complete the data reading operation; the data length identification module on the FPGA side monitors the DMA transmission completion status and dynamically identifies the transmitted data length to adapt to different data transmission length requirements.

4. The implementation method of the DSMC communication interface between RK3576 ARM and FPGA according to claim 3, characterized in that : The step 3 includes the following sub-steps: Sub-step 31: The ARM side sends the address and associated multiple data through the DMA burst length feature; Sub-step 32: Detect the completion status of the DMA transmission. When the transmission is completed, trigger an interrupt and enter the DMA transmission completion interrupt service function; Sub-step 33: When the DMA transmission is completed, the ARM side raises the DSMC chip select signal to end this communication; Sub-step 34: When the DMA transmission is completed, the ARM side sends an event signal to the / dev / input / eventX node to notify the upper-layer application of the ARM of the transmission completion; Sub-step 35: The data length identification module on the FPGA side dynamically identifies the data length of this transmission through the change of the DSMC chip select signal; Sub-step 36: The data length identification module continuously monitors the status of the DSMC chip select signal DSMC_CS; Sub-step 37: The data length identification module updates the data length value according to the status of the clock counting module.

5. The method for implementing the DSMC communication interface between RK3576 ARM and FPGA according to claim 4, wherein The method further includes the following steps: The timing calibration module on the FPGA side fine-tunes the data signal to ensure the synchronization of the clock and data signals; When the bidirectional data bus is in the input mode, the timing calibration module synchronously adjusts the sampling timing of the data line, compensates for the transmission delay difference between the clock and data by advancing or delaying the data sampling point, and ensures that the data is sampled at the correct clock edge.

6. A system based on the DSMC communication interface between RK3576 ARM and FPGA, characterized in that, It includes: One ARM side and one FPGA side; The ARM side includes: a user logic module, a DMA burst transfer module, a DSMC bus control module, and an ARM input / output port module; The FPGA side includes: an FPGA top-level module, a timing calibration module, a data double-edge encoding module, a data decoding module, a data double-edge decoding module, a DRAM module, a dynamic bus direction switching module, a data length identification module, a chip select signal inversion module, a data clock conversion module, a clock counter module, and an FPGA input / output port module.

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