Special high-frequency low-level control system

Abstract

The invention discloses a special high-frequency low-level control system, which is characterized by comprising a digital signal processing board card and a radio frequency front-end board card, the digital signal processing board card mainly comprises a clock distribution unit, an ADC digital-to-analog conversion unit, a DAC analog-to-digital conversion unit, an FPGA and a cavity frequency tuning driving unit. The ADC digital-to-analog conversion unit is used for converting an intermediate frequency acquisition analog signal output by the radio frequency front-end board card into a digital intermediate frequency signal and sending the digital intermediate frequency signal to the FPGA; the DAC analog-to-digital conversion unit is used for converting the DDS excitation signal output by the FPGA into an intermediate frequency excitation analog signal and sending the intermediate frequency excitation analog signal to the radio frequency front-end The radio frequency front-end board card performs up-conversion on the intermediate-frequency excitation analog signal to obtain an RF excitation signal, sends the RF excitation signal to a high-frequency cavity for field construction, and performs down-conversion on a cavity field recovery signal to obtain an intermediate-frequency acquisition analog signal; the cavity frequency tuning drive unit comprises a motor slow tuning drive and a piezoelectric ceramic fast tuning drive; and the FPGA is used for data acquisition and loop control.

Description

Technical Field

[0001] The present invention belongs to the technical field of accelerators, and particularly relates to a dedicated high-frequency low-level control system, which is used for the low-level control of the high-frequency system of the Beijing Electron Positron Collider II (BEPCII) and can be widely applied in related projects involving high-frequency signal data acquisition and control. Background Art

[0002] The high-frequency system is crucial in the accelerator device and is the "engine" of the entire accelerator system. An RF electric field is established in the high-frequency resonant cavity. Charged particles move along the longitudinal orbit. When they pass through the RF electric field, they obtain energy in the accelerating phase and are accelerated or longitudinally bunched.

[0003] The high-frequency system mainly includes three major parts: high-frequency cavities, power sources, and low-level controls.

[0004] The main functions of the high-frequency low-level control system include high-frequency cavity field amplitude control and cavity field phase control, high-frequency cavity frequency tuning control, safety interlock protection, etc., to ensure the stable operation of the high-frequency system and even the accelerator system.

[0005] Whether for acceleration or bunching, the RF electric field established by the high-frequency system must have good stability, so that the beam can obtain a stable RF electric field amplitude and phase when passing through the RF electric field, ensuring high-quality beam. Thus, the low-level control technology and its corresponding system came into being. Due to factors such as micro-vibrations, Lorentz forces, uneven bunch charges, temperature, and the nonlinearity of klystrons, the high-frequency cavity will be detuned. Therefore, a high-frequency system frequency control loop needs to be established, which can be used to compensate for the detuning of the cavity. Due to factors such as changes in beam loading, the amplitude and phase of the RF field in the cavity will change. A high-frequency system amplitude and phase control loop needs to be established to compensate for the fluctuations in the amplitude and phase of the cavity field and stabilize the amplitude and phase of the cavity field.

[0006] The low-level control technology has gone through three stages: all-analog control, digital plus analog control, and all-digital control. The high-frequency low-level control of accelerators in the 1960s and 1970s was all-analog control, with the core component being a micro-control device; in the 1980s and the early 1990s, a high-frequency low-level controller that combined analog and digital technologies was developed. This stage was mainly due to the emergence of the Numerically Controlled Oscillator (NCO) with high precision and high stability; in the 21st century, an all-digital high-frequency low-level control system was developed, thanks to the widespread use of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs).

[0007] Since the commissioning and operation of the high-frequency system of the second phase of the Beijing Electron-Positron Collider (BEPC-II) in 2005, an analog low-level control system has been adopted, which is imported equipment purchased from the High Energy Accelerator Research Organization (KEK) in Japan. It not only has a high equipment cost, simple functions, but also lags behind in technology. The digitalization of the low-level control system is an irresistible trend.

[0008] Currently, the internationally popular high-frequency low-level control systems mainly include those based on the Micro Advanced Telecom Computing Architecture (MTCA) and those based on the Compact Peripheral Component Interconnect (CPCI) bus. For example, the high-frequency systems of accelerator facilities such as APS-U in the United States, PETRA-IV in Germany, and MAX-IV in Sweden all adopt the low-level control system with the MTCA architecture. The high-frequency systems of the Shanghai Synchrotron Radiation Facility (SSRF) ring and the China Spallation Neutron Source (CNSN) ring in China both adopt the low-level control system based on CPCI. The low-level control systems based on MTCA and CPCI use commercial control chassis and bus technologies, which can meet the basic low-level control requirements. However, for the high-frequency systems of different engineering projects, the low-level system needs to have different control functions, which requires the low-level system to have flexible expansion functions. Commercial boards are not convenient to expand and have relatively high costs. Developing a dedicated custom digital low-level control system can meet the core needs of low-level control. Summary of the Invention

[0009] In view of the development trend of the digital low-level control system and the disadvantages of the digital low-level system based on commercial boards, the present invention provides a new dedicated high-frequency low-level control system. The present invention designs and manufactures a dedicated digital signal processing (DSP) board based on Altera FPGA, a radio frequency front-end board, and a low-level control chassis. The design of the hardware board circuit schematic diagram and the PCB drawing are both completed using Altium Designer; an input and output control (IOC) application system based on the Experimental Physics and Industrial Control System (EPICS) is developed, and the upper-layer control interface is completed based on the Control System Studio (CS-Studio). Control algorithms such as cavity field amplitude-phase loop control and cavity frequency loop control are developed based on the Quartus II development software.

[0010] The newly developed low-level hardware and control algorithms of the present invention include:

[0011] 1) A digital signal processing board, with FPGA as the core, peripherally configured with memories such as SRAM, DRAM, EPCS, and FLASH, equipped with high-speed parallel ADC and DAC, serial ADC and DAC, a clock distribution chip AD9520, a configuration chip CPLD, an opto-isolator, an analog phase detector, etc.

[0012] 2) A radio frequency front-end board, which realizes the down-conversion of RF radio frequency signals and the up-conversion of IF intermediate frequency signals. The main devices involved in the radio frequency front-end board include power dividers, amplifiers, mixers, filters, voltage regulators, etc. The high-frequency system of the High Energy Photon Source (HEPS) project has high-frequency cavities with two RF frequencies of 166.6 MHz and 499.8 MHz. In order to be compatible with these two RF operating frequencies, the operating bandwidth of the radio frequency devices can cover these two operating frequencies.

[0013] 3) Control algorithms, implemented based on the FPGA of the DSP board, mainly including amplitude-phase feedback loop control of the cavity field and tuning control of the cavity frequency, etc.

[0014] The technical solution of the present invention is:

[0015] Hardware mainly includes a digital signal processing board and a radio frequency front-end board. The design of the circuit schematic diagram and the PCB layout are both completed using Altium Designer. The digital signal processing board uses an Altera FPGA as the core chip to complete various digital algorithms and control functions of LLRF. The radio frequency front-end board includes the generation function of the LO local oscillator and the up / down conversion function of the RF signal. The control software is completed based on the EPICS control system; the upper-layer control interface is completed based on CS-Studio.

[0016] The digital signal processing board mainly includes:

[0017] 1) Clock distribution unit: Adopts the high-performance clock distribution and synchronization chip AD9520-3. The input is the RF high-frequency signal. The multiple outputs include the ADC and DAC clocks, the FPGA working clock, the IF intermediate-frequency reference signal, etc. The frequencies of the ADC clock and the DAC clock are M-divided by the RF frequency, and the frequency of the IF intermediate-frequency reference signal is N-divided by the RF frequency.

[0018] Equipped with a CPLD chip, the clock distribution parameters of the AD9520 are configured through the SPI serial interface.

[0019] 2) High-speed ADC and DAC analog-to-digital conversion unit: Includes 3 ADC chips AD9268-125 and 1 DAC chip AD9788. AD9268-125 is a 16-bit, dual-channel, high-performance analog-to-digital converter with a maximum sampling rate of 125 MSPS, high SNR and SFDR. It is responsible for converting the IF intermediate-frequency acquisition analog signal output by the radio frequency front-end board into a digital intermediate-frequency signal, and then sending it into the FPGA of the digital signal processing board for further processing; AD9788 is a 16-bit, dual-channel, high-performance digital-to-analog converter with a maximum sampling rate of 800 MSPS. It is responsible for converting the DDS excitation digital signal of the FPGA into an IF intermediate-frequency excitation analog signal, and then sending it into the radio frequency front-end board for up-conversion to obtain a low-level RF excitation signal.

[0020] 3) Cavity Frequency Tuning Drive Unit: The tuning drive unit consists of two parts: motor slow tuning drive and piezo ceramic fast tuning drive. For the motor slow tuning drive, an opto-coupler circuit is used to output the pulse signal, direction signal, and enable signal from the FPGA to drive the motor to the motor driver, thereby driving the motor to operate and tune the cavity frequency. At the same time, the upper and lower limit switch signals of the motor are transmitted to the FPGA through the opto-coupler circuit to achieve mechanical limit of the motor. The opto-coupler circuit isolates the external signals of the non-low-level digital signal processing board to prevent noise from being introduced into the low-level digital signal processing board. In addition, a low-speed ADC is used to collect the position voltage signal of the motor tuning and send it to the FPGA, and the electrical limit of the motor is achieved through an algorithm. For the piezo ceramic fast tuning drive, a slow-speed DAC is used to convert the piezo drive digital signal generated by the FPGA control algorithm into a piezo drive analog signal, which is then sent to the ceramic driver. The ceramic driver amplifies the piezo drive analog signal and loads it onto the piezo ceramic body on the cavity to achieve frequency tuning of the high-frequency cavity.

[0021] 4) FPGA Logic Processing Unit: The FPGA uses the EP3SL150F1152C2 chip of the StratixIII series produced by ALTERA Corporation, and is peripherally configured with memories such as SRAM, DRAM, EPCS, and FLASH. The FPGA is the core of the low-level control system, and functions such as data acquisition, loop control algorithm, and data communication of the low-level system are all implemented through the FPGA.

[0022] a) The main RF signals collected by the low-level system include reference signal REF, cavity field feedback signal Pt, cavity forward power signal Pf, cavity reflected power signal Pr, etc. These signals are down-converted to obtain the corresponding IF intermediate-frequency acquisition analog signals, which are then sent to the ADC for data acquisition. The data acquisition function uses the Non-IQ algorithm to convert the digital intermediate-frequency signal converted by the ADC into orthogonal quantities in the I / Q domain, and further filters out the high-frequency signals through a cascaded integrator-comb filter (CIC) to obtain the final I / Q quantities of the sampled signals.

[0023] b) The loop control algorithms mainly include the amplitude-phase control loop algorithm of the cavity field, the cavity frequency tuning control loop algorithm, etc. The amplitude-phase loop control of the cavity field adopts the vector control method in the I / Q domain. The FPGA collects the cavity field feedback signal Pt to obtain its quadrature components fdb_i and fdb_q, and after vector rotation, the quadrature components fdb_rot_i and fdb_rot_q of the cavity field feedback rotation signal are obtained. The cavity field amplitude-phase set values are ref_set_i and ref_set_q. The difference between ref_set_i and fdb_rot_i is sent to the proportional-integral (PI) controller of the cavity field amplitude-phase loop to obtain the in-phase component output signal pi_out_i of the PI controller. The difference between ref_set_q and fdb_rot_q is sent to the PI controller of the cavity field amplitude-phase loop to obtain the quadrature component output signal pi_out_q of the PI controller. pi_out_i and pi_out_q are modulated by the NCO controller inside the FPGA to obtain the DDS excitation output signal of the intermediate frequency. This DDS excitation digital signal is converted from digital to analog by the DAC to obtain the IF intermediate frequency excitation analog signal of the low-level system, and then it is up-converted to the RF high-frequency signal through the up-conversion channel of the RF front-end board. This signal is used as the RF excitation signal of the low-level system and sent to the subsequent power source for power amplification, and then sent to the high-frequency cavity through the microwave transmission channel to build the field. The cavity frequency tuning control loop algorithm includes two algorithms: motor tuning and piezo tuning.The quadrature I / Q quantities obtained by the FPGA collecting the cavity field feedback signal Pt are first subjected to vector rotation and then passed through the cordic algorithm (Coordinate Rotation Digital Computer Algorithm) to obtain the cavity field phase cav_pha; the quadrature I / Q quantities obtained by the FPGA collecting the cavity forward power signal Pf are first passed through the vector rotation module and then through the cordic algorithm to obtain the cavity forward phase forw_pha. The difference between the two is the cavity detuning angle detun_angle. The difference between detun_angle and the set detuning angle load_angle is further subtracted to obtain the difference dif_angle; dif_angle is sent to the PI controller of the motor tuning loop. When dif_angle is less than the motor start angle start_angle or greater than the negative start_angle, the output of the PI controller of the motor tuning loop is 0, controlling the motor to stop. Otherwise, the output of the PI controller of the motor tuning loop is not 0, controlling the motor to start rotating; when dif_angle is greater than the motor stop angle stop_angle or less than the negative stop_angle, the PI controller of the motor tuning loop works normally, the motor enable signal is set to high level, and the motor drive pulse signal pulse is assigned the pulse signal of the motor set speed. According to the positive and negative values of the output of the PI controller of the motor tuning loop and the motor rotation speed, the motor drive pulse signal pulse and the motor rotation direction signal dir are output to the motor driver, and the motor driver drives the motor to operate according to the input pulse signal and dir signal. When dif_angle is less than the motor stop angle stop_angle and greater than the negative stop_angle at the same time, the output of the PI controller of the reset motor tuning loop is 0, and the motor enable signal enable and the pulse signal pulse are both set to low level to stop the rotation of the motor. dif_angle is also sent to the PI controller of the piezo tuning loop. After the output of this PI controller, high-frequency signals are filtered out through CIC low-pass filtering to obtain the digital signal piezo_out for piezo drive. This signal is converted into an analog signal for piezo drive through a slow DAC and then output and sent to the ceramic driver. After signal amplification, it is output to the piezo ceramic of the high-frequency cavity to achieve the tuning of the high-frequency cavity.

[0024] c) The data communication function is mainly implemented by the embedded Nios-II soft core processor based on the Reduced Instruction Set Computer (RISC) architecture inside the FPGA. In terms of hardware configuration, SRAM, DRAM, EPCS, FLASH and other memories, and a three-speed Ethernet module are configured around the Nios-II processor.

[0025] The internal register module of the FPGA uses the Avalon bus for inter-module interconnection to achieve data communication. The Nios-II soft-core algorithm is based on the simple socket server routine. The soft-core system packs the read and write data of the low-level system into network data packets, and uses the NicheStack TCP / IP protocol to realize the data transmission of Ethernet data packets between the soft-core system and the database server through the socket API of LWIP.

[0026] Furthermore, the DSP board is configured with 2 reset switches to achieve the hardware reset of the low-level control system.

[0027] Furthermore, the DSP board is configured with 2 trigger interfaces, which can be used as the timing trigger input of the low level or as the TTL output port of the low level.

[0028] Furthermore, the DSP board is configured with 10 I / O expansion interfaces to provide external interfaces for the function expansion of the low level.

[0029] Furthermore, the M and N frequency division coefficients of the clock distribution unit can be flexibly configured according to the requirements of the Non-IQ algorithm.

[0030] Furthermore, the low-level control algorithm also develops functional algorithms including maximum power protection, cavity quench protection, and feedforward control.

[0031] The RF front-end board mainly includes:

[0032] 1) Power splitting of the RF reference signal: After passing through a 4-way power splitter, 4 RF reference signals are output. The first RF output is sent to the clock distribution unit of the DSP board for clock distribution, which will generate an IF intermediate-frequency reference signal and return it to the RF front-end board; the second RF output is mixed with the IF intermediate-frequency reference signal output by the clock distribution unit of the DSP board and then passed through a band-pass filter to obtain the LO local oscillator signal; the third RF output is sent to the down-conversion channel for down-conversion and then output to the DSP board for ADC acquisition; the last one is output as the RF spare signal to the front panel of the low-level control chassis.

[0033] 2) Generation of the LO signal: The IF intermediate-frequency reference signal output by the DSP clock distribution unit is mixed with the RF reference signal after low-pass filtering. The mixed signal contains two frequencies, RF±IF. This signal is first amplified by an amplifier and then passed through a band-pass filter with the LO local oscillator frequency to obtain the LO local oscillator signal. The LO frequency is equal to the RF frequency minus the IF frequency. Then, through a 2-way power splitter and then a 4-way power splitter, 8 LO frequency signals are obtained. Two of them are directly output for backup or signal monitoring, and the other 6 are amplified to a level of about 7 dBm and sent to the mixers of the 1-way up-conversion and 5-way down-conversion channels as the LO local oscillator signals respectively.

[0034] 3) 5-way down-conversion channel: The RF acquisition signals such as the forward power signal Pf of the cavity, the reflected power signal Pr of the cavity, and the back-captured signal Pt of the cavity field are mixed with the LO local oscillator frequency signal by a mixer, amplified by an amplifier, and then filtered by a low-pass filter to obtain the IF intermediate-frequency acquisition analog signals of the corresponding RF acquisition signals. The output IF intermediate-frequency acquisition analog signals will be connected to the ADC sampling channels of the DSP board.

[0035] 4) 1-way up-conversion channel: The IF intermediate-frequency excitation analog signal output by the DSP board and the LO local oscillator frequency signal are mixed by a mixer, amplified by an amplifier, and then filtered by a band-pass filter with the RF frequency to obtain a low-level RF excitation signal output. This RF output signal is sent as a low-level excitation to the power source for power amplification and then sent to the high-frequency cavity to establish a field.

[0036] Furthermore, a low-noise regulated power supply circuit is configured for each up / down-conversion channel of the RF front-end board.

[0037] Furthermore, a microwave shielding wall is configured between each channel and between different functional circuits.

[0038] Furthermore, the interface positions of the RF front-end board are layout-designed according to the positions of the ADC and DAC channels of the digital signal processing board.

[0039] Compared with the prior art, the present invention has the following advantages:

[0040] 1) The development cost is reduced

[0041] Since it is a self-developed board, all the circuits on the board are designed according to the functional requirements, which is different from many commercial boards that are useless for low-level systems. At the same time, the selected chips are designed according to the functional requirements, not the more expensive the better, saving costs.

[0042] 2) High functional integration

[0043] According to the functional requirements of the low level, the system integrates an algorithm control circuit with FPGA as the core, a clock distribution circuit, an ADC / DAC analog-to-digital conversion circuit, a motor drive circuit, a ceramic piezo drive circuit, an analog phase discrimination circuit, etc. For commercial boards, usually multiple boards are required to achieve the control function of the low level, and for some functions where there are no commercial boards available, specific function boards still need to be developed independently, increasing the complexity of the control system.

[0044] 3) Convenient function expansion

[0045] The low-level control algorithm is mainly implemented based on the FPGA firmware algorithm, and the algorithm is easy to expand. The ADC / DAC analog-to-digital conversion circuit is an important part to ensure the low-level control accuracy and is located on the periphery of the board. If there are ADC / DAC chips with better performance, the PCB board can be slightly modified to complete the board upgrade. In addition, more than 10 expansion I / Os are reserved on the board to facilitate the subsequent function expansion of the board. Description of the drawings

[0046] Figure 1 It is a block diagram of the hardware architecture of the low-level control system.

[0047] Figure 2 It is a principle block diagram of the digital signal processing board.

[0048] Figure 3 It is the schematic diagram of the RF front-end board.

[0049] Figure 4 It is the schematic diagram of the cavity field amplitude-phase feedback loop control algorithm.

[0050] Figure 5 It is the schematic diagram of the cavity frequency tuning loop control algorithm.

[0051] Figure 6 It is a block diagram of the software architecture of the low-level control system.

[0052] Figure 7 It is the overall framework diagram of the high-frequency system. Detailed implementation manners

[0053] The present invention will be further described in detail below with reference to the drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0054] 1. Top-level design

[0055] The composition framework diagram of the low-level control system is as Figure 1As shown in the figure, the system mainly includes a digital signal processing board, a radio frequency front-end board, a low-level chassis, etc. The digital signal processing board completes the conversion between analog and digital signals, the acquisition of digital signals, control algorithm functions, clock distribution functions, etc. The radio frequency front-end board completes the up-conversion of IF signals and the down-conversion of RF signals. The low-level control chassis provides power for the boards and interfaces with external devices.

[0056] 2. Hardware Design

[0057] Altium designer is used for the design of circuit schematics and the drawing of PCB printed boards.

[0058] Hardware Design of DSP Board:

[0059] The principle block diagram of the digital signal processing board is as Figure 2 shown. Among them, the FPGA chip selects the EP3SL150F1152C2 chip of the StratixIII series produced by ALTERA Corporation. Its main performance parameters are shown in Table 1. Its ALM and LE reach 56.8k and 142.5k respectively, and there are 744 pin I / Os. For the LLRF low-level system, the number of logic units and pins is sufficient to meet the design requirements.

[0060] Table 1 Main Performance Parameters of EP3SL150F1152C2

[0061]

[0062] According to the functional requirements, in order to implement the data communication function, the FPGA embedded processor soft core Nios-II of ALTERA is adopted, and SRAM, DRAM, EPCS, FLASH and other memories are configured around the FPGA; for high-precision control and high-speed data acquisition, high-speed parallel ADCs and DACs are configured; in addition, a serial ADC is configured to collect the motor position signal, and a slow serial DAC is configured to realize the drive control of piezo ceramics; in order to provide the clock for the digital signal processing board and the clocks of the ADC and DAC chips, a clock distribution chip AD9520 and a parameter configuration control chip CPLD are configured; an opto-isolator is configured between the motor drive circuit and the low-level control circuit to prevent the noise interference at the motor drive end from affecting the low-level control circuit; an analog phase detector is configured to realize the phase recovery function in the case of power failure of the low-level system. Through the integration of these hardware circuits, the low-level multi-functional hardware requirements can be met.

[0063] Design the schematic diagram according to the chip selection and functional requirements, and complete the PCB layout. Since the digital signal processing board involves complex circuits and a large amount of signals, the PCB design adopts a 16-layer design to ensure signal integrity and good EMC electromagnetic shielding performance.

[0064] Hardware design of the RF front-end board:

[0065] The high-frequency RF acquisition signals include the reference signal REF, the forward cavity power signal Pf, the reflected cavity power signal Pr, the cavity field feedback signal Pt, the beam current signal Pb, etc. The high-frequency RF output signal is the power source RF excitation signal. Therefore, the RF front-end board includes 5 down-conversion and 1 up-conversion channels, which realize the down-conversion of 5 RF acquisition signals into IF intermediate-frequency acquisition analog signals, and the up-conversion of 1 IF intermediate-frequency excitation analog signal into RF excitation signals. The main devices involved in the RF front-end board include power splitters, amplifiers, mixers, filters, and voltage regulators, etc. The HEPS project includes two RF frequencies of 166.6 MHz and 499.8 MHz. When selecting these RF devices, first consider that the working bandwidth of the RF devices needs to cover these two working frequencies. Secondly, select according to other main characteristics of each RF device. Finally, complete the schematic diagram design and draw the PCB printed circuit board. The PCB board layout mainly considers the isolation between channels and cooperates with the digital signal processing board to complete the layout design of channels and other aspects. The schematic diagram of the RF front-end board is as Figure 3 shown.

[0066] 3. Development of control algorithms

[0067] The main algorithms of the low-level control system include cavity field amplitude-phase feedback loop control and cavity frequency tuning loop control.

[0068] a) Cavity field amplitude-phase feedback loop control:

[0069] The schematic diagram of the cavity field amplitude-phase feedback loop control algorithm is as Figure 4 shown. The cavity field amplitude-phase feedback loop control adopts the vector control method in the I / Q domain.

[0070] ● Acquisition of two rf high-frequency signals: The reference signal REF and the cavity field feedback signal Pt first pass through down-conversion to obtain their IF intermediate-frequency sampling signals, and then are sent to a high-speed ADC for analog-to-digital conversion. The obtained digital signals use the Non-IQ algorithm inside the FPGA to obtain the orthogonal I / Q quantities of the reference signal and the cavity field feedback signal.

[0071] ● Acquisition of amplitude and phase: The orthogonal I / Q quantities of the reference signal and the cavity field feedback signal can obtain the amplitude and phase of the corresponding signals through the Cordic algorithm.

[0072] ● PI feedback control: The quadrature I / Q components of the reference signal are first normalized. The I / Q set values obtained from the reference amplitude-phase setting are used to perform vector rotation on the normalized quadrature I / Q components of the reference signal to obtain the I / Q set values ref_set_i / ref_set_q of the reference signal. The I / Q adjustment amounts obtained from the feedback amplitude-phase adjustment are used to perform vector rotation on the I / Q quadrature components of the cavity field feedback signal to obtain the adjusted I / Q amounts fdb_rot_i / fdb_rot_q of the feedback signal. The difference del_i between ref_set_i and fdb_rot_i is sent to the PI controller to obtain the in-phase component output signal pi_out_i; the difference del_q between ref_set_q and fdb_rot_q is sent to the PI controller to obtain the quadrature component output signal pi_out_q; pi_out_i and pi_out_q are sent to the DDS to obtain the intermediate frequency excitation digital signal, and then through the DAC digital-to-analog converter, the intermediate frequency excitation analog signal can be obtained. The intermediate frequency excitation analog signal is up-converted to obtain the RF excitation signal, and then through the RF switch, power source, circulator, and then sent into the high-frequency cavity to establish the field, thus completing the entire loop feedback control.

[0073] b) Cavity frequency tuning loop control:

[0074] The schematic diagram of the cavity frequency tuning loop control algorithm is as Figure 5 shown. The cavity frequency tuning loop control includes motor tuning feedback control and piezo piezoelectric ceramic tuning feedback control.

[0075] ● Acquisition of two-way rf high-frequency signals: The forward power signal Pf and the cavity field feedback signal Pt are first down-converted to obtain their IF intermediate frequency signals, and then sent to the high-speed ADC for analog-to-digital conversion. The obtained digital signals use the Non-IQ algorithm inside the FPGA to obtain the quadrature I / Q components of the forward power signal and the cavity field feedback signal.

[0076] ● Obtaining the cavity detuning angle: The I / Q adjustment amounts obtained from the forward power amplitude-phase adjustment are used to perform vector rotation on the quadrature I / Q components of the forward power signal to obtain the adjusted I / Q amounts forw_rot_i / forw_rot_q of the forward power signal. After passing through the cordic algorithm, forw_rot_i / forw_rot_q obtain the phase forw_angle of the forward power signal at the cavity port; the I / Q adjustment amounts obtained from the cavity field feedback amplitude-phase adjustment are used to perform vector rotation on the quadrature I / Q components of the cavity field feedback signal to obtain the adjusted I / Q amounts cav_rot_i / cav_rot_q of the cavity field feedback signal. After passing through the cordic algorithm, cav_rot_i / cav_rot_q obtain the phase cav_angle of the cavity field feedback signal; the cavity detuning angle detun_angle is obtained by subtracting forw_angle from cav_angle.

[0077] ● Piezo Tuning Loop: 1. Set the difference between the detuning angle load_angle and the cavity detuning angle detun_angle as dif_angle, and send dif_angle into the PI controller of the piezo tuning loop. Its output is filtered by a low-pass filter to obtain the piezo drive digital signal; 2. The piezo drive digital signal is converted into a piezo drive analog signal by a slow DAC; 3. The piezo drive analog signal is amplified by a piezo ceramic driver to obtain the piezo tuning high-voltage signal; 4. The piezo tuning high-voltage signal is sent to the piezo ceramic on the cavity side to realize the frequency adjustment of the high-frequency cavity.

[0078] ● Motor Tuning Loop: Set the difference between the detuning angle load_angle and the cavity detuning angle detun_angle as dif_angle. When the absolute value of dif_angle is greater than the motor start angle start_angle, dif_angle is sent into the PI controller. The output of the PI controller is not 0, and the motor pulse signal and direction signal are output to the motor driver to drive the motor to rotate and drive the tuning arm on the cavity side to adjust the frequency of the cavity. When the absolute value of dif_angle is less than the motor stop angle stop_angle, it means that the cavity frequency adjustment is in place, and the PI controller is reset to make the output of the PI controller 0, and then stop sending pulse signals to the motor, and the motor stops running, completing the tuning of the cavity frequency.

[0079] 4. Software Development

[0080] The software architecture block diagram of the low-level control system is as Figure 6 shown. The software system is developed based on the EPICS control system for the application of the low-level Input / Output Controller (IOC). The record support RecordSupport of the IOC accesses the Linux kernel through the low-level device driver. The Linux kernel obtains the socket data packet through the network driver; the low-level device driver mainly completes the read and write functions of the socket data packet based on the TCP / IP protocol, realizes the access of the IOC database application layer to the Linux kernel, and thus realizes the data interaction with the digital signal processing board, realizes the read and write of the internal registers of the FPGA, and further realizes the algorithm control of the low level. The database of the IOC publishes the process variable PV (Process Variable) on the network through the channel access CA (channel access). The upper control interface installed on the client OPI monitors and controls the PV quantity based on CS-Studio.

[0081] 4. System Integration and Debugging

[0082] After the digital signal processing board and the radio frequency front-end board are manufactured and the chips are soldered, the design of the low-level chassis needs to be carried out, and then integrated into a complete low-level control system. On the front panel of the chassis are mainly the power switch, LED status lights, radio frequency signal input interface, radio frequency signal excitation output interface, ceramic excitation output interface, etc., while on the rear panel are the input and output interfaces for motor drive, reset switch, trigger interface, network port, and 220V power input, etc.

[0083] The overall integrated debugging of the high-frequency system is as Figure 7 shown. The reference line provides a low-level RF reference signal, and the low-level control system collects the cavity field feedback signal Pt, the cavity forward power signal Pf, and the cavity reflected power signal Pr; the low-level RF excitation output signal is sent to the power source through the radio frequency switch, and the power source amplifies the RF excitation signal and then sends it to the high-frequency cavity through the circulator to build the field; the low-level system simultaneously tunes the frequency of the high-frequency cavity through the tuning driver including the motor driver and the piezo ceramic driver to achieve frequency control. The low-level system conducts network data interaction with the client OPI and the database server through the network.

[0084] Although specific embodiments of the present invention are disclosed for illustrative purposes, the purpose is to help understand the content of the present invention and implement it accordingly. Those skilled in the art can understand that: without departing from the spirit and scope of the present invention and the appended claims, various substitutions, changes, and modifications are possible. Therefore, the present invention should not be limited to the content disclosed in the best embodiments, and the scope of protection required by the present invention is defined by the scope of the claims.

Claims

1. A dedicated high-frequency low-level control system, characterized in that It includes a digital signal processing board and a radio frequency front-end board; the digital signal processing board mainly includes a clock distribution unit, an ADC digital-to-analog conversion unit, a DAC analog-to-digital conversion unit, an FPGA logic processing unit, and a cavity frequency tuning drive unit; The clock distribution unit is used to generate an ADC clock signal, a DAC clock signal, an FPGA working clock, and an IF intermediate frequency reference signal according to the input RF signal, and send them to the ADC digital-to-analog conversion unit, the DAC analog-to-digital conversion unit, the FPGA logic processing unit, and the radio frequency front-end board respectively; The clock distribution unit mainly includes a clock distribution chip and a CPLD chip, and the CPLD chip is used to configure clock distribution parameters for the clock distribution chip; The ADC digital-to-analog conversion unit is used to convert the intermediate frequency acquisition analog signal output by the radio frequency front-end board into a digital intermediate frequency signal and send it to the FPGA logic processing unit; The DAC analog-to-digital conversion unit is used to convert the DDS excitation signal output by the FPGA logic processing unit into an intermediate frequency excitation analog signal and send it to the radio frequency front-end board; The radio frequency front-end board is used to up-convert the intermediate frequency excitation analog signal to obtain a low-level RF excitation signal, amplify its power, and then send it to the high-frequency cavity for field building, and attenuate the cavity field back-collected signal and send it to the down-conversion channel for down-conversion to obtain the intermediate frequency acquisition analog signal and input it into the ADC digital-to-analog conversion unit; The cavity frequency tuning drive unit includes a motor slow tuning drive and a piezo ceramic fast tuning drive; The motor slow tuning drive drives the motor to operate according to the control signal of the FPGA logic processing unit to tune the frequency of the high-frequency cavity, and collects the position voltage signal of the motor tuning and sends it to the FPGA logic processing unit to control the electrical limit of the motor; the piezo ceramic fast tuning drive converts the digital signal of the FPGA logic processing unit driving the piezo ceramic of the high-frequency cavity into an analog signal and sends it to the ceramic driver to tune the frequency of the high-frequency cavity; The FPGA logic processing unit is used for data acquisition and loop control; among them, a) During the data acquisition process, convert the digital intermediate frequency signal into the quadrature quantity in the I / Q domain and filter out the high-frequency signals therein to obtain the quadrature I / Q quantity of the sampling signal; the sampling signals include RF reference signal, cavity field back-collected signal, cavity reflection power signal, and cavity forward power signal; b) The loop control includes amplitude-phase loop control of the cavity field and cavity frequency tuning loop control; wherein, the amplitude-phase loop control of the cavity field uses the vector control method in the I / Q domain to rotate the I component of the cavity field feedback signal to obtain fdb_rot_i, and rotates the Q component of the cavity field feedback signal to obtain fdb_rot_q; the difference between the set value ref_set_i of the cavity field amplitude-phase of the I component and fdb_rot_i is sent to the PI controller of the cavity field amplitude-phase loop to obtain the in-phase component output signal pi_out_i, and the difference between the set value ref_set_q of the cavity field amplitude-phase of the Q component and fdb_rot_q is sent to the PI controller to obtain the quadrature component output signal pi_out_q; pi_out_i and pi_out_q are modulated by the NCO controller inside the FPGA logic processing unit to obtain the DDS excitation signal of the intermediate frequency; The cavity frequency tuning loop control includes a motor tuning loop and a piezo tuning loop; the motor tuning loop obtains the forward phase forw_pha of the cavity and the cavity field phase cav_pha according to the quadrature I / Q quantities of the cavity forward power signal and the cavity feedback signal, and calculates the difference between forw_pha and cav_pha to obtain the cavity detuning angle detun_angle, and the difference between the cavity detuning angle detun_angle and the set detuning angle load_angle is used to obtain the phase difference dif_angle; dif_angle is sent to the PI controller of the motor tuning loop. When dif_angle is less than the motor start angle start_angle or greater than the negative start_angle, the output of the PI controller of the motor tuning loop is 0, and the motor is controlled to stop rotating. Otherwise, the output of the PI controller of the motor tuning loop is not 0, and the motor is controlled to start rotating; when dif_angle is greater than the motor stop angle stop_angle or less than the negative stop_angle, the PI controller of the motor tuning loop works normally, and generates a motor drive pulse signal pulse and a motor rotation direction signal dir according to the positive and negative values of the output of the PI controller of the motor tuning loop and sends them to the motor driver to drive the motor to operate and adjust the high-frequency cavity frequency; when dif_angle is less than the motor stop angle stop_angle and greater than the negative stop_angle, the output of the PI controller of the motor tuning loop is reset, and the rotation of the motor is stopped; and dif_angle is sent to the PI controller of the piezo tuning loop to generate the drive digital signal of the piezo ceramic, which is converted into a piezo drive analog signal and sent to the ceramic driver for amplification to obtain the piezo tuning high-voltage signal acting on the piezo ceramic of the high-frequency cavity, so as to realize the frequency tuning of the high-frequency cavity.

2. The dedicated high-frequency low-level control system according to claim 1, wherein The RF front-end board divides the input RF reference signal into 4 paths of RF signals through a 4-way power divider. One path is mixed with the IF intermediate-frequency reference signal output by the clock distribution unit to obtain the LO local oscillator signal. One path is input into the clock distribution unit for clock distribution. One path is sent to the down-conversion channel as a reference signal for down-conversion. One path is used as a backup.

3. The dedicated high-frequency low-level control system according to claim 1, wherein The RF front-end board mixes the IF reference signal output by the clock distribution unit with the input RF reference signal after low-pass filtering; then the mixed signal is amplified by an amplifier and then passes through a band-pass filter with the LO local oscillator frequency to obtain the LO local oscillator signal and divides it into 8 paths of LO signals. Two of them are directly output for backup or monitoring. The other 6 paths are amplified and used as the LO local oscillator signals and are respectively sent to a mixer including 1 up-conversion channel and 5 down-conversion channels; among them, the down-conversion channel is used to mix the collected RF signal with the LO signal through the mixer, amplify it by the amplifier, and then filter it through the low-pass filter to obtain the intermediate-frequency acquisition analog signal and input it into the ADC analog-to-digital conversion unit; the up-conversion channel mixes the intermediate-frequency excitation analog signal and the LO signal through the mixer, amplifies it by the amplifier, and then passes through a band-pass filter with the RF frequency to obtain a low-level RF excitation signal, and amplifies its power and then sends it to the high-frequency cavity to establish a field.

4. The dedicated high-frequency low-level control system according to claim 3, characterized in that, The collected RF signals include the reference signal REF, the cavity field backscattered signal Pt, the cavity forward power signal Pf, the cavity reflected power signal Pr, and the beam current signal Pb.

5. The dedicated high-frequency low-level control system according to claim 3, wherein Each up / down-conversion channel of the RF front-end board is respectively configured with a low-noise voltage stabilizing circuit.

6. The dedicated high-frequency low-level control system according to claim 1 or 2 or 3, characterized in that The Non-IQ algorithm is used to convert the digital intermediate-frequency signal into the orthogonal quantities in the I / Q domain.

7. The dedicated high-frequency low-level control system according to claim 1 or 2 or 3, characterized in that, The motor tuning loop rotates the orthogonal I / Q quantities of the cavity forward power signal and the cavity field backscattered signal through the vector rotation module and then respectively obtains the forward phase forw_pha of the cavity and the cavity field phase cav_pha through the cordic algorithm.

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