FPGA-based Ymodel protocol online loading method and system

Abstract

The invention provides a Ymodel protocol online loading method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: in a working mode, the FPGA receives an online loading instruction, receives and analyzes a Ymodel protocol, after the loading instruction is analyzed, firstly skips to a boot program of a base address 1 and rewrites an eeprom state register value, firstly automatically erases an area of an application program under the boot program, and then automatically erases the area of the application program; and after erasing is completed, application program data received by the Ymodel protocol is written from a base address 2, after flash data writing is completed, after an eeprom state register is modified, a main program is automatically jumped into, and loading is completed. According to the method, as long as the main device sends the online loading instruction, operations such as erasing and writing are all automatically realized by logic, and additional instructions do not need to be added. The method is implemented by FPGA logic, an IP core, especially a soft core, is not used, two software configuration items can be avoided in the design, the code transportability is high, the Ymodel protocol is a general protocol, multiple verification detection is achieved, and the universality is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of airborne equipment, and in particular relates to an FPGA-based Ymodel protocol online loading method and system. Background Art

[0002] With the development of electronic technology, airborne equipment has put forward higher requirements for the installation and maintenance of onboard equipment, requiring onboard equipment to be quickly replaced. At the same time, for the reliability of equipment upgrade and maintenance, it is required that the software of the equipment can be upgraded without disassembling the equipment to avoid problems such as improper installation by personnel or damage to parts during the disassembly and assembly process.

[0003] In order to facilitate software upgrades and subsequent expansion applications, upgrades can be performed through a remote network interface to achieve fully automated upgrades, save manpower and material resources, and improve maintenance reliability. On this basis, a Ymodel protocol online loading method and system based on FPGA is proposed. Summary of the Invention

[0004] The present invention mainly provides a method for online loading of the Ymodel protocol based on FPGA. The host computer software or the main device sends online upgrade instructions and data through the serial port. The FPGA receives the instructions and data sent by the main device and parses the Ymodel protocol to realize the upgrade of the FPGA application.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is: A Ymodel protocol online loading method based on FPGA, comprising the following steps: In working mode, FPGA receives online loading instructions, receives and parses the Ymodel protocol. After parsing the loading instruction, it first jumps to the boot program at base address 1 and rewrites the eeprom status register value. Under the boot program, the application area is automatically erased first. After the erasing is completed, the application data received by the Ymodel protocol is written starting from base address 2. After the flash data is written, the eeprom status register is modified and then automatically jumps to the main program to complete the loading.

[0006] Preferably, the FPGA receives an online loading instruction from a master device, where the master device is a master-end board or computer software, and can send online loading instructions and data according to the Ymodel protocol.

[0007] Preferably, the flash chip can store two different programs, namely a boot program in maintenance mode and an application program in normal mode, and interact with the FPGA via an SPI bus.

[0008] Preferably, the eeprom chip can store 3 bytes of data, has a redundant design, adopts majority voting, improves reliability, and is used to distinguish between a boot program and an application program.

[0009] Preferably, the FPGA chip can parse the Ymodel protocol and simulate the spi bus protocol and the i2c bus protocol.

[0010] The present invention also discloses an FPGA-based Ymodel protocol online loading system, comprising: The serial port receiving module is used to convert the serial data sent by the serial port into parallel data and pass it to the back-end for processing; Ymodel protocol parsing module, used to parse the Ymodel protocol, convert the online loading instructions and data sent by the master device into internal commands to control the reading and writing of the eeprom control module and the erasing and reading and writing of the flash control module; The flash control module is used to erase, write, and read the flash chip through the SPI bus and update the application program; The eeprom control module is used to store and read the program status value of the eeprom chip through the I2C bus.

[0011] Preferably, the master device is a master-end board or computer host software, which can send online loading instructions and data according to the Ymodel protocol.

[0012] Preferably, the flash chip in the flash control module can store two different programs, namely a boot program in maintenance mode and an application program in normal mode.

[0013] Preferably, the eeprom chip in the eeprom control module can store 3 bytes of data, perform redundant design, adopt majority voting, improve reliability, and be used to distinguish between a boot program and an application program.

[0014] Compared with the prior art, the present invention has the following beneficial effects: In the present invention, the master device only needs to send an online loading instruction, and operations such as erasing and writing are all automatically implemented by logic without adding additional instructions.

[0015] The present invention is implemented by FPGA logic and does not use IP core, especially soft core. The design can avoid two software configuration items and the code is highly portable.

[0016] The Ymodel protocol in the present invention is a universal protocol with multiple verification detection, high transmission reliability, unified with other MCUs, and high universality.

[0017] The present invention will be explained in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the principle of the present invention; Figure 2 It is the FPGA logic design block diagram of the present invention; Figure 3 It is the Ymodel protocol flow chart of the present invention. DETAILED DESCRIPTION

[0019] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described in the text. On the contrary, these embodiments are provided to make the content disclosed in the present invention more thorough and comprehensive.

[0020] Example 1: Reference Figure 1 This embodiment provides an FPGA-based Ymodel protocol online loading method, including the following steps: In normal working mode, FPGA receives online loading instructions, receives and parses the Ymodel protocol. After parsing the loading instruction, it first jumps to the boot program at base address 1 and rewrites the eeprom status register value. Under the boot program, the application area is automatically erased first. After the erasing is completed, the application data received by the Ymodel protocol is written starting from base address 2. After the flash data is written, the eeprom status register is modified and it automatically jumps to the main program to complete the loading.

[0021] Specifically, such as Figure 1 As shown, it is a hardware schematic diagram of an FPGA-based Ymodel protocol online loading method provided by the present invention, and is also a schematic diagram of the principle of the present invention.

[0022] The master device described in the figure is a master-end board or computer host software, which can send online loading instructions and data according to the Ymodel protocol.

[0023] The flash chip described in the figure can store two different programs, namely the boot program in maintenance mode and the application program in normal mode, and interacts with the FPGA through the SPI bus.

[0024] The eeprom chip described in the figure can store 3 bytes of data, has a redundant design, uses majority voting to improve reliability, and is used to distinguish between the boot program and the application.

[0025] The FPGA chip described in the figure is the main controller of this design, which can parse the Ymodel protocol and simulate the implementation of the spi bus protocol and the i2c bus protocol.

[0026] Example 2: Reference Figure 2-3 The present invention provides a Ymodel protocol online loading system based on FPGA, comprising: The serial port receiving module is mainly used to convert the serial data sent by the serial port into parallel data and pass it to the back-end for processing; The Ymodel protocol parsing module is used to parse the Ymodel protocol and convert the online loading instructions and data sent by the master device into internal commands to control the reading and writing of the eeprom control module and the erasing and reading and writing of the flash control module. It is the core module of this design. The flash control module is used to erase, write, and read the flash chip through the SPI bus and update the application program; The eeprom control module is used to store and read the program status value of the eeprom chip through the I2C bus.

[0027] Among them, the detailed flowchart of Ymodel protocol analysis is as follows Figure 3 As shown, the specific process is as follows: Initial state: The system is in IDLE state.

[0028] ‌Read IIC address value after power-on‌: When power is turned on, the system reads the IIC address value.

[0029] ‌Heartbeat Status‌: If the read IIC address value is equal to "07", it jumps to the end frame state.

[0030] Otherwise, continue to detect the signal status.

[0031] ‌Sending “06” completed‌: The system sends the “06” signal to complete.

[0032] ‌Send “C” status‌: The system sends a “C” status.

[0033] Detection data frame: The system detects data frames.

[0034] ‌Detect data frame packet number‌: If "04" is detected, jump to the end frame state.

[0035] Otherwise, continue to detect the data frame packet number.

[0036] ‌Main program‌: Send the write IIC command "01".

[0037] Send a data packet.

[0038] Count packets until the last one.

[0039] Send cancel signal status "C".

[0040] ‌Detecting Data Frames‌: The system continues to detect data frames.

[0041] Data frame packet number: If "02" is detected, jump to the end frame state.

[0042] Otherwise, continue to detect the data frame packet number.

[0043] ‌Receiving Data‌: The system receives data until the last frame of data is received.

[0044] If the number of packets received does not match the expected number, a NAK signal status is sent.

[0045] ‌Detecting Data Frames‌: The system continues to detect data frames.

[0046] ‌Detect data frame packet number‌: If "01" is detected, jump to the end frame state.

[0047] Otherwise, continue to detect the data frame packet number.

[0048] Data processing: The system processes received packets until all packets have been processed.

[0049] If an error occurs during processing, a negative status is sent.

[0050] ‌End Frame State‌: The system enters the End Frame State.

[0051] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

[0052] Read IIC address value after power-on: After powering on, the device first reads the IIC address value. Detect signal status: Detects whether the current signal status is ACK IDLE. Send "C" character: If ACK IDLE is detected, send a "C" character. Detect data frame STX: Monitors whether the STX (frame header) of the data frame is received. Write data frame packet number "07": After detecting the data frame STX, write the data frame packet number to "07". Count data packet status: Counts the data packet status until the last frame. Send write IIC instruction: When the instruction "01" is detected, send the write IIC instruction. Generate write instruction: Generate a write instruction "01" and send it. Detect the last frame of data in the data frame: Monitors whether the data frame is the last frame of data. Inverted frame number status: If it is the last frame of data, process the inverted frame number status. Continuous transmission status: Processes the continuous transmission status. ‌Request signal status‌: Detect instruction "02" and process the request signal status. ‌Cancel signal status‌: Send the "C" character once every 1 second to process the cancel signal status. ‌Detect the last packet of data frame reception‌: Monitor whether the data frame reception is the last packet. ‌Frame data status‌: If it is the last packet, process the frame data status. ‌Detect first frame SOH‌: Monitor whether it is the first frame SOH (frame header). ‌File size and file name size reception data‌: Receive data on file size and file name size. ‌Data packet byte count‌: Count data packet bytes until it reaches 1024 bytes. ‌CRC check‌: Perform CRC check on the received data. ‌End frame detection‌: Monitor whether the end frame "02" is received. ‌Main program‌: If the end frame is detected, the main program continues to execute related operations.

Claims

1. A Ymodel protocol online loading method based on FPGA, characterized in that: The steps include: In working mode, FPGA receives online loading instructions, receives and parses the Ymodel protocol. After parsing the loading instruction, it first jumps to the boot program at base address 1 and rewrites the eeprom status register value. Under the boot program, the application area is automatically erased first. After the erasing is completed, the application data received by the Ymodel protocol is written starting from base address 2. After the flash data is written, the eeprom status register is modified and then automatically jumps to the main program to complete the loading.

2. A Ymodel protocol online loading method based on FPGA according to claim 1, characterized in that, FPGA receives online loading instructions from the master device, which is a master board or computer software, and can send online loading instructions and data according to the Ymodel protocol.

3. A Ymodel protocol online loading method based on FPGA according to claim 1, characterized in that, The flash chip can store two different programs, namely a boot program in maintenance mode and an application program in normal mode, and interacts with the FPGA via an SPI bus.

4. A Ymodel protocol online loading method based on FPGA according to claim 1, characterized in that, The eeprom chip can store 3 bytes of data, has a redundant design, adopts majority voting, improves reliability, and is used to distinguish between a boot program and an application program.

5. A Ymodel protocol online loading method based on FPGA according to claim 1, characterized in that, The FPGA chip can parse the Ymodel protocol and simulate the spi bus protocol and the i2c bus protocol.

6. A Ymodel protocol online loading system based on FPGA, characterized in that: The system includes: The serial port receiving module is used to convert the serial data sent by the serial port into parallel data and pass it to the back-end for processing; Ymodel protocol parsing module, used to parse the Ymodel protocol, convert the online loading instructions and data sent by the master device into internal commands to control the reading and writing of the eeprom control module and the erasing and reading and writing of the flash control module; The flash control module is used to erase, write, and read the flash chip through the SPI bus and update the application program; The eeprom control module is used to store and read the program status value of the eeprom chip through the I2C bus.

7. The FPGA-based Ymodel protocol online loading system according to claim 1, characterized in that: The master device is a master-end board or computer software, which can send online loading instructions and data according to the Ymodel protocol.

8. The FPGA-based Ymodel protocol online loading system according to claim 1, characterized in that: The flash chip in the flash control module can store two different programs, namely a boot program in maintenance mode and an application program in normal mode.

9. The FPGA-based Ymodel protocol online loading system according to claim 1, characterized in that: The eeprom chip in the eeprom control module can store 3 bytes of data, is designed for redundancy, and adopts majority voting to improve reliability, and is used to distinguish between a boot program and an application program.

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