Resonant converter output overload and short circuit protection system and method without output current detection

Abstract

The invention discloses a resonant converter output overload and short circuit protection system and method without output current detection, and belongs to the technical field of power electronic converters. When a resonance tank current peak detection signal is equal to a ramp signal to trigger a comparator to output a high-level pulse, the edge triggers the microcontroller to interrupt, and the register value of the current ramp signal is captured immediately after interruption, so that a resonance current peak can be obtained. After an output overload and short circuit fault mark based on the value and the output voltage is triggered, the switching frequency is adjusted through the slope parameter self-adaptive controller to achieve output overload protection, and when the output overload is serious or short circuit occurs, rapid wave sealing protection can be achieved through a software code and a hardware comparator. And meanwhile, the soft start function of the resonant converter can be realized by gradually decreasing the initial value of the set slope descent rate cycle by cycle during starting. The control performance of the resonant converter is improved under the control of the peak current, and the output overload and short circuit protection function can be realized without adding an output current detection circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic converters, and in particular to a resonant converter output overload and short circuit protection system and method without output current detection. Background Art

[0002] A resonant converter is a power electronic converter built based on a resonant circuit, in which the resonant circuit is usually composed of capacitors and inductors. Both inductors and capacitors are energy storage devices. The resonant cavity circuit composed of the inductor and capacitor elements in the resonant converter can realize the zero-voltage switch (ZVS) or zero-current switch (ZCS) soft switching of the resonant converter switch tube at resonance, allowing the resonant converter to operate at a higher switching frequency. It has the advantages of high frequency, high efficiency, high power density, and a wide input and output voltage range, and is widely used.

[0003] Among many types of resonant converters, LLC resonant converters have been widely used due to their excellent performance. Currently, direct frequency control (DFC) is the most commonly used control method for LLC resonant converters. However, analysis of the control-output transfer function of LLC resonant converters [B. Yang and F. C. Lee, “Small-signal analysis for LLC resonant converter,” in Proc. Center Power Electron. Syst. Semin, 2003, pp. 133–149.] shows that the control-output transfer function of LLC resonant converters has multiple poles on the frequency response Bode plot, making it difficult to achieve fast dynamic performance under wide input and output conditions. In order to improve the dynamic performance of LLC resonant converters, the literature [C.Hao, E.K.K.Sng, and K.-J.Tseng, “Generalized optimal trajectory control for closed loop control of series-parallel resonant converter,” IEEE Trans.Power Electron., vol.21, no.5, pp.1347–1355, Sep.2006.] proposed an optimal trajectory control method for LLC resonant converters based on state plane analysis. However, this method requires the measurement of three state variables: resonant current, resonant voltage, and magnetizing current. Moreover, due to the existence of multiple resonant modes in LLC resonant converters, the calculation of the corresponding state variables is extremely complex, making this method difficult to implement. The literature [Z.Hu, Y.-F.Liu, and PCSen, “Bang-bang charge control for LLC resonant converters,” IEEE Trans.Power Electron., vol.30, no.2, pp.1093–1108, Feb.2015.] implemented hysteretic charge control (BBCC) using the resonant capacitor voltage of LLC resonant converters.The literature [R.Yang, BAMcDonald, and Y.Li,"Investigation on the small signal characteristic based on the LLC hybrid hysteretic charge control,"CPSS Trans.Power Electron.Appl.,vol.4,no.2,pp.128–142,Jun.2019.] proposed a hybrid hysteretic charge control method to enable the LLC resonant converter to obtain better transient performance and improve stability. Furthermore, the literature [Q.Xu et al.,"A nonlinear load current feedforward strategy for the charge-controlled LLC converter and its digital implementation to improve the dynamic response,"IEEE Trans.Ind.Electron.,vol.70,no.10,pp.10195–10203,Oct.2023.] added a nonlinear load current feedforward control method on the basis of charge control, further improving the dynamic performance of the LLC resonant converter. However, the hardware architecture cost of the digital processor (DSP) + programmable logic device (CPLD) is relatively high. The aforementioned charge control method does not directly control the resonant current. Furthermore, the integral capacitor value range is limited and introduces additional poles. Furthermore, most slope compensation is implemented using analog circuits, reducing control flexibility.

[0004] The LLC resonant converter operates normally in the ZVS region, but overload conditions often cause it to operate in the ZCS region. The most serious disadvantage of ZCS is that the switch turns on with hard switching, which increases turn-on losses and generates noise and EMI. Furthermore, the diode turns off with a very large dv / dt, generating a high reverse recovery current spike. This current significantly increases losses in the switch and diode, causing significant heat generation. In extreme cases, damage to the switch and diode can lead to complete system failure. The short-circuit condition operates almost identically to the overload condition, but is even more severe, with higher current levels and greater susceptibility to damage and failure of the switch and diode.

[0005] There are certain research results in hardware and control for the output overload and short-circuit protection of LLC resonant converters. The circuit topology clamping method was first proposed by Yang Bo [B. Yang, F.C. Lee and M. Concannon, "Over current protection methods for LLC resonant converter," Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2003. APEC'03, Miami Beach, FL, USA, 2003, pp.605-609 vol. 2, doi: 10.1109 / APEC.2003.1179276.], which uses a split resonant capacitor and a parallel clamping diode to achieve a switching cycle-by-cycle current limiting effect without control intervention. References [X. Xie, J. Zhang, C. Zhao, Z. Zhao, and Z. Ming, "Analysis and optimization of LLC resonant converter with a novel over-current protection circuit," IEEE Trans.PowerElectron.,vol.22,no.2,pp.435–443,Mar.2007.] used an additional clamping hardware circuit, but its effect was mediocre.References [Liu Shuo, Zhang Fanghua, Ren Ren. Short-circuit current control method for full-bridge LLC converter (I) - theoretical analysis [J]. Transactions of China Electrotechnical Society, 2015, 30 (10): 226-233.] proposed two switch control methods based on phase shifting, frequency increase and frequency decrease, which are suitable for limiting the short-circuit current of full-bridge LLC converter, and have good short-circuit current limiting effect; References [C. Fei, F. C. Lee and Q. Li,"Digital Implementation of Soft Start-Up and Short-Circuit Protection for High-Frequency LLC Converters With Optimal Trajectory Control (OTC)," in IEEE Trans on Power Electronics, vol. 32, no. 10, pp. 8008-8017, Oct. 2017.] Based on optimal trajectory control (OTC), a method for realizing soft start and short-circuit protection of LLC converters by using a low-cost microcontroller (MCU) with minimum stress and optimal energy delivery is proposed. The method can be applied to high-frequency LLC converters without increasing the cost of the controller and has a good protection effect. However, the microcontroller needs to process a large amount of calculation. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a resonant converter output overload and short-circuit protection system and method without output current detection. This system aims to detect the resonant current peak without any delay or analog-to-digital conversion, achieving peak current control of the resonant converter without performing any computational processing on the resonant current, and improving the resonant converter's control performance. Furthermore, the system achieves output overload and short-circuit protection for the resonant converter without the need for any additional circuitry, including but not limited to output current detection. Furthermore, the resonant converter's soft-start function is achieved by gradually decreasing the initial value of the ramp-down rate set on a cycle-by-cycle basis during startup.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is: a resonant converter output overload and short-circuit protection system without output current detection, comprising a resonant converter unit and a control unit, wherein the resonant converter unit includes a DC input circuit, a switch bridge arm circuit, a resonant cavity and high-frequency transformer circuit, and a rectifier filter circuit connected in series in sequence; the control unit includes a resonant current peak detection circuit for realizing a controlled object detection function, a microcontroller for controlling the peak current, and a drive circuit with a power amplification function connected in series in sequence, wherein the resonant current peak detection circuit includes a resonant current detection subcircuit and a resonant current peak holding subcircuit connected in series in sequence, the microcontroller includes an outer loop controller, an inner loop controller, an EPWM module, and a parameter adaptive control protection unit at the control logic level, the inner loop controller includes a ramp generator, a DAC digital-to-analog converter, and an analog comparator COMP connected in series in sequence, and the parameter adaptive control protection unit includes an output overload and short-circuit fault flag and a ramp parameter adaptive controller.

[0008] The further improvement of the technical solution of the present invention is that: the resonant current detection subcircuit is an isolated current peak detection circuit based on a current transformer or a Hall sensor; the resonant current peak holding subcircuit includes a diode D1, a capacitor C1 and an auxiliary switch tube S a , wherein the anode of the diode D1 of the resonant current peak holding sub-circuit is connected to the output end of the resonant current detection sub-circuit; the cathode of the diode D1 of the resonant current peak holding sub-circuit is connected to the positive electrode of the capacitor C1 and the auxiliary switch tube S a The drain of capacitor C1 is connected to the negative electrode of auxiliary switch S a The source of is connected to the voltage zero level reference GND, that is, the capacitor C1 and the auxiliary switch tube S a Connect in parallel; the resonant current detection subcircuit has a conversion ratio coefficient of k ICS The current in the branch where the resonant current is located or the branch associated with the resonant current is converted into a voltage signal and output to the input end of the resonant current peak holding sub-circuit; the auxiliary switch tube S a Used to construct the capacitor C1 voltage discharge circuit to achieve the capacitor C1 voltage reset function; the resonant current peak detection circuit output signal v ILrSamp That is the voltage across capacitor C1 in the resonant current peak holding subcircuit; the voltage across capacitor C1 v ILrSamp After the output voltage signal of the resonant current detection subcircuit rises to the positive peak value, the peak hold function is realized due to the reverse cutoff of the diode D1; the capacitance value of capacitor C1 ranges from a few pF to hundreds of μF, that is, the capacitance value has no effect on the peak hold result within a very wide range; the output signal v of the resonant current peak detection circuit ILrSamp and the resonant current i Lr The expression is:

[0009]

[0010] A further improvement of the technical solution of the present invention is that: the switching bridge arm circuit in the resonant converter unit includes at least one switching half-bridge structure; the resonant cavity and high-frequency transformer circuit include at least one inductor, capacitor and transformer, and the inductor, capacitor and transformer are interconnected.

[0011] A method for output overload and short-circuit protection of a resonant converter without output current detection.

[0012] When the resonant converter unit does not have an output overload or short-circuit fault, the resonant converter unit adopts a dual closed-loop control system consisting of an inner loop controller and an outer loop controller based on the peak current control of the resonant current peak value. The specific steps are as follows:

[0013] Step 1: The outer loop controller is combined with the inner loop controller of the peak current control based on the peak value of the resonant current. The analog comparator COMP obtains the analog signal at the inverting input terminal, that is, the given reference signal of the inner loop controller is obtained;

[0014] Step 2: Obtain the current peak detection signal, and the analog comparator COMP obtains the analog signal at the non-inverting input terminal, that is, the feedback signal of the inner loop controller;

[0015] Step 3: The analog comparator COMP compares the analog signal at the inverting input terminal with the analog signal at the non-inverting input terminal. The EPWM module performs a logic operation based on the comparison result and outputs a control signal.

[0016] When an output overload or short circuit fault occurs in the resonant converter unit, the specific steps for implementing output overload or short circuit fault protection in the resonant converter unit under the dual closed-loop control of the inner loop controller based on the peak current control of the resonant current peak value and the outer loop controller are as follows:

[0017] Step 4: triggering the output overload and short circuit fault flags based on the resonant current peak value and output voltage detection signal;

[0018] Step 5: The output of the outer loop controller is limited to the maximum value i LrpkrefMax At the same time, the ramp parameter adaptive controller adjusts the ramp down rate value per unit clock cycle digital value V Slope_Adj Repeat step 3 to complete the switching frequency f s Regulation, suppressing the increase of primary and secondary current of the transformer due to output overload fault, which may damage the switch tube and diode, and completing the output overload protection function;

[0019] Step 6: When the output overload and short-circuit fault flags determine that the resonant converter unit has a serious overload or even a short-circuit fault, the software is blocked after comparing the code with the preset short-circuit protection threshold. Alternatively, other analog comparators built into the microcontroller unit are compared with the preset short-circuit protection threshold to trigger the EPWM TZ (Trip-Zone) unit output protection action, completing hardware-level fast protection and realizing dual software and hardware protection functions.

[0020] The further improvement of the technical solution of the present invention is that the specific steps of step 1 are as follows:

[0021] Step 1.1: Output ramp maximum value i of the outer loop controller Lrpkref And input it to the ramp generator of the microcontroller's built-in inner loop controller;

[0022] Step 1.2: The ramp generator is set to the maximum value i Lrpkref Based on the slope compensation control algorithm, the negative slope signal v with slope compensation is obtained after the DAC digital-to-analog converter of the inner loop controller is used for calculation. Ramp ;

[0023] Among them, the slope compensation control algorithm is: with slope compensation negative slope signal v Ramp is a piecewise function, at t=[(n - 1)T s / 2,nT s / 2], that is, in the first half of the switching cycle, set v Ramp is a constant value; at t=[nT s / 2,nT s ], that is, in the second half of the switching cycle, set v Ramp is a negative slope ramp signal with a constant digital slope value of λ; and establishes a control signal switching frequency f for the switching half-bridge switch tube of the switching bridge arm circuit. s The mathematical model between the outer loop controller and the inner loop controller with peak current control based on the peak value of the resonant current is shown in Figure 2. The clock period of the microcontroller is T Sysclk , and the slope compensation control algorithm sets the digital value of the unit clock cycle ramp rate to V Slope , then the expression of the digital slope λ of the ramp signal is:

[0024]

[0025] Final switching frequency f s and the outer loop controller output i Lrpkref The inner loop controller variable parameters of the peak current control based on the resonant current peak include the microcontroller clock period T Sysclk , Slope unit clock cycle ramp down rate value digital value VSlope And the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp The expression between them is:

[0026]

[0027] In formula (3), α is the ADC analog-to-digital conversion coefficient.

[0028] Step 1.3: Convert the negative slope signal v with slope compensation Ramp As the analog signal of the inverting input terminal of the analog comparator COMP.

[0029] A further improvement of the technical solution of the present invention is that: in step 2, the input end of the resonant current peak detection circuit is connected to the branch where the resonant current is located or the resonant current associated branch, and the current in the branch where the resonant current is located or the resonant current associated branch is converted by a proportional coefficient k ICS The resonant current detection subcircuit and the output v after the resonant current peak holding subcircuit realizes the peak holding function ILrSamp It is directly connected to the non-inverting input of the analog comparator COMP of the microcontroller's internal loop controller, and the resonant current peak detection signal v ILrSamp From the detection of the current in the branch where the resonant current is located or the branch associated with the resonant current to the non-inverting input terminal of the analog comparator COMP of the loop controller in the microcontroller, the entire process does not go through any delay or analog-to-digital conversion link.

[0030] The further improvement of the technical solution of the present invention is that the specific steps of step 3 are as follows:

[0031] Step 3.1: Connect the analog comparator COMP non-inverting input terminal v ILrSamp Signal and inverting input terminal v Ramp The signals are compared;

[0032] Step 3.2: When the non-inverting input of analog comparator COMP is ILrSamp The signal is greater than the inverting input v Ramp signal, the analog comparator COMP outputs a high-level pulse signal; when the analog comparator COMP's non-inverting input terminal v ILrSamp The signal is less than the inverting input v Ramp signal, the analog comparator COMP output is always a low-level signal; the EPWM module only controls and processes when the analog comparator COMP outputs a high-level pulse signal, and the analog comparator COMP outputs a low-level signal without affecting the EPWM module;

[0033] Step 3.3: The EPWM module is controlled according to the high-level pulse signal output by the analog comparator COMP. The specific process can be divided into:

[0034] Step 3.3.1: The driving signal of the switch tube of the switching half-bridge structure in the switching bridge arm circuit is named V Drive1 and V Drive2 , driving signal V Drive1 By V Gs1 Control, drive signal V Drive2 By V GS2 Control, and V Gs1 and V Gs2 is a complementary relationship, that is, V Drive1 and V Drive2 There is a complementary relationship between them; the EPWM module adopts the up-counting mode, and the microcontroller software algorithm sets the analog comparator COMP to output a high-level pulse signal as the interrupt source signal;

[0035] Step 3.3.2: When the analog comparator COMP outputs a high-level pulse signal, the software algorithm in the microcontroller enters the interrupt link, and the EPWM module outputs the control signal V Gs1 Immediately switch from high level signal to low level signal; immediately capture the ramp signal value v at that moment after entering the interrupt subroutine Ramp , get the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp , combined with formula (1), the resonant current peak value can be obtained; then the ramp generator is reset immediately, v Ramp Restore to the initial value; then capture the EPWM module time base counter value TBCTR, multiply it by 2 and add a compensation value as the EPWM module period register value TBPRD; through TBPRD, the control signal switching frequency f of the current switching bridge arm circuit switching half-bridge switch tube can be obtained s ; and the control signal V Gs2 After the dead time delay set by the software algorithm, the low level signal is switched to a high level signal. This stage is the first half of the switching cycle described in step 1.2. At this time, v Ramp is a constant value;

[0036] Step 3.3.3: When the time base counter value TBCTR counts up to the period register value TBPRD, that is, TBCTR=TBPRD, the control signal V Gs2 Immediately switch from high level signal to low level signal, the time base counter value TBCTR is reset to 0, and the ramp generator is set, v Ramp The digital slope value is constant at a negative slope of λ and it starts to decrease. This stage is the second half of the switching cycle described in step 1.2. At this time, v Ramp is a negative slope ramp signal with a constant digital slope value of λ, and the control signal V Gs1The low-level signal is switched to a high-level signal only after the dead-time delay set by the software algorithm;

[0037] Step 3.3.4: Analog comparator COMP inverting input v Ramp The signal decreases at a negative slope with a constant digital slope value of λ until it reaches the same phase input terminal v of the analog comparator COMP. ILrSamp When the signals are equal, the analog comparator COMP starts to output a high-level pulse signal, and the software algorithm in the microcontroller enters the interrupt link. The subsequent process is consistent with steps 3.3.2 and 3.3.3, and the cycle is repeated;

[0038] Step 3.4: Finally, the EPWM module outputs the control signal V Gs1 and V Gs2 After the driving circuit, the switching half-bridge switch tube of the switching bridge arm circuit of the resonant converter unit and the auxiliary switch tube S of the resonant current peak detection circuit are a Control is performed to realize the resonant current peak control of the resonant converter unit, and the voltage v across the capacitor C1 of the resonant current detection sub-circuit is ILrSamp The end time of peak hold is when the analog comparator outputs a high level pulse signal, and the auxiliary switch tube S a The driving signal is logically the switch control signal V of the switch bridge circuit half-bridge structure. Gs1 The result of a NOT logical operation.

[0039] A further improvement of the technical solution of the present invention is that the specific steps of step 5 are as follows:

[0040] Step 5.1: After the output overload and short circuit fault flags are triggered, the output value of the outer loop controller is limited to the maximum value i LrpkrefMax , and capture the current moment of the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp and the control signal switching frequency f s_current ;

[0041] Step 5.2: Calculate the adjustment value V of the digital quantity of the ramp down rate value per unit clock cycle according to formula (3): Slope_Adj :

[0042]

[0043] Step 5.3: Set the ramp down rate per clock cycle to the digital value V Slope Updated to V Slope_Adj , the new ramp unit clock cycle ramp down rate value digital quantity V Slope_Adj Next, the switching frequency f s New Update, that is:

[0044]

[0045] Step 5.4: Repeat steps 5.1-5.3 above to achieve adaptive control of ramp parameters.

[0046] A further improvement of the technical solution of the present invention is that both the inner loop controller and the outer loop controller of the peak current control based on the resonant current peak are implemented in the microcontroller by the software control algorithm and its built-in peripherals, that is, a fully digital control method; at the same time, the ramp function can be written by software code to replace the hardware ramp generator.

[0047] A further improvement of the technical solution of the present invention is that: by setting the maximum initial value V of the digital quantity of the ramp down rate value per clock cycle Slope_Ini and stable value V Slope , at startup V Slope_Ini Decreases to V Slope , which can realize the soft start function of the resonant converter.

[0048] Due to the adoption of the above-mentioned technical solution, the present invention achieves the following technical advancements: by providing a resonant converter peak current detection circuit, resonant current peak detection can be completed without any delay or analog-to-digital conversion. By introducing a slope compensation link, the stability performance of the converter is effectively improved. By providing an analog comparator and corresponding control method, peak current control can be achieved without performing any calculations on the resonant current, greatly improving the converter's control bandwidth and dynamic response performance. At the same time, without the need to add any additional detection circuits, including but not limited to output current, the resonant converter output overload and short-circuit protection functions can be implemented. Furthermore, the initial value of the ramp-down rate is set to decrease cycle by cycle at startup to achieve the soft start function of the resonant converter. The method of the present invention is implemented by the combination of a microcontroller software algorithm and the microcontroller's built-in analog peripheral module, which can realize a fully digital control method with more flexible control and lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0050] Figure 1 It is a circuit and control structure diagram of the present invention;

[0051] Figure 2This is a resonant current peak detection circuit diagram of the present invention;

[0052] Figure 3 This is a waveform diagram of simulation results of a resonant current peak detection circuit with different capacitance values of the capacitor C1 of the present invention;

[0053] Figure 4 is a circuit and control structure diagram of an embodiment of the present invention;

[0054] Figure 5 This is a key waveform diagram of the resonant converter according to the embodiment of the present invention when the switching frequency is equal to the resonant frequency.

[0055] Figure 6 These are key waveform diagrams of the LLC resonant converter according to an embodiment of the present invention operating in the startup phase, without an output overload or short-circuit fault, and with an output overload or short-circuit fault;

[0056] Figure 7 1. The circuit simulation results waveform diagram of the LLC resonant converter according to the embodiment of the present invention are respectively shown in the startup phase, when no output overload or short-circuit fault occurs, and when an output overload or short-circuit fault occurs; DETAILED DESCRIPTION

[0057] The present invention is described in further detail below in conjunction with the embodiments:

[0058] In order to quickly detect and control the current in the branch where the resonant current of the resonant converter is located or the resonant current associated branch, the technical solution principle adopted by the present invention is as follows: using an isolated current peak detection circuit based on a current transformer or a Hall sensor to obtain a weak signal that truly reflects the peak value of the resonant current, directly detecting and controlling the resonant current peak in real time without any delay or analog-to-digital conversion link, the resonant current peak detection circuit outputs a signal v ILrSamp and the resonant current i Lr The expression is:

[0059]

[0060] where k ICS is the current detection proportional coefficient, and it can be seen that the resonant current peak detection signal v ILrSamp and the resonant current i of the object being detected Lr There is only a proportional relationship between them, and there are no links such as inertia, delay, integration, and analog-to-digital conversion.

[0061] According to the above principle, Figure 1The present invention provides a circuit diagram of a resonant converter output overload and short-circuit protection system without output current detection and a control structure diagram. Specifically, it includes a resonant converter unit 10 and a control unit 20, wherein the resonant converter unit 10 includes a DC input circuit 110, a switching bridge arm circuit 120, a resonant cavity and high-frequency transformer circuit 130, and a rectifier filter circuit 140 connected in series in sequence; the control unit 20 includes a resonant current peak detection circuit 210 for realizing a controlled object detection function, a microcontroller 220 for controlling the peak current, and a drive circuit 230 for a power amplification function, which are connected in series in sequence, wherein the resonant current peak detection circuit 210 includes a resonant current detection subcircuit 211 and a resonant current peak holding subcircuit 212 connected in sequence, and the microcontroller 220 includes an outer loop controller 221, an inner loop controller 222, an EPWM module 223, and a parameter adaptive control protection unit 224 at the control logic level, wherein the inner loop controller 222 includes a ramp generator, a DAC digital-to-analog converter, and an analog comparator COMP connected in series in sequence, and the parameter adaptive control protection unit 224 includes an output overload and short-circuit fault flag and a ramp parameter adaptive controller.

[0062] Specifically, the specific connection relationship between the resonant current peak current control inner loop and the outer loop control is as follows: the outer loop regulator 221 outputs the slope maximum value i Lrpkref And input it to the ramp generator, the ramp generator is at the maximum value i Lrpkref Based on the corresponding algorithm configuration operation and after the comparator DAC digital-to-analog converter, a negative slope signal v with slope compensation is obtained. Ramp As the analog signal of the inverting input terminal of the analog comparator; the input terminal of the resonant current peak detection circuit 210 is connected to the branch where the resonant current is located or the resonant current associated branch, and the current in the branch where the resonant current is located or the resonant current associated branch is converted by a proportional coefficient k ICS The resonant current detection sub-circuit 211 and the output v after the resonant current peak holding sub-circuit 212 realizes the peak holding function ILrSamp It is directly connected to the non-inverting input of the analog comparator of the loop controller 222 in the microcontroller 220, and this process does not go through any delay or analog-to-digital conversion link; the high-level pulse signal output by the analog comparator is input to the EPWM module 223 for logic operation, and the pulse signal output by the EPWM module 223 is controlled by the driving circuit 230 to control the auxiliary switch tube of the resonant converter switch bridge circuit 120 and the resonant current peak detection circuit 210, thereby realizing the resonant current peak control of the resonant converter.

[0063] Figure 2The structure diagram of the resonant current peak detection circuit provided by the output overload and short circuit protection system of the resonant converter without output current detection according to the present invention is as follows: the resonant current peak detection circuit 210 includes a resonant current detection subcircuit 211 and a resonant current peak holding subcircuit 212; the resonant current detection subcircuit 211 includes the following components: Figure 2 (a) and Figure 2 (b) shows an isolated current peak detection circuit diagram based on a current transformer and a Hall sensor; the resonant current peak holding subcircuit 212 is composed of a diode D1, a capacitor C1 and an auxiliary switch tube S a The anode of the resonant current peak holding sub-circuit 212 of the diode D1 is connected to the output end of the resonant current detection sub-circuit; the cathode of the resonant current peak holding sub-circuit 212 of the diode D1 and the positive electrode of the capacitor C1 and the auxiliary switch tube S a The drain of capacitor C1 is connected to the negative electrode of auxiliary switch S a The source of is connected to the voltage zero level reference GND, that is, the capacitor C1 and the auxiliary switch tube S a The resonant current detection sub-circuit 211 is connected in parallel with a conversion ratio coefficient of k ICS The current in the branch where the resonant current is located or the branch associated with the resonant current is converted into a voltage signal and output to the input end of the resonant current peak holding sub-circuit 212; the auxiliary switch tube S a It is used to construct a capacitor C1 voltage discharge circuit to achieve the capacitor C1 voltage reset function; the resonant current peak detection circuit 210 outputs a signal v ILrSamp That is, the voltage across the capacitor C1 in the resonant current peak holding sub-circuit 212; the voltage across the capacitor C1 v ILrSamp After the output voltage signal of the resonant current detection subcircuit 212 rises to the positive peak value, the peak hold function is realized due to the reverse cutoff of the diode D1; the capacitance value of the capacitor C1 can range from several pF to hundreds of μF, that is, the capacitance value has almost no effect on the peak hold result within a very wide range; the voltage across the capacitor v ILrSamp The end time of peak hold is the voltage across the capacitor v ILrSamp Greater than the negative slope signal v with slope compensation Ramp At this moment, that is, the analog comparator built into the microcontroller 220 outputs a high-level pulse signal, which controls the auxiliary switch tube to conduct to form a capacitor voltage discharge circuit to realize the capacitor voltage reset function; at the same time, the relationship between the auxiliary switch tube drive signal and the complementary switch tube drive signal of the switch bridge arm circuit 120 is: the auxiliary switch tube drive signal is logically the drive signal of the switch tube S1 of the switch bridge arm circuit 120 or the result of a non-logical operation.

[0064] In order to illustrate that the value of capacitor C1 has almost no effect on the peak hold result in a very wide range, 6 groups of different capacitor C1 values are set under the same sampling conditions and simulations are performed. The simulation results are shown in the figure below. Figure 3 As shown. Figure 3 It can be seen from the waveform of the resonant current peak detection result that the simulation results of the six working conditions in the peak hold stage are almost exactly the same, which proves that the capacitance value of capacitor C1 has almost no effect on the peak hold result within a very wide range.

[0065] In addition to the resonant current peak detection circuit 210 of the control unit 20 realizing the controlled object detection function and the drive circuit 230 power amplification function, the protection method is implemented by the microcontroller 220 software algorithm and the analog peripheral module built into the microcontroller. That is, the resonant converter output overload and short-circuit protection is realized on the basis of the fully digital implementation of the proposed resonant converter peak current control method. The key to the full digital implementation lies in the built-in analog comparator of the microcontroller 220.

[0066] A method for output overload and short-circuit protection of a resonant converter without output current detection is provided. When the resonant converter unit 10 does not have an output overload or short-circuit fault, the resonant converter unit 10 adopts a dual closed-loop control method in which an inner loop controller and an outer loop controller are nested based on a peak current control of the resonant current peak value. The specific steps are as follows:

[0067] Step 1: The outer loop controller is combined with the inner loop controller of the peak current control based on the peak value of the resonant current. The analog comparator COMP obtains the analog signal at the inverting input terminal, that is, the given reference signal of the inner loop controller is obtained;

[0068] Step 1.1: The outer loop controller 221 outputs the maximum value of the ramp i Lrpkref And input it to the ramp generator of the inner loop controller 222 built into the microcontroller 220;

[0069] Step 1.2: The ramp generator is set to the maximum value i Lrpkref Based on the slope compensation control algorithm, the negative slope signal v with slope compensation is obtained after the DAC digital-to-analog converter of the inner loop controller 222 is calculated. Ramp ;

[0070] Among them, the slope compensation control algorithm is: with slope compensation negative slope signal v Ramp is a piecewise function, at t=[(n - 1)T s / 2,nT s / 2], that is, in the first half of the switching cycle, set v Ramp is a constant value; at t=[nT s / 2,nTs ], that is, in the second half of the switching cycle, set v Ramp is a negative slope ramp signal with a constant digital slope value of λ; and establishes a control signal switching frequency f of the switching half-bridge switch tube of the switching bridge arm circuit 120 s The mathematical model between the outer loop controller and the inner loop controller of the peak current control based on the peak value of the resonant current is shown in FIG. 2 . The clock period of the microcontroller 220 is T Sysclk , and the slope compensation control algorithm sets the digital value of the unit clock cycle ramp down rate to V Slope , then the expression of the digital slope λ of the ramp signal is:

[0071]

[0072] Final switching frequency f s and the output i of the outer loop controller 221 Lrpkref The inner loop controller variable parameters of the peak current control based on the resonant current peak value include the microcontroller 220 clock period T Sysclk , Slope unit clock cycle ramp down rate value digital value V Slope And the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp The expression between them is:

[0073]

[0074] In formula (3), α is the ADC analog-to-digital conversion coefficient.

[0075] Step 1.3: Convert the negative slope signal v with slope compensation Ramp As the analog signal of the inverting input terminal of the analog comparator COMP.

[0076] Step 2: Obtain the current peak detection signal, the analog comparator COMP obtains the analog signal of the in-phase input terminal, that is, the feedback signal of the inner loop controller is obtained; the input terminal of the resonant current peak detection circuit 210 in step 2 is connected to the branch where the resonant current is located or the resonant current associated branch, and the current in the branch where the resonant current is located or the resonant current associated branch is converted by a proportional coefficient k ICS The resonant current detection sub-circuit 211 and the output v after the resonant current peak holding sub-circuit 212 realizes the peak holding function ILrSamp It is directly connected to the non-inverting input of the analog comparator COMP of the loop controller 222 in the microcontroller 220, and the resonant current peak detection signal v ILrSampFrom the detection of the current in the branch where the resonant current is located or the branch associated with the resonant current to the non-inverting input terminal of the analog comparator COMP of the loop controller 222 in the microcontroller 220, the entire process does not go through any delay or analog-to-digital conversion link.

[0077] Step 3: The analog comparator COMP compares the analog signal at the inverting input terminal with the analog signal at the non-inverting input terminal, and the EPWM module 223 performs a logic operation based on the comparison result and outputs a control signal.

[0078] Step 3.1: Connect the analog comparator COMP non-inverting input terminal v ILrSamp Signal and inverting input terminal v Ramp The signals are compared;

[0079] Step 3.2: When the non-inverting input of analog comparator COMP is ILrSamp The signal is greater than the inverting input v Ramp signal, the analog comparator COMP outputs a high-level pulse signal; when the analog comparator COMP's non-inverting input terminal v ILrSamp The signal is less than the inverting input v Ramp signal, the analog comparator COMP output is always a low-level signal; the EPWM module 223 only controls and processes when the analog comparator COMP outputs a high-level pulse signal, and the analog comparator COMP outputs a low-level signal without affecting the EPWM module 223;

[0080] Step 3.3: The EPWM module 223 performs control according to the high-level pulse signal output by the analog comparator COMP. The specific process can be divided into:

[0081] Step 3.3.1: The driving signal of the switch tube of the switch half-bridge structure in the switch bridge arm circuit 120 is named V Drive1 and V Drive2 , driving signal V Drive1 By V GS1 Control, drive signal V Drive2 By V GS2 Control, and V GS1 and V GS2 The EPWM module 223 adopts the up-counting mode, and the microcontroller 220 software algorithm sets the analog comparator COMP to output a high-level pulse signal as the interrupt source signal;

[0082] Step 3.3.2: When the analog comparator COMP outputs a high-level pulse signal, the software algorithm in the microcontroller 220 enters the interrupt link, and the EPWM module 223 outputs the control signal V GS1 Immediately switch from high level signal to low level signal; immediately capture the ramp signal value v at that moment after entering the interrupt subroutine Ramp, get the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp , combined with formula (1), the resonant current peak value can be obtained; then the ramp generator is reset immediately, v Ramp Restore to the initial value; then capture the time base counter value TBCTR of the EPWM module 223, multiply it by 2 and add a compensation value as the period register value TBPRD of the EPWM module 223; through TBPRD, the control signal switching frequency f of the switching half-bridge switch tube of the current switching bridge arm circuit 120 can be obtained s ; and the control signal V GS2 After the dead time delay set by the software algorithm, the low level signal is switched to a high level signal. This stage is the first half of the switching cycle described in step 1.2. At this time, v Ramp is a constant value;

[0083] Step 3.3.3: When the time base counter value TBCTR counts up to the period register value TBPRD, that is, TBCTR=TBPRD, the control signal V GS2 Immediately switch from high level signal to low level signal, the time base counter value TBCTR is reset to 0, and the ramp generator is set, v Ramp The digital slope value is constant at a negative slope of λ and it starts to decrease. This stage is the second half of the switching cycle described in step 1.2. At this time, v Ramp is a negative slope ramp signal with a constant digital slope value of λ, and the control signal V GS1 The low-level signal is switched to a high-level signal only after the dead-time delay set by the software algorithm;

[0084] Step 3.3.4: Analog comparator COMP inverting input v Ramp The signal decreases at a negative slope with a constant digital slope value of λ until it reaches the same phase input terminal v of the analog comparator COMP. ILrSamp When the signals are equal, the analog comparator COMP starts to output a high-level pulse signal, and the software algorithm in the microcontroller 220 enters the interrupt link. The subsequent process is consistent with steps 3.3.2 and 3.3.3, and the cycle is repeated;

[0085] Step 3.4: Finally, the EPWM module 223 outputs the control signal V GS1 and V GS2 After the driving circuit, the switching half-bridge switch tube of the switching bridge arm circuit 120 of the resonant converter unit 10 and the auxiliary switch tube S of the resonant current peak detection circuit 210 are a Control is performed to realize the resonant current peak control of the resonant converter unit 10, and the voltage v across the capacitor C1 of the resonant current detection sub-circuit 211 is ILrSampThe end time of peak hold is when the analog comparator outputs a high level pulse signal, and the auxiliary switch tube S a The driving signal is logically the switch control signal V of the switch bridge arm circuit 120 switching half-bridge structure. GS1 The result of a NOT logical operation.

[0086] A method for output overload and short-circuit protection of a resonant converter without output current detection. When an output overload or short-circuit fault occurs in the resonant converter unit 10, the resonant converter unit 10 implements output overload or short-circuit fault protection under a dual closed-loop control system consisting of an inner loop controller and an outer loop controller based on peak current control of the resonant current peak value. The specific steps are as follows:

[0087] Step 4: triggering the output overload and short circuit fault flags based on the resonant current peak value and output voltage detection signal;

[0088] Step 5: The output of the outer loop controller is limited to the maximum value i LrpkrefMax At the same time, the ramp parameter adaptive controller adjusts the ramp down rate value per unit clock cycle digital value V Slope_Adj Repeat step 3 to complete the switching frequency f s Regulation, suppressing the increase of primary and secondary current of the transformer due to output overload fault, which may damage the switch tube and diode, and completing the output overload protection function;

[0089] Step 5.1: After the output overload and short circuit fault flags are triggered, the output value of the outer loop controller is limited to the maximum value i LrpkrefMax , and capture the current moment of the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp and the control signal switching frequency f s_current ;

[0090] Step 5.2: Calculate the adjustment value V of the digital quantity of the ramp down rate value per unit clock cycle according to formula (3): Slope_Adj :

[0091]

[0092] Step 5.3: Set the ramp down rate per clock cycle to the digital value V Slope Updated to V Slope_Adj , the new ramp unit clock cycle ramp down rate value digital quantity V Slope_Adj Next, the switching frequency f s_New Update, that is:

[0093]

[0094] Step 5.4: Repeat steps 5.1-5.3 above to achieve adaptive control of ramp parameters.

[0095] Step 6: When the output overload and short-circuit fault flags determine that the resonant converter unit has a serious overload or even a short-circuit fault, the software is blocked after comparing the code with the preset short-circuit protection threshold. It can also be compared with the preset short-circuit protection threshold through other analog comparators built into the microcontroller unit to trigger the EPWM TZ (Trip-Zone) unit output protection action (such as shutting down or entering a safe state), completing hardware-level fast protection, and realizing dual software and hardware protection functions.

[0096] The inner loop controller and the outer loop controller of the peak current control based on the peak value of the resonant current are both implemented in the microcontroller 220 by the software control algorithm and its built-in peripherals, that is, the control method is fully digital. At the same time, the ramp function can be written in software code to replace the hardware ramp generator. By setting the maximum initial value V of the digital quantity of the ramp down rate value per unit clock cycle Slope_Ini and stable value V Slope , at startup V Slope_Ini Decreases to V Slope , which can realize the soft start function of the resonant converter.

[0097] Figure 4 and Figure 5 The circuit and control structure diagram of an embodiment of a resonant converter output overload and short circuit protection method without output current detection of the present invention and the key waveform diagram of the resonant converter of the embodiment operating under the condition that the switching frequency is equal to the resonant frequency are respectively shown. Figure 4 The invention of the output overload and short-circuit protection method for a resonant converter without output current detection is based on a peak current control method. The resonant converter is a half-bridge LLC resonant converter. This embodiment is described with the output voltage as the outer loop control object, with the purpose of stabilizing the output voltage v of the half-bridge LLC resonant converter. o , respectively, the three situations of the LLC resonant converter startup phase, no output overload or short circuit fault, and output overload or short circuit fault occur are explained.

[0098] (1) When the half-bridge LLC resonant converter starts, the outputs of fault flag 1 and fault flag 2 are both 0, that is, the control signal level of gate 2 is 0 at this time, then the output v of gate 2 Slope Follow the input signal V corresponding to the control level 0 Slope_start , that is, v Slope＝ V Slope_start The ramp generator starts to ramp down at the maximum ramp rate per clock cycle, which is the maximum initial value of the digital quantity V Slope_IniAt the moment of startup, the output value of the outer loop controller is limited to the maximum value i because the output voltage has not yet been established. LrpkrefMax At this time, the resonant tank current gradually increases from 0, corresponding to the peak detection signal v ILrSamp Small, the switching frequency f s_start is the maximum value, that is, soft start is achieved through the maximum switching frequency:

[0099]

[0100] In V Slope_start Decrease cycle by cycle to the steady-state set value V Slope After that, the ramp down rate value per clock cycle is kept at V Slope The corresponding starting frequency also drops from the maximum value to near the stable value, completing the soft start process.

[0101] (2) When the LLC resonant converter runs stably, the output voltage is stable, and there is no output overload or short circuit fault, the outputs of fault flag 1 and fault flag 2 are both 0, and the control signal level of gate 1 is 0, then the output i of gate 1 is Lrpkref Following the output of the PI controller, the control system only operates in the peak current mode control module. Output voltage v o With the output voltage given by v oref_ After making the difference, the difference is sent to the PI controller, and the output of the PI controller is used as the maximum value of the ramp i Lrpkref And input it to the ramp generator of the inner loop controller, the ramp generator is at the maximum value of the ramp i Lrpkref Based on the ramp unit clock cycle ramp down rate value digital steady-state setting value V Slope After passing through the DAC digital-to-analog converter of the inner loop controller, a negative slope signal v with slope compensation is obtained. Ramp As the analog signal at the inverting input of the analog comparator.

[0102] t o ~t1 stage: t o At this moment, the EPWM time base counter value TBCTR counts up to the EPWM period register value TBPRD, and the EPWM time base counter value TBCTR begins to reset to zero. GS2 From high level to low level, it enters the dead time, that is, the dead time is t1-t o , the switches S1 and S2 are turned off, and the auxiliary switch S a Keep conducting, build capacitor C1 discharge circuit to achieve capacitor C1 voltage reset. At the same time, the ramp generator starts running, and at the maximum value of the ramp i Lrpkref Based on the control algorithm, the slope down rate value per unit clock cycle is counted.

[0103] t1~t2 stage: at t1, the EPWM time base counter value TBCTR starts counting up from zero, V GS1 From low level to high level, switch tube S1 starts to conduct, switch tube S2 remains off, and auxiliary switch tube S a It starts to shut down, at which point the voltage on capacitor C1 increases and the ramp generator continues to decrease.

[0104] Phase t2 to t3: At t2, the current on the secondary side of the high-frequency transformer reaches its peak and then begins to decrease. Because the diode D1 is reverse-blocked and the capacitor C1 has no discharge circuit, the voltage v ILrSamp Maintain peak v ILrpkSamp .

[0105] t3~t4 stage: at t3, v ILrpkSamp Greater than v Ramp , the analog comparator outputs a high-level pulse signal to trigger the interrupt and enter the interrupt service code, read the EPWM time base counter value TBCTR and multiply it by 2 as the EPWM period register value TBPRD, and at the same time V GS1 From high level to low level, it enters the dead time, that is, the dead time is t4-t3, the switch tubes S1 and S2 are turned off, and the auxiliary switch tube S a Starts to conduct, capacitor C1 voltage v ILrSamp Rapidly drops to 0, and the ramp generator is reset to the maximum value of the ramp i Lrpkref .

[0106] t4~t5 stage: at t4, V GS2 From low level to high level, the switch tube S2 starts to conduct, while the switch tube S1 is turned off, and the auxiliary switch tube S a Keep conducting, capacitor C1 voltage v ILrSamp Keep it at 0.

[0107] t5~t6 stage: with t o The circuit operation mode after t6 is consistent with that during the period from t1 to t6, and will not be described in detail.

[0108] (3) When the LLC resonant converter has an output overload, the output of fault flag 1 is 1 and the output of fault flag 2 is 0. The control signal levels of gate 1 and gate 2 are both 1. Then the output i of gate 1 is Lrpkref The corresponding input signal i when the follow control level is 1 LrpkrefMax , and the output of gate 2 v Slope The corresponding input signal V when the follower control level is 1 Slope_Adj , which is the output result of the parameter adaptive controller. V Slope_AdjCalculated by formula (4), combined with formula (5), the frequency conversion control is used to suppress overcurrent faults and realize the output overcurrent protection function of the LLC resonant converter.

[0109] When the LLC resonant converter encounters extreme conditions such as severe output overload or short circuit, the outputs of fault flag 1 and fault flag 2 are both 1, triggering the EPWM TZ (Trip-Zone) unit output protection action (wave blocking protection, that is, all drive signals are pulled down to a low level), completing hardware-level rapid protection. At the same time, the wave blocking can also be completed by judging the fault through software code, realizing dual software and hardware protection functions.

[0110] Furthermore, in order to fully demonstrate the changes in key voltage and current at different stages of the embodiment of the output overload and short-circuit protection method of a resonant converter without output current detection of the present invention, Figure 6 The following are key waveform diagrams of an LLC resonant converter operating in the startup phase, in the absence of an output overload or short-circuit fault, and in the presence of an output overload or short-circuit fault, according to an embodiment of a method for output overload and short-circuit protection of a resonant converter without output current detection according to the present invention:

[0111] t o ~t1 stage: This stage is the soft start stage. In this stage, fault flag 1 and fault flag 2 are always low level, t o At this moment, the LLC resonant converter starts to start. Under the soft start scheme proposed by the present invention, the positive and negative peak values of the resonant current (+i Lrpk and -i Lrpk ) and the rectified current (i D1pk and i D2pk ) does not exceed the corresponding maximum value i Lrpk_Max and i Dpk_Max The whole startup process is completed at time t1, achieving a good startup effect.

[0112] Phase t1 to t4: This phase is when no output overload or short-circuit faults occur. During this phase, Fault Flag 1 and Fault Flag 2 remain low. After stabilizing at t1 and continuing until t2, the LLC resonant converter operates at full load, with stable output voltage and current. At t2, the LLC resonant converter steps from full load to half load, and after a very short time, the converter remains stable with minimal overshoot. At t3, the LLC resonant converter steps from half load to full load, and after a very short time, the converter remains stable with minimal overshoot. The LLC resonant converter's load step disturbance performance from t1 to t4 demonstrates the superior control performance achieved through peak current control.

[0113] Phase t4 to t9: This phase is when output overload or short circuit occurs. This phase is subdivided into three situations: slight overload, general overload, and severe overload or short circuit. Among them: in phase t4 to t5, there is slight output overload. The converter controls the output voltage to remain constant through its own control, and the current increases slightly. In phase t5 to t7, there is general overload. At this time, fault flag 1 changes from low level to high level, while fault flag 2 remains low level, indicating that the system has a general output overload. At this time, the parameter adaptive controller adjusts the ramp unit clock cycle ramp down rate value digital quantity to V Slope_Adj , suppressing the sharp increase in resonant current and rectifier current caused by general overload. Only a small resonant current and rectifier current spike appears at the moment of fault occurrence, effectively protecting the switching devices of the LLC resonant converter from damage due to output overload. During the t7-t8 stage, there is a severe overload or short circuit. At this time, Fault Flag 2 changes from low level to high level, that is, Fault Flag 1 and Fault Flag 2 are both high, indicating that the system has a severe output overload or short circuit. At this time, the wave blocking protection is triggered and the LLC resonant converter stops working. In this professional field, severe overload or short circuit is one of the most serious circuit faults, and the converter is not allowed to start automatically. During the t8-t9 stage, the converter is simulated and cannot start automatically after the wave blocking protection is completed due to severe overload or short circuit. At time t8, the output load returns to the full load condition, but the converter still remains in a no-output state, that is, the converter cannot start automatically.

[0114] In order to verify the embodiment of the output overload and short circuit protection method of a resonant converter without output current detection of the present invention Figure 4 and Figure 5 The effectiveness of the program and Figure 6 To verify the accuracy of the theoretical waveform, the LLC resonant converter is simulated through circuit simulation in three conditions: the startup phase, no output overload or short circuit fault, and output overload or short circuit fault. The simulation result waveform is shown in the figure below. Figure 7 shown.

[0115] It can be seen intuitively and clearly that Figure 7 Simulation results and Figure 6 Therefore, it is verified that the LLC resonant converter based on the output overload and short-circuit protection method of the resonant converter without output current detection of the present invention has superior control performance and good protection effect.

[0116] The embodiments described above are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should fall within the scope of protection determined by the claims of the present invention.

Claims

1. A resonant converter output overload and short-circuit protection system without output current detection, characterized in that: The invention comprises a resonant converter unit (10) and a control unit (20), wherein the resonant converter unit (10) comprises a DC input circuit (110), a switch bridge arm circuit (120), a resonant cavity and high-frequency transformer circuit (130), and a rectifier filter circuit (140) connected in series in sequence; the control unit (20) comprises a resonant current peak detection circuit (210) for realizing a controlled object detection function, a microcontroller (220) for controlling the peak current, and a drive circuit (230) for a power amplification function, which are connected in series in sequence, wherein the resonant current peak detection circuit (210) ) comprises a resonant current detection subcircuit (211) and a resonant current peak holding subcircuit (212) connected in sequence, the microcontroller (220) comprises an outer loop controller (221), an inner loop controller (222), an EPWM module (223) and a parameter adaptive control protection unit (224) at the control logic level, the inner loop controller (222) comprises a ramp generator, a DAC digital-to-analog converter and an analog comparator COMP connected in series in sequence, and the parameter adaptive control protection unit (224) comprises an output overload and short circuit fault flag and a ramp parameter adaptive controller.

2. The resonant converter output overload and short-circuit protection system without output current detection according to claim 1, characterized in that: The resonant current detection subcircuit (211) is an isolated current peak detection circuit based on a current transformer or a Hall sensor; The resonant current peak holding subcircuit (212) includes a diode D1, a capacitor C1 and an auxiliary switch tube S a The anode of the diode D1 of the resonant current peak holding subcircuit (212) is connected to the output end of the resonant current detection subcircuit (211); the cathode of the diode D1 of the resonant current peak holding subcircuit (212) is connected to the positive electrode of the capacitor C1 and the auxiliary switch tube S a The drain of capacitor C1 is connected to the negative electrode of auxiliary switch S a The source of is connected to the voltage zero level reference GND, that is, the capacitor C1 and the auxiliary switch tube S a Parallel connection; The resonant current detection subcircuit (211) uses a conversion ratio coefficient k ICS The current in the branch where the resonant current is located or the branch associated with the resonant current is converted into a voltage signal and output to the input end of the resonant current peak holding sub-circuit (212); the auxiliary switch tube S a It is used to construct a capacitor C1 voltage discharge circuit to realize the capacitor C1 voltage reset function; the resonant current peak detection circuit (210) outputs a signal v ILrSamp That is, the voltage across the capacitor C1 in the resonant current peak holding subcircuit (212); the voltage across the capacitor C1 v ILrSamp After the output voltage signal of the resonant current detection subcircuit (211) rises to a positive peak value, the diode D1 is reversely cut off to achieve a peak holding function; the capacitance value of the capacitor C1 ranges from several pF to hundreds of μF, that is, the capacitance value has no effect on the peak holding result within an extremely wide range; the resonant current peak detection circuit (210) outputs a signal v ILrSamp and the resonant current i Lr The expression is:

3. The resonant converter output overload and short-circuit protection system without output current detection according to claim 1, characterized in that: The switching bridge arm circuit (120) in the resonant converter unit (10) includes at least one switching half-bridge structure; the resonant cavity and high-frequency transformer circuit (130) includes at least one inductor, a capacitor and a transformer, and the inductor, capacitor and transformer are interconnected.

4. A method for output overload and short-circuit protection of a resonant converter without output current detection, implemented based on the resonant converter output overload and short-circuit protection system according to any one of claims 1 to 3, characterized in that: When the resonant converter unit (10) does not have an output overload or short circuit fault, the resonant converter unit (10) adopts a double closed-loop control in which an inner loop controller based on a peak current control of a resonant current peak value and an outer loop controller are nested. The specific steps are as follows: Step 1: The outer loop controller is combined with the inner loop controller of the peak current control based on the peak value of the resonant current. The analog comparator COMP obtains the analog signal at the inverting input terminal, that is, the given reference signal of the inner loop controller is obtained; Step 2: Obtain the current peak detection signal, and the analog comparator COMP obtains the analog signal at the non-inverting input terminal, that is, the feedback signal of the inner loop controller; Step 3: The analog comparator COMP compares the analog signal of the inverting input terminal with the analog signal of the non-inverting input terminal, and the EPWM module (223) performs a logic operation according to the comparison result and outputs a control signal. When an output overload or short circuit fault occurs in the resonant converter unit (10), the specific steps of implementing output overload or short circuit fault protection of the resonant converter unit (10) under dual closed-loop control of an inner loop controller based on peak current control of the resonant current peak value and an outer loop controller are as follows: Step 4: triggering the output overload and short circuit fault flags based on the resonant current peak value and output voltage detection signal; Step 5: The output of the outer loop controller is limited to the maximum value i LrpkrefMax At the same time, the ramp parameter adaptive controller adjusts the ramp down rate value per unit clock cycle digital value V Slope_Adj Repeat step 3 to complete the switching frequency f s Regulation, suppressing the increase of primary and secondary current of the transformer due to output overload fault, which may damage the switch tube and diode, and completing the output overload protection function; Step 6: When the output overload and short-circuit fault flags determine that the resonant converter unit (10) has a serious overload or even a short-circuit fault, the software is blocked after comparing the code with the preset short-circuit protection threshold. Alternatively, the TZ (Trip-Zone) unit output protection action of the EPWM can be triggered by comparing the code with the preset short-circuit protection threshold through other analog comparators built into the microcontroller unit, thereby completing hardware-level fast protection and realizing dual software and hardware protection functions.

5. The method for output overload and short-circuit protection of a resonant converter without output current detection according to claim 4, wherein: Step 1 The specific steps are as follows: Step 1.1: The outer loop controller (221) outputs the maximum value of the ramp i Lrpkref and inputting it into the ramp generator of the inner loop controller (222) built into the microcontroller (220); Step 1.2: The ramp generator is set to the maximum value i Lrpkref Based on the slope compensation control algorithm, the negative slope signal v with slope compensation is obtained after the DAC digital-to-analog converter of the inner loop controller (222) is calculated. Ramp ; Among them, the slope compensation control algorithm is: with slope compensation negative slope signal v Ramp is a piecewise function, at t=[(n - 1)T s / 2,nT s / 2], that is, in the first half of the switching cycle, set v Ramp is a constant value; at t=[nT s / 2,nT s ], that is, in the second half of the switching cycle, set v Ramp is a negative slope ramp signal with a constant digital slope value of λ; and a control signal switching frequency f of the switching half-bridge switch tube of the switching bridge arm circuit (120) is established. s The mathematical model between the outer loop controller and the inner loop controller of the peak current control based on the peak value of the resonant current, the clock period of the microcontroller (220) is T Sysclk , and the slope compensation control algorithm sets the digital value of the unit clock cycle ramp down rate to V Slope , then the expression of the digital slope λ of the ramp signal is: Final switching frequency f s and the output i of the outer loop controller (221) Lrpkref , the inner loop controller variable parameters of the peak current control based on the resonant current peak value include the microcontroller (220) clock period T Sysclk , Slope unit clock cycle ramp down rate value digital value V Slope And the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp The expression between them is: In formula (3), α is the ADC analog-to-digital conversion coefficient. Step 1.3: Convert the negative slope signal v with slope compensation Ramp As the analog signal of the inverting input terminal of the analog comparator COMP.

6. The method for output overload and short-circuit protection of a resonant converter without output current detection according to claim 4, characterized in that: In step 2, the input end of the resonance current peak detection circuit (210) is connected to the branch where the resonance current is located or the resonance current associated branch, and the current in the branch where the resonance current is located or the resonance current associated branch is converted by a proportional coefficient k. ICS The resonant current detection subcircuit (211) and the output v after the resonant current peak holding subcircuit (212) realizes the peak holding function ILrSamp It is directly connected to the non-inverting input terminal of the analog comparator COMP of the loop controller (222) in the microcontroller (220), and the resonant current peak detection signal v ILrSamp From the detection of the current in the branch where the resonant current is located or the branch associated with the resonant current to the in-phase input terminal of the analog comparator COMP of the inner loop controller (222) of the microcontroller (220), the entire process does not go through any delay or analog-to-digital conversion link.

7. The method for output overload and short-circuit protection of a resonant converter without output current detection according to claim 4, wherein: Step 3: Step 3.1: Connect the analog comparator COMP non-inverting input terminal v ILrSamp Signal and inverting input terminal v Ramp The signals are compared; Step 3.2: When the non-inverting input of analog comparator COMP is ILrSamp The signal is greater than the inverting input v Ramp signal, the analog comparator COMP outputs a high-level pulse signal; when the analog comparator COMP's non-inverting input terminal v ILrSamp The signal is less than the inverting input v Ramp signal, the analog comparator COMP output is always a low-level signal; the EPWM module (223) only performs control processing when the analog comparator COMP outputs a high-level pulse signal, and the analog comparator COMP outputs a low-level signal without affecting the EPWM module (223); Step 3.3: The EPWM module (223) performs control according to the high-level pulse signal output by the analog comparator COMP. The specific process can be divided into: Step 3.3.1: The driving signal of the switch tube of the switch half-bridge structure in the switch bridge arm circuit (120) is named V Drive1 and V Drive2 , driving signal V Drive1 By V Gs1 Control, drive signal V Drive2 By V GS2 Control, and V Gs1 and V Gs2 is a complementary relationship, that is, V Drive1 and V Drive2 There is a complementary relationship between them; the EPWM module (223) adopts an upward counting mode, and the microcontroller (220) software algorithm sets the analog comparator COMP to output a high-level pulse signal as an interrupt source signal; Step 3.3.2: When the analog comparator COMP outputs a high-level pulse signal, the software algorithm in the microcontroller (220) enters the interrupt link, and the EPWM module (223) outputs a control signal V Gs1 Immediately switch from high level signal to low level signal; immediately capture the ramp signal value v at that moment after entering the interrupt subroutine Ramp , get the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp , combined with formula (1), the resonant current peak value can be obtained; then the ramp generator is reset immediately, v Ramp Restore to the initial value; then capture the time base counter value TBCTR of the EPWM module (223), multiply it by 2 and add a compensation value to it as the period register value TBPRD of the EPWM module (223); through TBPRD, the control signal switching frequency f of the switching half-bridge switch tube of the current switching bridge arm circuit (120) can be obtained. s ; and the control signal V Gs2 After the dead time delay set by the software algorithm, the low level signal is switched to a high level signal. This stage is the first half of the switching cycle described in step 1.

2. At this time, v Ramp is a constant value; Step 3.3.3: When the time base counter value TBCTR counts up to the period register value TBPRD, that is, TBCTR=TBPRD, the control signal V Gs2 Immediately switch from high level signal to low level signal, the time base counter value TBCTR is reset to 0, and the ramp generator is set, v Ramp The digital slope value is constant at a negative slope of λ and it starts to decrease. This stage is the second half of the switching cycle described in step 1.

2. At this time, v Ramp is a negative slope ramp signal with a constant digital slope value of λ, and the control signal V Gs1 The low-level signal is switched to a high-level signal only after the dead-time delay set by the software algorithm; Step 3.3.4: Analog comparator COMP inverting input v Ramp The signal decreases at a negative slope with a constant digital slope value of λ until it reaches the same phase input terminal v of the analog comparator COMP. ILrSamp When the signals are equal, the analog comparator COMP starts to output a high-level pulse signal, and the software algorithm in the microcontroller (220) enters the interrupt link. The subsequent process is consistent with steps 3.3.2 and 3.3.3, and the cycle is repeated; Step 3.4: Finally, the EPWM module (223) outputs the control signal V Gs1 and V Gs2 After the drive circuit, the switching half-bridge switch tube of the switching bridge arm circuit (120) of the resonant converter unit (10) and the auxiliary switch tube S of the resonant current peak detection circuit (210) are a Control is performed to achieve the resonant current peak control of the resonant converter unit (10), and the voltage v across the capacitor C1 of the resonant current detection subcircuit (211) is ILrSamp The end time of peak hold is when the analog comparator outputs a high level pulse signal, and the auxiliary switch tube S a The driving signal is logically the switch tube control signal V of the switch bridge arm circuit (120) switch half-bridge structure. Gs1 The result of a NOT logical operation.

8. The method for output overload and short-circuit protection of a resonant converter without output current detection according to claim 4, wherein: Step 5: The specific steps are as follows: Step 5.1: After the output overload and short circuit fault flags are triggered, the output value of the outer loop controller is limited to the maximum value i LrpkrefMax , and capture the current moment of the resonant current peak detection signal v ILrSamp The peak value v ILrpkSamp and the control signal switching frequency f s_current ; Step 5.2: Calculate the adjustment value V of the digital quantity of the ramp down rate value per unit clock cycle according to formula (3): Slope_Adj : Step 5.3: Set the ramp down rate per clock cycle to the digital value V Slope Updated to V Slope_Adj , the new ramp unit clock cycle ramp down rate value digital quantity V Slope_Adj Next, the switching frequency f s_New Update, that is: Step 5.4: Repeat steps 5.1-5.3 above to achieve adaptive control of ramp parameters.

9. A method for output overload and short-circuit protection of a resonant converter without output current detection according to any one of claims 4 to 8, characterized in that: The inner loop controller and the outer loop controller of the peak current control based on the resonant current peak are both implemented in the microcontroller (220) by the software control algorithm and its built-in peripherals, that is, a fully digital control method; at the same time, a ramp function can be written by software code to replace the hardware ramp generator.

10. The method for output overload and short-circuit protection of a resonant converter without output current detection according to claim 9, characterized in that: By setting the ramp down rate per clock cycle, the maximum initial value of the digital quantity V Slope_Ini and stable value V Slope , at startup V Slope_Ini Decreases to V Slope , which can realize the soft start function of the resonant converter.

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