Ultra-wideband ultra-low power consumption millimeter wave quadrupler

Abstract

The invention discloses an ultra-wideband ultra-low power consumption millimeter wave injection locking quadrupler, which realizes frequency multiplication bandwidth exceeding 100 GHz, 3 dB working bandwidth exceeding 10 GHz, 10 mW total power consumption and 1t under millimeter wave frequency through innovative resonant cavity design, adaptive bias and output equalization technology. And the output power fluctuation of 0.1 dB is obviously superior to that of other existing schemes, and the millimeter-wave radar antenna is suitable for a 76-81 GHz high-performance millimeter-wave radar system.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave integrated circuit technology, and more particularly to an ultra-wideband, ultra-low-power quadrupler circuit based on injection locking technology. This circuit offers stable output signal power, a very wide locking bandwidth, no additional phase noise, and consumes only one-quarter the power of a conventional millimeter-wave quadrupler. Background Art

[0002] In the millimeter wave band, traditional frequency multipliers have several technical problems, such as: (1) limited bandwidth, unable to achieve stable frequency multiplication in the entire frequency band of 76 to 81 GHz, and there is a risk of loss of lock; (2) extremely high power consumption: the harmonic signals generated by traditional push-pull or passive frequency multipliers are very weak and must be compensated by high-gain buffers. Their total power consumption is generally higher than 40 mW, which limits the scope of application; (3) phase noise deterioration: two doublers are cascaded to form a quadruple frequency. Due to the large signal attenuation, the buffer introduces distortion and noise, and the overall phase noise cumulative deterioration often exceeds 12 dB, affecting the receiver sensitivity; (4) large output power fluctuations: the power fluctuation within the band exceeds 3 dB, resulting in unstable system signal-to-noise ratio and poor consistency of each channel, affecting the radar beamforming performance and antenna directivity. Summary of the Invention

[0003] To address the aforementioned issues in the prior art, the present invention provides an ultra-wideband, ultra-low-power quadrupler. This quadrupler is constructed by cascading two doublers, each of which can switch between a passive push-pull structure and an active injection-locked frequency doubler (ILFD) structure.

[0004] The ultra-wideband, ultra-low-power quadrupler can adaptively switch operating states based on the input signal. When both stages of the doubler are active ILFD, the quadrupler output power reaches its maximum, eliminating the need for an external buffer. When both stages are passive push-pull structures, the quadrupler's operating bandwidth reaches its maximum, supporting operating frequencies from a few kHz to 100 GHz, making it suitable for millimeter-wave applications.

[0005] The ultra-wideband ultra-low power consumption quadrupler can be flexibly configured, and the two-stage doubler can be selected to be in active or passive mode to achieve a balance between operating bandwidth and output power.

[0006] In any stage of the ultra-wideband ultra-low power quadrupler, the ILFD also adopts a push-pull cross-coupled oscillator structure, which forms a complementary effect with the passive push-pull frequency doubling structure. Through the synergistic effect of the nonlinear coupling of the resonant cavity and the harmonic components of the injected signal, the frequency doubling efficiency is greatly improved.

[0007] In any one-stage frequency doubler, the passive push-pull module and the active injection-locked core share the same LC frequency-selective network, multiplexing dynamic currents and seamlessly coupling the two frequency-doubling modules to form a mutually pulling positive feedback structure, saving area and eliminating the need for DC blocking and bias circuit modules.

[0008] For any level of ILFD, its bias point can be configured so that it does not oscillate but provides gain for the passive push-pull module, greatly reducing its insertion loss.

[0009] By adjusting the Q value of the frequency-selective network resonator and optimizing the coupling coefficient between the two stages, the ultra-wideband, ultra-low-power quadrupler can stably output signals within a bandwidth of 10 GHz with an amplitude fluctuation of approximately 0.1 dB.

[0010] When the input end is a voltage-controlled oscillator, the resonant frequency selection network of this ultra-wideband and ultra-low-power quadrupler can be linked with it. That is, the self-oscillation frequency of the quadrupler increases or decreases synchronously with the input signal, ensuring that the two ILFDs of the quadrupler are always at the center of the locking bandwidth. Its output signal power is maximized, the swing is constant, and the phase noise is optimized.

[0011] The ultra-wideband, ultra-low-power quadrupler utilizes an adaptive bias circuit to eliminate the effects of temperature and power supply voltage fluctuations, achieving highly stable output within the 76 to 81 GHz millimeter wave band. Used as a local oscillator (LO) signal, it provides high consistency across transceiver channels, ensuring radar frequency sweep accuracy.

[0012] Because the output noise of the two-stage ILFD is incoherent, the final broadband noise of the quadrupler is determined only by the last stage, and thermal noise is not accumulated, so the overall phase noise is improved by 3 to 6 dB compared with the traditional solution.

[0013] The use of subthreshold bias and dynamic current multiplexing technology reduces the overall power consumption of the quadrupler to 10 mW (only 25% of similar circuits). An integrated adaptive amplitude equalization network ensures output power fluctuations of less than 1 dB across the entire frequency band. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the ultra-wideband ultra-low power quadruple frequency multiplier of the present invention.

[0015] Figure 2 This is a schematic diagram of the wide locking range resonant cavity design of the present invention, including synchronous frequency tuning and current multiplexing modules.

[0016] Figure 3 This is the CMOS ultra-wideband low-power millimeter-wave quadrupler in Example 1 of the present invention.

[0017] Figure 4This is a schematic diagram of the output power shaping effect of a three-stage injection-locked oscillator buffer.

[0018] Figure 5 Schematic diagram of the phase noise simulation results of the quadrupler of the present invention.

[0019] Figure 6 It is a schematic diagram comparing the input signal and the output signal of the quadrupler of the present invention.

[0020] Figure 7 This is a simulation diagram of the amplitude curve of a traditional quadruple frequency signal (the amplitude fluctuation of the traditional quadruple frequency signal in the 77.68 to 82.06 GHz band is greater than 5 dB. Because the passive frequency multiplier gain is negative, the amplitude of the quadruple frequency signal is less than 150 mV).

[0021] Figure 8 This is a schematic diagram of the simulation of the amplitude curve of the quadruple frequency signal of the present invention (the amplitude fluctuation of the quadruple frequency signal of the present invention in the 77.68 to 82.06 GHz band is less than 0.1 dB, and the amplitude is 1.2 V (600 mV single peak value)). DETAILED DESCRIPTION

[0022] The following describes a specific embodiment of the ultra-wideband, ultra-low power quadrupler of the present invention to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiment. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0023] Example 1 (SMIC 40nm CMOS process).

[0024] The core circuit of the quadruple frequency multiplier of Example 1 is composed of two stages of cascaded doublers.

[0025] Transistors M1 to M8 of the quadrupler form the first-stage frequency doubler. When control voltage EN_ILFD1 = 0, it operates in low-power push-pull mode with an operating bandwidth from DC to over 100 GHz. When EN_ILFD1 = 1, it operates in injection-locked oscillator mode, outputting a high-power doubled frequency signal with a 3-dB bandwidth greater than 5 GHz.

[0026] Furthermore, transistors M9 to M16 of the quadrupler constitute a second-stage frequency doubler: when the control voltage EN_ILFD2 = 0, it operates in a low-power push-pull mode with an operating bandwidth of near DC to above 100 GHz; when EN_ILFD2 = 1, it operates in an injection-locked oscillator mode, outputting a high-power doubled frequency signal (the overall frequency is quadrupled), with a 3-dB bandwidth greater than 10 GHz.

[0027] Furthermore, the control voltages of the two-stage doubler can be freely combined. That is, by freely selecting EN_ILFD1 and EN_ILFD2 to "0" or "1," the quadrupler can operate in four modes. "11" is the high-performance mode, in which both stages operate in an injection-locked oscillation state, maximizing output signal power. This mode can provide a 0 dBm millimeter-wave signal without an external buffer or added gain, while consuming only one-quarter the DC power of a traditional quadrupler-buffer combination. This mode is suitable for scenarios with extremely high performance requirements, such as automotive millimeter-wave radar.

[0028] Furthermore, "00" is a low-power mode. In this mode, M1, M4, M9, and M12 are turned off, while the remaining transistors are biased in the subthreshold region. The overall power consumption is one-quarter that of "11" mode. It can provide a -15 dBm signal without an external buffer or added gain, supporting the full frequency band from near DC to over 100 GHz, with a 3-dB bandwidth exceeding 10 GHz. This mode is suitable for scenarios requiring low power consumption, such as portable millimeter-wave radar.

[0029] Furthermore, the "01" and "10" modes are both balanced modes, with output power between -15 and 0dBm and moderate power consumption, which are suitable for low-power scenarios with certain performance requirements, such as consumer-grade and industrial-grade millimeter-wave radars.

[0030] Furthermore, TF2 is used between the first-stage frequency multiplier and the second-stage frequency multiplier for frequency modulation and impedance matching. Similarly, TF3 is used between the second-stage frequency multiplier and the output buffer for frequency modulation and impedance matching. TF2 and TF3 form resonant cavities with CV2 and CV3, respectively, and are tuned to the second and fourth harmonics frequencies, respectively.

[0031] The resonant cavities of the first-stage frequency multiplier and the second-stage frequency multiplier are jointly designed with the VCO resonator at the input end. By selecting the size ratio of the three varactor diodes, the three self-resonant frequencies are linked in proportion. That is, the varactor diodes of the three modules are controlled by the same frequency modulation voltage, increase or decrease synchronously, and are located at the center of the resonant cavity at the same time.

[0032] According to injection locking theory, the Adler equation shows that, under the above operation, the amplitude of the VCO output signal after passing through the two-stage doubler varies with frequency modulation, determined solely by the Q value of the resonant cavity. For example, when the radar chirp sweep frequency range is 76 to 81 GHz, the output power fluctuation of a conventional injection-locked doubler is often greater than 6 dB, while this technique achieves less than 1 dB. Manually lowering the Q value can further reduce this fluctuation.

[0033] The ultra-wideband, ultra-low-power quadrupler utilizes an adaptive bias circuit to eliminate the effects of temperature and power supply voltage on bias current. The output of the ultra-wideband, ultra-low-power quadrupler can be buffered by adding multiple injection-locked oscillators. By cleverly selecting the frequency difference between their resonant cavities, the output power of the preceding stage can be further compensated for within-band fluctuations in the output power of the preceding stage. For example, if the Q value of the second-stage resonant cavity of the quadrupler is centered at 4f0 and its Q value is too large, the output power at the center frequency of 78.5 GHz within the millimeter-wave bandwidth of 76 to 81 GHz will be maximum, while signals at the edges of the wideband, such as 81 GHz, will be less powerful. Selecting an 81 GHz oscillation frequency for the output ILO buffer will produce a "peak clipping" effect on the 78.5 GHz signal, flattening the signal power across the entire frequency band. For even flatter output power, multiple injection-locked oscillators can be cascaded as buffers, with their self-resonant frequencies evenly distributed across the bandwidth. This ensures that the quadrupler's output power remains virtually constant with frequency, remaining less than 0.1 dB within a bandwidth of at least 10 GHz.

Claims

1. An ultra-wideband, ultra-low power consumption millimeter-wave quadrupler, characterized by: It includes a frequency multiplication module (1) that can select between passive push-pull and active injection locked oscillation modes, a wide frequency multiplication module (2) with linked tuning, an adaptive bias circuit (3), and an output amplitude equalization module (4); The frequency multiplication module (1) can be selected between passive push-pull and active injection-locked oscillation modes, wherein the active module also adopts a push-pull oscillator structure and shares a tunable LC resonant cavity with the passive module; The linked tuned wide frequency multiplication module (2) can ensure that the output power of the quadruple frequency multiplier is stable within a frequency modulation range of at least 10 GHz, and the phase noise reaches a theoretical optimal value, that is, the frequency multiplier itself does not increase additional phase noise; The adaptive bias circuit (3) includes an adaptively regulated current source, a tunable subthreshold bias technology, and a bias module for adjusting the negative impedance value of the injection-locked oscillator; The output amplitude equalization module (4) includes a cascaded injection-locked buffer, which suppresses the fluctuation of the output power in the frequency band by staggering its natural frequency, and can achieve power fluctuation of less than 0.1 dB in the 10 GHz frequency band.

2. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 1, characterized in that: The tunable LC resonant cavity is jointly designed, and its resonant frequency is tuned in conjunction with an input voltage-controlled oscillator (VCO) through a varactor diode, ensuring that the injection-locked frequency multiplier operates at an optimal resonant point within the entire frequency band.

3. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 1, characterized in that: The quadrupler is composed of two stages of switchable doubler frequency units in cascade, and each stage of doubler frequency units includes: a passive push-pull frequency multiplication structure; an active injection-locked oscillator frequency multiplication structure; the passive and active structures share the same LC frequency selection network, reuse dynamic current, and form a mutually pulling positive feedback coupling.

4. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 3, characterized in that: Each double frequency unit switches its working mode independently through control signals (EN_ILFD1 and EN_ILFD2): Mode 1 (EN_ILFD1=1, EN_ILFD2=1): Active injection-locked frequency multiplication structure is enabled in both stages, and the output signal power is maximized. Mode 2 (EN_ILFD1=0, EN_ILFD2=0): Both stages use the passive push-pull structure, the transistors are biased in the subthreshold region, the multiplication bandwidth is maximized, and the power consumption is minimized; Mode 3 (EN_ILFD1=1, EN_ILFD2=0): The first stage uses an active injection-locked frequency multiplication structure, and the second stage uses a passive push-pull structure, which has a wide output bandwidth and a trade-off between power consumption and output power. Mode 2 (EN_ILFD1=0, EN_ILFD2=1): The first stage uses a passive push-pull structure, and the second stage uses an active injection-locked frequency doubling structure. The output power is high, and power consumption and output power are compromised.

5. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 1, characterized in that: The adaptive bias circuit dynamically adjusts the tail current through a temperature compensation circuit, so that the overall power consumption is ≤10 mW, and the output power is adjustable in the range of -15 dBm to 0 dBm.

6. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 3, characterized in that: The active injection-locked frequency multiplication structure provides gain compensation for the passive push-pull module and reduces insertion loss when the oscillation function is turned off at the bias point.

7. The ultra-wideband, ultra-low power consumption millimeter wave quadrupler according to claim 1, characterized in that: The output amplitude equalization module is cascaded with at least one stage of injection-locked oscillator buffer, and the natural frequency of each buffer is evenly distributed in the 76-81 GHz frequency band, and power fluctuation compensation is achieved through the resonant frequency difference.

8. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 1, characterized in that: The noise between the two-stage doubler units is incoherently superimposed, and the overall phase noise is determined by the last stage, which is 3-6 dB better than the traditional cascade structure.

9. The ultra-wideband, ultra-low power consumption millimeter-wave quadrupler according to claim 1, characterized in that: The quadrupler embodiment is a single CMOS chip, implemented using a 40 nm or higher process technology. This invention is universally applicable to any other process technology, including but not limited to BJT, SiGe, SiC, GaAs, BiCMOS, DMOS, BCD, borophene, and graphene.

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