Motor filtering speed measurement method based on FPGA

Abstract

The invention relates to a motor filtering speed measurement method based on an FPGA, and belongs to the technical field of motor speed measurement. The filtering speed measurement method comprises the following steps: detecting rotation of a motor through a Hall encoder and outputting a pulse signal, outputting the pulse signal to a digital quantity input interface of an FPGA (Field Programmable Gate Array), and realizing a filtering speed measurement algorithm in the FPGA in a hardware form; and performing data operation processing on the pulse signal by using an FPGA based on a filtering speed measurement algorithm to realize measurement of the rotating speed of the motor. Compared with a speed measurement method in the prior art, the method has the advantages that the FPGA is combined with a filtering speed measurement algorithm, so that the rotation speed of the motor can be measured, the problem of low speed measurement precision of the motor in an unstable state can be effectively solved, the anti-interference capability of motor speed measurement can be improved, and the response speed of a speed measurement system can be increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of motor speed measurement, and in particular relates to a motor speed measurement method based on FPGA. Background Art

[0002] Motor speed, as a key physical quantity for all types of motors, often plays a crucial role as a feedback variable in control systems. Therefore, for closed-loop motor speed control systems, the closer the measured speed is to the true value, the better the control system performance. Currently, encoder speed measurement is the most commonly used motor speed measurement system. However, due to the operating environment and the mechanical motion of the motor itself, motors often generate mechanical vibration and high-frequency noise during operation. These vibrations and noise significantly interfere with the accurate speed signal output by the motor encoder, resulting in a significant discrepancy between the measured speed and the actual speed.

[0003] In the patent document "202311836318.9 A servo motor encoder speed measurement device and method based on a microcontroller", this method uses a microcontroller to receive encoder pulse signals, and adjusts the encoder pulse signals based on the parameter adaptive adjustment method of the Lyapunov function. The speed value of the motor is calculated according to the adjusted pulse signal, which can ensure relatively accurate motor speed measurement. However, for multi-channel high-speed and filtering algorithm implementation, the frequent interruptions generated by the microcontroller will result in poor real-time performance. The current practice is to use FPGA instead of MCU, but the basic version of FPGA does not have internal multipliers and dividers. Implementing motor speed measurement calculations will consume a large amount of memory resources, affecting later development and design. Summary of the Invention

[0004] The purpose of the present invention is to propose a motor speed measurement method based on FPGA to solve the technical problems of unstable motor speed measurement and long response time under external environmental interference, improve the anti-interference ability of motor speed measurement and accelerate the response speed of the speed measurement system.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows: A motor speed measurement method based on FPGA includes the following steps: S1, using a Hall encoder to detect motor rotation and output a pulse signal, which is output to the digital input interface of the FPGA, and a filtering speed measurement algorithm is implemented in the FPGA in hardware form; S2, using the FPGA to perform data calculation and processing on the pulse signal based on the filtering speed measurement algorithm to achieve measurement of the motor speed.

[0006] Furthermore, in S1, the filtering speed measurement algorithm is sinc 3Filtering algorithm; the sinc 3 The input signal of the filtering algorithm is the pulse signal output by the Hall encoder after being collected by the FPGA; the sinc 3 Z-domain transfer function of the filtering algorithm: Where M is the decimation factor, Z is the complex frequency domain variable of the Z transform, is the integral part transfer function, is the transfer function of the comb part.

[0007] Furthermore, in S2, the FPGA includes a configuration module, a counting module, a control module, a calculation module, a data storage module and a data processing module; the configuration module is connected to the pulse signal output by the Hall encoder; the counting module is connected to the configuration module; the control module is connected to the counting module; the calculation module is connected to the control module; the data storage module is connected to the calculation module; and the data processing module is connected to the data storage module; The configuration module sets the multiplication / division coefficient and the sinc according to the motor speed information and the clock frequency of the FPGA. 3 The decimation factor of the filtering algorithm; After the coefficient count value in the counting module reaches the frequency multiplication / division coefficient, the coefficient count value is reset to zero and counted again, and a pulse acquisition signal is sent to the control module; The decimation factor count value in the counting module reaches the sinc 3 After the extraction factor of the filtering algorithm is determined, the extraction count value is reset to zero and the count is restarted, and a data extraction signal is sent to the control module; The control module receives the pulse acquisition signal of the counting module and periodically acquires the pulse signal output by the Hall encoder; The control module receives the data extraction signal of the counting module and periodically collects the accumulated result of the addition operation of the operation module; The operation module implements the sinc 3 Addition operations in the integral part of the filtering algorithm and subtraction operations in the comb part; The operation module receives the pulse signal output by the Hall encoder collected by the control module as the sinc 3 The input signal of the addition operation of the integral part of the filtering algorithm; The operation module receives the accumulated signal of the addition operation of the operation module collected by the control module as the sinc 3 The input signal of the subtraction operation of the comb part of the filtering algorithm; The data storage module stores the sinc 3The result of each level of filtering algorithm operation; The data processing module receives the sinc 3 The third level operation result of the comb part of the filtering algorithm is based on the sinc 3 The extraction factor and sampling period of the filtering algorithm are used to perform data conversion on the third-level operation result to obtain the motor speed.

[0008] Furthermore, in S2, according to the sinc 3 The output value of the filtering algorithm is converted into motor speed: Where N is the motor speed, M is the decimation factor, and S is the sinc 3 Filter algorithm output value, T sample is sinc 3 Filter algorithm sampling period, in seconds.

[0009] Beneficial effects of the present invention: (1) The filtering speed measurement algorithm of the present invention has low-pass filtering characteristics, which effectively solves the problem of low motor speed measurement accuracy under external environmental interference; (2) The present invention uses FPGA to implement the filtering speed measurement algorithm. By taking advantage of the high-speed parallelization of FPGA programs, the operating efficiency of the filtering speed measurement algorithm is improved, and the response speed of the motor speed measurement system is accelerated; (3) The filtering speed measurement algorithm of the present invention has a simple structure and can measure the motor speed only through addition and subtraction operations, thus making up for the deficiency of the basic version FPGA having no multiplication and division devices inside. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Schematic diagram of the flow of the motor speed measurement method based on FPGA in the present invention; Figure 2 The sinc of the motor filter speed measurement method based on FPGA in the present invention 3 Filter algorithm implementation structure diagram; Figure 3 This is a block diagram of the FPGA internal modules of the motor filter speed measurement method based on FPGA in the present invention; Figure 4 This is a ModelSim simulation diagram of the FPGA-based motor filtering speed measurement method in an example of the present invention. DETAILED DESCRIPTION

[0011] The following describes the specific implementation of the embodiment of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present invention and is not used to limit the embodiment of the present invention.

[0012] like Figure 1 The figure shows a flow chart of the motor speed measurement method based on FPGA according to the present invention. Figure 1 The motor speed measurement method may include the following steps: In step S1, the motor rotation is detected by a Hall encoder and a pulse signal is output. The pulse signal is output to the digital input interface of the FPGA, and a filtering speed measurement algorithm is implemented in the FPGA in hardware form. In step S2, the FPGA is used to perform data calculation processing on the pulse signal based on the filtering speed measurement algorithm to achieve the measurement of the motor speed.

[0013] Step S1 is used to detect the motor rotation through the Hall encoder and output a pulse signal, which is output to the digital input interface of the FPGA. The filtering speed measurement algorithm is implemented in the FPGA in hardware form. 3 Filtering algorithm, sinc 3 The input signal of the filtering algorithm is the pulse signal output by the Hall encoder after being collected by FPGA. 3 Z-domain transfer function of the filtering algorithm: Where M is the decimation factor, Z is the complex frequency domain variable of the Z transform, is the integral part transfer function, is the transfer function of the comb part.

[0014] sinc 3 The filtering algorithm only needs to execute a cascaded 3-order accumulator at a high sampling frequency, and then execute a cascaded 3-order differentiator at a low sampling rate to complete the filtering, and according to the sinc 3 The output value of the filtering algorithm can be converted to the motor speed value. Figure 2 The figure shows the sinc circuit of the motor speed measurement method based on FPGA according to the present invention. 3 Filter algorithm implementation structure diagram. Figure 2 In the example, the input is the pulse signal output by the Hall encoder after being collected by the FPGA, and the output is the motor speed value after data conversion.

[0015] Step S2 is used to use FPGA to pass sinc 3 The filtering algorithm performs data calculation and processing on the pulse signal to achieve the measurement of the motor speed. Figure 3 The figure shows the internal module block diagram of the FPGA according to the motor filter speed measurement method based on FPGA in the present invention. Figure 3In the example, the FPGA may include a configuration module 1, a counting module 2, a control module 3, an operation module 4, a data storage module 5, and a data processing module 6; the configuration module is connected to the pulse signal output by the Hall encoder; the counting module is connected to the configuration module; the control module is connected to the counting module; the operation module is connected to the control module; the data storage module is connected to the operation module; and the data processing module is connected to the data storage module. The configuration module sets the multiplication / division coefficient and sinc according to the motor speed information and the FPGA clock frequency. 3 The decimation factor of the filtering algorithm; When the coefficient count value in the counting module reaches the frequency multiplication / division coefficient, the coefficient count value is reset and re-counted, and a pulse acquisition signal is sent to the control module; The extraction factor count value in the counting module reaches sinc 3 After the extraction factor of the filtering algorithm is determined, the extraction count value is reset to zero and the count is restarted, and a data extraction signal is sent to the control module; The control module receives the pulse acquisition signal from the counting module and periodically acquires the pulse signal output by the Hall encoder; The control module receives the data extraction signal of the counting module and periodically collects the accumulated results of the addition operation of the operation module; The operation module implements sinc 3 Addition operations in the integral part of the filtering algorithm and subtraction operations in the comb part; The operation module receives the pulse signal output by the Hall encoder collected by the control module as the sinc 3 The input signal of the addition operation of the integral part of the filtering algorithm; The operation module receives the accumulated signal of the addition operation of the operation module collected by the control module as sinc 3 The input signal of the subtraction operation of the comb part of the filtering algorithm; The data register module stores sinc 3 The result of each level of filtering algorithm operation; The data processing module receives the sinc in the data storage module 3 The third level operation result of the comb part of the filtering algorithm is based on the sinc 3 The decimation factor and sampling period of the filtering algorithm are used to convert the third-level operation result into motor speed.

[0016] According to sinc 3 The output value of the filtering algorithm is converted into motor speed: Where N is the motor speed, M is the decimation factor, and S is the sinc 3 Filter algorithm output value, T sample is sinc3 Filter algorithm sampling period, in seconds.

[0017] In this embodiment, the motor speed is initialized to 600r / min and the FPGA clock frequency is 50MHZ in the simulation test. The configuration module sets the frequency division coefficient to 5000 and sinc according to the motor speed and FPGA clock frequency. 3 The decimation factor M of the filtering algorithm is 1000, so sinc 3 Sampling period T of the filtering algorithm sample The sampling period is 100us and the sampling period is 100ms.

[0018] like Figure 4 The figure shows a ModelSim simulation diagram of the motor filter speed measurement method based on FPGA according to an embodiment of the present invention. Figure 4 In the example, sys_clk is the FPGA clock, rst_n is the system reset signal, hallOut is the pulse signal output by the Hall encoder, sinc 3 _input is the pulse signal output by the Hall encoder after being collected by FPGA, clk_count is the frequency division coefficient, sample_clk is the sinc 3 The sampling clocks of the filtering algorithm, acc1, acc2, and acc3 are sinc 3 The accumulated value of the three-stage cascade integral part of the filtering algorithm, word_count is the decimation factor, word_clk is sinc 3 The extraction clock of the filtering algorithm, diff1, diff2, and diff3 are sinc 3 The difference value of the three-stage cascade comb part of the filtering algorithm.

[0019] In this embodiment, it should be noted that sinc 3 _input is sinc 3 The input value of the filtering algorithm, sinc 3 _output is sinc 3 The output value of the filtering algorithm is S. Then the motor speed is: The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the scope of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A motor filter speed measurement method based on FPGA, characterized in that: The steps include: S1, using a Hall encoder to detect motor rotation and output a pulse signal, which is output to the digital input interface of the FPGA, and a filtering speed measurement algorithm is implemented in the FPGA in hardware form; S2, using the FPGA to perform data calculation and processing on the pulse signal based on a filtering speed measurement algorithm to achieve measurement of the motor speed.

2. The motor speed measurement method based on FPGA according to claim 1, characterized in that: In S1, the filtering speed measurement algorithm is sinc 3 Filtering algorithm; the sinc 3 The input signal of the filtering algorithm is the pulse signal output by the Hall encoder after being collected by the FPGA; the sinc 3 Z-domain transfer function of the filtering algorithm: ； Where M is the decimation factor, Z is the complex frequency domain variable of the Z transform, is the integral part transfer function, is the transfer function of the comb part.

3. The motor speed measurement method based on FPGA according to claim 2, characterized in that: In S2, the FPGA includes a configuration module, a counting module, a control module, an operation module, a data storage module and a data processing module; the configuration module is connected to the pulse signal output by the Hall encoder; the counting module is connected to the configuration module; the control module is connected to the counting module; the operation module is connected to the control module; the data storage module is connected to the operation module; and the data processing module is connected to the data storage module.

4. The motor speed measurement method based on FPGA according to claim 3, characterized in that: The configuration module sets the multiplication / division coefficient and the sinc according to the motor speed information and the clock frequency of the FPGA. 3 Decimation factor of the filtering algorithm.

5. The motor speed measurement method based on FPGA according to claim 4, characterized in that: After the coefficient count value in the counting module reaches the frequency multiplication / division coefficient, the coefficient count value is reset to zero and counted again, and a pulse acquisition signal is sent to the control module; The decimation factor count value in the counting module reaches the sinc 3 After the extraction factor of the filtering algorithm is determined, the extraction count value is reset to zero and re-counted, and a data extraction signal is sent to the control module.

6. The motor speed measurement method based on FPGA according to claim 5, characterized in that: The control module receives the pulse acquisition signal of the counting module and periodically acquires the pulse signal output by the Hall encoder; The control module receives the data extraction signal from the counting module and periodically collects the accumulated result of the addition operation of the operation module.

7. The motor speed measurement method based on FPGA according to claim 6, characterized in that: The operation module implements the sinc 3 Addition operations in the integral part of the filtering algorithm and subtraction operations in the comb part; The operation module receives the pulse signal output by the Hall encoder collected by the control module as the sinc 3 The input signal of the addition operation of the integral part of the filtering algorithm; The operation module receives the accumulated signal of the addition operation of the operation module collected by the control module as the sinc 3 The input signal of the comb part subtraction operation of the filtering algorithm.

8. The motor speed measurement method based on FPGA according to claim 7, characterized in that: The data storage module stores the sinc 3 The result of each level of filtering algorithm operation; The data processing module receives the sinc 3 The third level operation result of the comb part of the filtering algorithm is based on the sinc 3 The extraction factor and sampling period of the filtering algorithm are used to perform data conversion on the third-level operation result to obtain the motor speed.

9. The motor speed measurement method based on FPGA according to claim 8, characterized in that: According to the sinc 3 The output value of the filtering algorithm is converted into motor speed: in, N is the motor speed, M is the extraction factor, S is sinc 3 The output value of the filtering algorithm, T sample is sinc 3 Filter algorithm sampling period, in seconds.

Images