Capacitor charge coupling-based single-bit full adder, multi-bit adder and chip

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a single-bit full adder based on capacitor charge coupling, a multi-bit adder and a chip. The circuit comprises four NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N4, two PMOS (P-channel Metal Oxide Semiconductor) transistors P1 and P2, seven capacitors C1 to C7, two phase inverters INV1 and INV2 and a buffer B1, and the capacitance value of the C7 is twice of that of the C1-C6. Wherein the N1 and the N2 form a reset part, the capacitors C1-C7 form an analog operation part, additive operation in an analog domain is achieved through the charge coupling effect of the capacitors, and the N3, the N4, the P1, the P2, the INV1, the INV2 and the B1 form a digital quantization part. Compared with a traditional full adder, the full adder has the advantages that the computational logic of a circuit is changed, the number of transistors of the full adder can be greatly reduced under the condition that the output full swing is kept, the area is remarkably reduced, and the area utilization rate is increased.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a single-bit full adder, a multi-bit adder, a logic operation module, an accumulator and a logic chip thereof based on capacitor charge coupling. Background Art

[0002] With the continuous advancement of integrated circuit technology, designing more efficient circuits has become crucial. In full adder design, reducing the number of MOS transistors and minimizing their area to improve area utilization is crucial. As integrated circuit process nodes continue to shrink, transistor size continues to decrease. While this allows for more functionality to be integrated within the same area, the space and power consumption required for each unit remain design challenges. Reducing the number of MOS transistors in a full adder effectively reduces the device's footprint, freeing up more space for layout. This not only helps increase the integration of other circuit modules but also makes the overall chip design more compact, improving circuit area utilization efficiency and facilitating the integration of more complex functions and flexible circuit design.

[0003] Most existing full adders are designed using a variety of logic devices, resulting in a large number of MOS transistors and high circuit power consumption. In applications, switching losses are often directly proportional to the number of MOS transistors. Reducing the number of MOS transistors can also reduce circuit power consumption. By optimizing the full adder design and reducing the number of unnecessary transistors, the circuit's energy efficiency can be improved, thereby extending the device's lifespan and reducing the difficulty of thermal management. Furthermore, some circuits have reduced the number of MOS transistors through optimized circuit design. However, this also prevents the circuit's output from achieving full swing, further reducing the circuit's quantization difficulty and application value. Summary of the Invention

[0004] In order to solve the problem that existing circuit designs are difficult to fully optimize full adders in terms of output swing and number of transistors, the present invention provides a single-bit full adder, a multi-bit adder, a logic operation module, an accumulator and their corresponding logic chips based on capacitive charge coupling.

[0005] The technical solution provided by the present invention is:

[0006] A single-bit full adder based on capacitive charge coupling includes four NMOS transistors N1 to N4, two PMOS transistors P1 and P2, seven capacitors C1 to C7, two inverters INV1 and INV2, and a buffer B1. The capacitance of C7 is twice that of C1 to C6. The circuit connection is:

[0007] The source of P2 is connected to VDD; the sources of N1, N2 and N4 are grounded; the drain of N1 and the upper plates of C1, C2 and C3 are connected to the input of INV1; the drain of M2 and the upper plates of C4, C5, C6 and C7 are connected to the input of B1; the gates of N1 and N2 are connected to the control signal CLR; the gates of P1 and N3 are connected to the control signal CLRB; the sources of P1 and N3 are connected to the gates of P2 and N4; the drain of P1 is connected to the output of INV1 and the input of INV2; the drains of P2 and N4 are connected to the lower plate of C7; the lower plates of C1 and C4 are connected and serve as the input port of one of the addends A, the lower plates of C2 and C5 are connected and serve as the input port of the other addend B; the lower plates of C3 and C6 are connected and serve as the carry signal C of the low-order input. in The drain of M3 is connected to the output of INV2 and serves as the carry signal C output to the high bit. out ; The output end of B1 serves as the output port of the addition result S.

[0008] As a further improvement of the present invention, the inverter is composed of a PMOS transistor and an NMOS transistor; the source of the PMOS transistor is connected to a power supply; the source of the NMOS transistor is grounded; the gates of the NMOS transistor and the PMOS transistor are connected and serve as the input end of the inverter; and the drains of the NMOS transistor and the PMOS transistor are connected and serve as the output end of the inverter.

[0009] As a further improvement of the present invention, the buffer B1 is composed of two inverters connected in series, and each buffer is composed of two PMOS transistors and two NMOS transistors.

[0010] The single-bit full adder based on capacitor charge coupling provided by the present invention is used to input two single-bit addends A and B, and a carry signal C of a low-bit input. in Generate the single-bit addition result S of the current bit and the carry signal C output to the high bit out .

[0011] Among them, when A, B, C in , S, C out When it is high, it means the corresponding bit is "1"; when A, B, C in , S, C out When it is low, it means the corresponding bit is "0".

[0012] As a further improvement of the present invention, the control logic of the single-bit full adder based on capacitive charge coupling to realize the operation is divided into three stages: charge clearing, preparation and calculation. The process includes:

[0013] ⅰ. Charge reset stage

[0014] Set the control signal CLR to high level and CLRB to low level, A, B, Cin The corresponding port is set to low level.

[0015] II. Preparation

[0016] Set the control signal CLR to low level and CLRB to high level, A, B, C in The corresponding port still maintains a low level.

[0017] ⅲ. Calculation stage

[0018] Keep the control signal CLR at a low level and CLRB at a high level; input two addends A and B and the carry signal C of the low-order input through the corresponding ports respectively. in The value of the current bit is represented by S and C. out Corresponding port output.

[0019] The present invention also includes a multi-bit adder for implementing addition operations between two multi-bit numbers. The multi-bit adder is formed by cascading n single-bit full adders based on capacitor charge coupling as described above. The carry signal output to the high bit in the single-bit full adder of the previous stage is The carry signal of the low-order input of the next-stage single-bit full adder Connected, the carry signal of the low-order input of the lowest-level single-bit full adder Set to low level.

[0020] Among them, the two corresponding input ports of the single-bit full adder at each level are used to input the value of the sum of the two addends at their respective positions; the corresponding output ports are used to output the value of the single-bit addition result at their respective positions. In addition, the carry signal output to the high position in the highest level single-bit full adder is Used to output the carry result on the highest bit.

[0021] As a further improvement of the present invention, the multi-bit adder is used to input two multi-bit addends A1 to A2. n and B1~B n , generate multi-bit addition results S1~S n And the carry signal output to the high bit

[0022] The control logic for implementing the operation is also divided into three stages: charge clearing, preparation, and calculation. The process includes:

[0023] ⅰ. Charge reset stage

[0024] Set the control signal CLR of each single-bit full adder to a high level and CLRB to a low level. in The corresponding port is set to low level.

[0025] II. Preparation

[0026] The control signal CLR of each single-bit full adder is set to a low level, and the control signal CLRB is set to a high level. in The corresponding port still maintains a low level.

[0027] ⅲ. Calculation stage

[0028] The control signal CLR of each single-bit full adder is kept at a low level, and the control signal CLRB is kept at a high level; the two addends A and B on each bit are input synchronously through the corresponding ports on each single-bit full adder; the addition result representing each bit is output through the port corresponding to the signal S in each single-bit full adder, and the carry value of the highest bit of the operation result is transmitted through The corresponding port output.

[0029] The present invention also includes a logic operation module, which is encapsulated as the aforementioned multi-bit adder. The logic operation module includes pins including: 1 power supply terminal, 1 ground terminal, 2 control terminals, 2n input terminals, n sum output terminals, and 1 carry output terminal. Among them, the power supply terminal is used to connect to the power supply VDD; the ground terminal is used to connect to the ground VSS; the control terminal is used to connect to a set of mutually inverted control signals CLR and CLRB; each input terminal is used to input input signals A1 to A2 representing the value of each bit in two sets of n-bit addends. n and B1~B n Each sum output terminal is used to output output signals S1 to S2 representing the values of each bit of the n-bit addition result. n The carry output is used to output the carry result from the highest bit of the n-bit addition result to the next bit. value.

[0030] The present invention also includes an accumulator, which uses multiple single-bit full adders based on capacitor charge coupling as described above, or multiple multi-bit adders as described above as adding units; and each adding unit is designed as an adder tree structure; thereby realizing accumulation operation of multiple single-bit addends or multi-bit addends.

[0031] The present invention also includes a logic chip, which includes any one or more of the aforementioned single-bit full adder based on capacitive charge coupling, the aforementioned multi-bit adder, and the aforementioned accumulator.

[0032] The technical solution provided by the present invention has the following beneficial effects:

[0033] The present invention designs a single-bit full adder based on capacitor charge coupling based on a brand-new circuit principle, and derives a variety of addition-related circuits, such as multi-bit adders and accumulators. The single-bit full adder designed by the present invention includes a capacitor array for implementing operations, a digital quantization circuit for generating operation results, and a reset and zeroing part for forming a discharge path of the capacitor array. The overall design of the circuit can be implemented with only 14 transistors and 7 capacitors. The circuit design is very simple. Compared with various traditional full adders, the present invention changes the calculation logic and can greatly reduce the number of full adder MOS transistors while maintaining the full output swing, significantly reducing the area and improving the area utilization; thereby achieving a balance between circuit performance and power consumption, and has extremely high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a circuit diagram of a single-bit full adder based on capacitive charge coupling provided in Example 1 of the present invention.

[0035] Figure 2 4 is a circuit diagram of the inverter and buffer used in Example 1 of the present invention.

[0036] Figure 3 This is a functional principle diagram of a single-bit full adder in Example 1 of the present invention.

[0037] Figure 4 This is a circuit schematic diagram of a multi-bit adder provided in Example 2 of the present invention.

[0038] Figure 5 To verify the signal flow diagram during the circuit performing the addition operation in the experiment.

[0039] Figure 6 To verify the normal distribution curve of 2000 Monte Carlo simulation results of S in the circuit operation results in the experiment.

[0040] Figure 7 To verify the operation results of the circuit in the experiment, C out Normal distribution curve of 2000 Monte Carlo simulation results. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] Example 1

[0043] This embodiment provides a single-bit full adder based on capacitor charge coupling. The circuit is used to input two single-bit addends A and B, and a carry signal C of the low-bit input. in Generate the single-bit addition result S of the current bit and the carry signal C output to the high bit out .like Figure 1 As shown, the single-bit full adder provided in this embodiment includes four NMOS transistors N1 to N4, two PMOS transistors P1 and P2, seven capacitors C1 to C7, two inverters INV1 and INV2, and one buffer B1. Among them, the capacitance value of C7 is twice that of C1 to C6. The circuit connection is:

[0044] The source of P2 is connected to VDD; the sources of N1, N2 and N4 are grounded; the drain of N1 and the upper plates of C1, C2 and C3 are connected to the input of INV1; the drain of M2 and the upper plates of C4, C5, C6 and C7 are connected to the input of B1; the gates of N1 and N2 are connected to the control signal CLR; the gates of P1 and N3 are connected to the control signal CLRB; the sources of P1 and N3 are connected to the gates of P2 and N4; the drain of P1 is connected to the output of INV1 and the input of INV2; the drains of P2 and N4 are connected to the lower plate of C7; the lower plates of C1 and C4 are connected and serve as the input port of one of the addends A, the lower plates of C2 and C5 are connected and serve as the input port of the other addend B; the lower plates of C3 and C6 are connected and serve as the carry signal C of the low-order input. in The drain of M3 is connected to the output of INV2 and serves as the carry signal C output to the high bit. out ; The output end of B1 serves as the output port of the addition result S.

[0045] In the above circuit provided in this embodiment, each inverter is composed of a PMOS tube and an NMOS tube; Figure 2 As shown in part (a) of the figure, the source of the PMOS transistor is connected to the power supply; the source of the NMOS transistor is grounded; the gates of the NMOS transistor and the PMOS transistor are connected and serve as the input of the inverter; the drains of the NMOS transistor and the PMOS transistor are connected and serve as the output of the inverter. Figure 2 In part (b) of this embodiment, the buffer B1 can be composed of two inverters connected in series, that is, each buffer is composed of two PMOS transistors and two NMOS transistors. Of course, in actual applications, as long as the same circuit function can be achieved, Figure 1 The buffer B1 in the circuit can also adopt other circuit structures. In summary, after adopting the inverter and buffer composed of the MOS tube, Figure 1The single-bit full adder shown can be composed of 8 NMOS transistors, 6 PMOS transistors and 7 capacitors. Compared with the existing full adder circuit structure that can maintain full-rail output, the circuit solution provided by this embodiment has significantly reduced the number of transistors.

[0046] Compared with the traditional full adder, the single-bit full adder of this embodiment provides a new logic of addition budget. Figure 3 As shown, according to the circuit function, the single-bit full adder based on capacitor charge coupling provided in this embodiment can be divided into three parts, including a reset and clearing part composed of NMOS transistors N1 and N2, an analog operation part composed of capacitors C1 to C7, and a digital quantization part composed of NMOS transistors N3 and N4, PMOS transistors P1 and P2, inverters INV1 and INV2, and buffer B1. The analog operation part uses the charge coupling effect of the capacitors to perform an addition operation on the two input addends and the carry, and then uses the upper plate voltage of the capacitors on both sides as an analog quantity representing the addition result; the digital quantization part is used to generate the corresponding digital quantity of the addition result and the corresponding carry value based on the upper plate voltage of the capacitor; the reset and clearing part is used to discharge the charge on the upper plate of the capacitor in the analog operation part before and after each operation of the circuit, so as to clear the result of the previous round of operation and prevent the residual charge on the capacitor from interfering with the operation result.

[0047] In the actual application of the circuit, the control logic of the single-bit full adder based on capacitive charge coupling provided in this embodiment to implement the addition operation is divided into three stages: charge clearing, preparation, and calculation. The detailed process is as follows:

[0048] ⅰ. Charge reset stage

[0049] Set the control signal CLR to high level and CLRB to low level, A, B, C in The corresponding port is set to low level.

[0050] When CLR is high, N1 and N2 conduct, forming a discharge path between the top plates of capacitors C1-C7 and ground VSS. At this point, the lower plates of capacitors C1-C7 are at a low level, and the top plates are grounded, discharging the charge on them and returning the charge on each capacitor to zero. Simultaneously, setting CLRB low ensures that the lower plate of C7 is also low, discharging the capacitance on C7.

[0051] In addition, during the entire process of CLR enabling and clearing the charge, it is necessary to ensure that the three input V A 、V B 、V Cin It is 0mV, and there will be a short preparation phase after the reset phase.

[0052] II. Preparation

[0053] Set the control signal CLR to low level and CLRB to high level, A, B, C in The corresponding port still maintains a low level.

[0054] When CLR is low, N1 and N2 are turned off, and the discharge path between the upper plate of capacitors C1 to C7 and the ground terminal VSS is disconnected. At the same time, setting CLRB to a high level can make the input of the lower plate of C7 C out The inverted value is ready to enter the calculation phase to ensure the correct result.

[0055] ⅲ. Calculation stage

[0056] Keep the control signal CLR at a low level and CLRB at a high level; input two addends A and B and the carry signal C of the low-order input through the corresponding ports respectively. in The value of the current bit is represented by S and C. out Corresponding port output.

[0057] The circuit of the single-bit full adder provided in this embodiment is used to implement addition operations between single-bit numbers. Therefore, two addends A and B, the addition result S and the low-order carry C in and high-order carry C out are all single-bit numbers, so the corresponding values can be represented by the level of each port. Specifically, in this embodiment, when A, B, C in , S, C out When it is high, it means the corresponding bit is "1"; when A, B, C in , S, C out When it is low, it means the corresponding bit is "0".

[0058] During the calculation phase, this embodiment maintains control signal CLR at a low level and CLRB at a high level, effectively disconnecting the discharge path between the top plates of capacitors C1-C7 and ground VSS. Simultaneously, in this embodiment, the top plates of capacitors C1-C3 and C4-C7 are connected together, serving as two "bit lines" representing the calculation results, designated CL1 and CL2. The capacitors on each side share charge via their corresponding bit lines.

[0059] In this state, when A, B, C in When any one of A, B, C is high (representing a value of "1"), it can continue to charge the corresponding capacitor, thereby causing the bit line voltage on the corresponding side to increase. inWhen either of the bit lines CL1 and CL2 is low (representing a value of "0"), the corresponding capacitor cannot be charged, and the bit line voltage cannot be increased. Therefore, the circuit of this embodiment can represent the final calculation result and the corresponding carry value to the higher bit by the voltage level of the bit lines CL1 and CL2 on both sides of the capacitor.

[0060] Based on the above circuit design, the following describes how this embodiment generates the operation result S and the carry C to the higher bit according to the bit line voltage of the bit lines CL1 and CL2 through the digital quantization part. out Circuit principle:

[0061] (1) Carry result C to the higher bit out Generation

[0062] In single-bit addition, according to A, B, C in There are 8 different operation cases. In these 8 cases, C out =1 includes 4 cases, namely:

[0063] A=1,B=1,C in =1,

[0064] A=1,B=1,C in =0,

[0065] A=0,B=1,C in =1,

[0066] A=1,B=0,C in =1,

[0067] And make C out =0 includes four cases, namely:

[0068] A=0,B=0,C in =0,

[0069] A=1,B=0,C in =0,

[0070] A=0,B=1,C in =0,

[0071] A=0,B=0,C in =1,

[0072] It can be seen that only A, B, C in The number of high level states in the C out =0, greater than 1, then C out =1. In this embodiment, the voltage of the bit line CL1 corresponding to the upper plate of C1-C3 passes through two inverters INV1 and INV2, and outputs Cout value.

[0073] Combine Figure 3 In the circuit of this embodiment, since C1=C2=C3, according to the charge coupling principle of capacitors, the voltage output value V of the upper plates of C1 to C3 is CL1 =(V A +V B +V Ci ) / 3. In this case, when V A 、V B 、V Cin When both are high level (i.e. 900mV), the output V CL1 is 900mV; when any two of the three are high, the output V CL1 is 600mV; when only one of the three is high, the output V CL1 is 300mV; when all three are low (0mV), the output V CL1 is 0mV.

[0074] Therefore, when the input is 2 or 3 900mV, the output is greater than 450mV, which is consistent with the carry output C of the full adder. out The situation is similar: when there are 2 or 3 "1"s among the 3 inputs, the carry output C out is "1", and the rest are "0". CL1 Connect one or two inverters (equivalent to a buffer) to make V CL1 When it is greater than 450mV, it changes to 900mV (logic "1"); when V CL1 When it is less than 450mV, it turns to 0mV (logic "0"), completing the carry output C out Thus, the single-bit full adder provided in this embodiment can be designed based on A, B, C in Different inputs, accurately output C out value.

[0075] (2) Generation of the calculation result S on this position

[0076] Among the eight operation cases of single-bit addition operation, there are four cases where S=0, namely:

[0077] A=1,B=1,C in =0,

[0078] A=0,B=1,C in =1,

[0079] A=1,B=0,C in =1,

[0080] A=0,B=0,C in =0,

[0081] There are four situations where S=1, namely:

[0082] A=1,B=1,C in =1,

[0083] A=1,B=0,C in =0,

[0084] A=0,B=1,C in =0,

[0085] A=0,B=0,C in =1,

[0086] It can be seen that when A, B, C in When the number of high-level states is an even number (0 or 2), S=0. When it is an odd number (1 or 3), S=1. In this embodiment, the voltage of the bit line CL2 corresponding to the upper plates of C4 to C7 passes through the buffer B1 and outputs the value of S. In the circuit designed in this embodiment, since the calculation bit line CL2 corresponding to S is connected to four capacitors C4 to C7 at the same time, and the capacitance value of C7 is twice that of C1 to C3. Therefore, the output value of S will not only be affected by the input A, B, C in The value of the output is also affected by the C out impact.

[0087] Combine Figure 3 In the circuit of this embodiment, similarly, since C4=C5=C6=C1, C7=2C4, the voltage output value of the upper plate of C4~C7 is Where V C7 And with C out According to the truth table of the full adder's local summation output S, when C out is "0" and V A 、V B 、V Cin When all three inputs are "0", the output S is "0". out is "0" and V A 、V B 、V Cin When only one of the three inputs is "1", the output S is "1". out is "1" and V A 、V B 、V Cin When any two of the three inputs are "1", the output S is "0". out is "1" and V A 、VB 、V Cin When all three inputs are "1", the output S is "1". According to the characteristics of this situation, in the calculation stage, the design of V C7 The value of C out The value of is negated, so when C out When V is 0mV, C7 is 900mV, when V A 、V B 、V Cin When all three inputs are 0mV, the output V CL2 Less than 450mV, it will be converted to 0mV (logic “0”) after passing through a buffer. A 、V B 、V Cin When only one of the three inputs is 900mV, the output V CL2 Greater than 450mV, it changes to 900mV (logic “1”) after passing through a buffer. out When V C7 is 0mV, when V A 、V B 、V Cin When any two of the three inputs are 900mV, the output V CL2 Less than 450mV, it will be converted to 0mV (logic “0”) after passing through a buffer. A 、V B 、V Cin When all three inputs are 900mV, the output V CL2 is greater than 450mV, and after passing through a buffer, it is converted to 900mV (logic "1"). Thus, the design of the local sum output S is completed. It can be seen that the single-bit full adder provided in this embodiment can be used according to A, B, C in Different inputs accurately output the value of S.

[0088] In addition, it is necessary to further explain that: when designing the digital quantization part of the single-bit full adder of this embodiment, there is a special problem that requires special circuit design: As mentioned above, in the calculation stage, V C7 The value of C out However, in the charge clearing phase, it is necessary to ensure that the three input V A 、V B 、V Cin 0mV, V C7 Also needs to be 0mV, then C out The result is also 0mV. Therefore, it is necessary to design V C7The values of P1, P2, N3, N4 and control signals CLR and CLRB are based on this design idea. When the charge is cleared, V C7 The value of C out Keep it consistent, which is 0mV; in the calculation stage of design, V C7 The value of C out This circuit design can ensure the integrity of the circuit function while making the circuit design simpler and reducing the number of MOS tubes used.

[0089] Example 2

[0090] Based on the solution of embodiment 1, this embodiment further provides a multi-bit adder for implementing the addition operation between two multi-bit numbers. The multi-bit adder is formed by cascading n single-bit full adders based on capacitor charge coupling as described above, and the carry signal output to the high bit in the single-bit full adder of the previous stage is The carry signal of the low-order input of the next-stage single-bit full adder Connected, the carry signal of the low-order input of the lowest-level single-bit full adder Set to low level.

[0091] The multi-bit adder provided in this embodiment consists of multiple Figure 1 The single-bit full adders shown in the figure are cascaded. Figure 1 The single bit shown is an integrated device Add, which includes a power supply port VDD, a ground port VSS, and input ports A, B, and C. in , control ports CLR and CLRB, and output ports S and C out The multi-bit adder provided in this embodiment is as follows: Figure 4 As shown in the circuit, the power supply port VDD, ground port VSS and control ports CLR and CLRB of each Add can be connected in common. and the next level Add The Cin of the first-stage Add is connected to a low level. The number of single-bit full adders Add used in the circuit is the maximum number of bits of the maximum multi-bit addend supported by the circuit.

[0092] At this time, the two corresponding input ports A and B of the single-bit full adder Add at each level are used to input the sum of the two addends at their respective positions; the corresponding output ports S are used to output the single-bit addition result at their respective positions. In addition, the carry signal output to the high position in the highest level single-bit full adder Used to output the carry result on the highest bit.

[0093] As a further improvement of the present invention, the multi-bit adder is used to input two multi-bit addends A1 to A2. n and B1~B n , generate multi-bit addition results S1~S n And the carry signal output to the high bit

[0094] Correspondingly, similar to the operation logic of a single-bit full adder, the control logic for implementing the operation of the multi-bit adder of this embodiment is also divided into three stages: charge clearing, preparation, and calculation. The process includes:

[0095] ⅰ. Charge reset stage

[0096] The control signals CLR of each single-bit full adder Add1 to Addn are set to high level, CLRB to low level, A, B, C in The corresponding port is set to low level.

[0097] II. Preparation

[0098] The control signal CLR of each single-bit full adder Add1~Addn is set to a low level, and the control signal CLRB is set to a high level. in The corresponding port still maintains a low level.

[0099] ⅲ. Calculation stage

[0100] The control signals CLR of each single-bit full adder Add1~Addn are kept at a low level, and CLRB is kept at a high level; the two addends A1~A1 on each bit are input synchronously through the corresponding ports on each single-bit full adder Add1~Addn. n and B1~B n ; The addition result on each bit is represented by the signals S1~S in each single-bit full adder Add1~Addn n The corresponding port output, the carry value of the highest bit of the operation result is passed The corresponding port output.

[0101] In practical applications, the multi-bit adder provided in this embodiment can be used as a logic operation module, which is encapsulated by the aforementioned multi-bit adder. The logic operation module includes pins including: 1 power supply terminal, 1 ground terminal, 2 control terminals, 2n input terminals, n sum output terminals, and 1 carry output terminal. Among them, the power supply terminal is used to connect to the power supply VDD; the ground terminal is used to connect to the ground VSS; the control terminal is used to connect to a set of mutually inverted control signals CLR and CLRB; each input terminal is used to input input signals A1~A representing the value of each bit in the two sets of n-bit addends. n and B1~Bn Each sum output terminal is used to output output signals S1 to S2 representing the values of each bit of the n-bit addition result. n The carry output is used to output the carry result from the highest bit of the n-bit addition result to the next bit. value.

[0102] Example 3

[0103] Based on the solutions in the aforementioned embodiments 1 and 2, this embodiment further provides an accumulator. The accumulator in this embodiment uses multiple single-bit full adders based on capacitive charge coupling, such as in embodiment 1, or multiple multi-bit adders, such as in embodiment 2, as adding units. Each adding unit is designed as a tree structure of various types of adders, thereby enabling accumulation operations on multiple single-bit addends or multi-bit addends.

[0104] Example 4

[0105] Based on the solutions in Examples 1 to 3, this embodiment further provides a logic chip, which includes any one or more of the single-bit full adder based on capacitive charge coupling in Example 1, the multi-bit adder in Example 2, and the accumulator in Example 3.

[0106] Compared to traditional circuits, the logic chip of this embodiment utilizes a newly designed single-bit full adder and its derived multi-bit adders and accumulators. These circuits change the computational logic of addition operations in traditional circuits and significantly reduce the number of MOS transistors in the full adder while maintaining full output swing. This significantly reduces the area and improves area utilization. Therefore, the logic chip provided by this embodiment can reduce circuit power consumption while maintaining computational efficiency.

[0107] Verification experiment

[0108] In order to verify the circuit performance of the single-bit full adder based on capacitive charge coupling provided by the present invention, this embodiment selects Figure 1 The circuit design shown in the figure is simulated in Cadence Virtuoso. This embodiment performs 2000 Monte Carlo simulations on the circuit operation process, in which CLR, CLRB, A, B, C in each round of operation are in The signal flow diagram is as follows Figure 5 As shown, CR represents the charge clearing stage, PS represents the preparation stage, and CS represents the calculation stage.

[0109] According to the experimental results of Monte Carlo simulation, the calculation results S and C can be plotted. out The normal distribution curves of Figure 6 and Figure 7 Analyzing the data in the figure, we find that the single-bit full adder based on capacitor charge coupling designed in the present invention can effectively reduce the number of MOS transistors while ensuring that the output is close to the full swing. When the output is "0", the voltage is close to 0mV, and when the output is "1", the voltage is close to 900mV. The deviation is extremely small, the calculation accuracy is as high as 100%, and it has good computing performance.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A single-bit full adder based on capacitive charge coupling, characterized in that: It includes four NMOS transistors N1 to N4, two PMOS transistors P1 and P2, seven capacitors C1 to C7, two inverters INV1 and INV2, and a buffer B1. The capacitance value of C7 is twice that of C1 to C6. The circuit connection is: The source of P2 is connected to VDD; the sources of N1, N2 and N4 are grounded; the drain of N1 and the upper plates of C1, C2 and C3 are connected to the input of INV1; the drain of M2 and the upper plates of C4, C5, C6 and C7 are connected to the input of B1; the gates of N1 and N2 are connected to the control signal CLR; the gates of P1 and N3 are connected to the control signal CLRB; the sources of P1 and N3 are connected to the gates of P2 and N4; the drain of P1 is connected to the output of INV1 and the input of INV2; the drains of P2 and N4 are connected to the lower plate of C7; the lower plates of C1 and C4 are connected and serve as the input port of one of the addends A, the lower plates of C2 and C5 are connected and serve as the input port of the other addend B; the lower plates of C3 and C6 are connected and serve as the carry signal C of the low-order input. in The drain of M3 is connected to the output of INV2 and serves as the carry signal C output to the high bit. out ; The output end of B1 serves as the output port of the addition result S.

2. The single-bit full adder based on capacitive charge coupling according to claim 1, wherein: The inverter is composed of a PMOS tube and an NMOS tube; the source of the PMOS tube is connected to the power supply; the source of the NMOS tube is grounded; the gates of the NMOS tube and the PMOS tube are connected and serve as the input end of the inverter; the drains of the NMOS tube and the PMOS tube are connected and serve as the output end of the inverter.

3. The single-bit full adder based on capacitive charge coupling according to claim 1, wherein: The buffer B1 is composed of two inverters connected in series, including two PMOS transistors and two NMOS transistors.

4. The single-bit full adder based on capacitive charge coupling according to claim 1, wherein: It is used to calculate the value of the two single-bit addends A and B according to the input, and the carry signal C of the low-order input. in Generate the single-bit addition result S of the current bit and the carry signal C output to the high bit out ; Among them, when A, B, C in , S, C out When it is high, it means the corresponding bit is "1"; when A, B, C in , S, C out When it is low, it means the corresponding bit is "0".

5. The single-bit full adder based on capacitive charge coupling according to claim 4, wherein: The control logic for implementing the operation is divided into three stages: charge clearing, preparation, and calculation. The process includes: ⅰ. Charge reset stage Set the control signal CLR to high level and CLRB to low level, A, B, C in The corresponding port is set to low level; II. Preparation Set the control signal CLR to low level and CLRB to high level, A, B, C in The corresponding port still maintains a low level; ⅲ. Calculation stage Keep the control signal CLR at a low level and CLRB at a high level; input two addends S and B and the carry signal C of the low-order input through the corresponding ports respectively. in The value of the current bit is represented by S and C. out Corresponding port output.

6. A multi-bit adder, characterized in that: It is used to realize the addition operation between two multi-bit numbers; the multi-bit adder is formed by cascading n single-bit full adders based on capacitive charge coupling as described in any one of claims 1 to 5, and the carry signal output to the high bit in the single-bit full adder of the previous stage is The carry signal of the low-order input of the next-stage single-bit full adder Connected; the carry signal of the low-order input in the lowest-level single-bit full adder Set to low level; The two corresponding input ports of the single-bit full adder at each level are used to input the value of the sum of the two addends on their respective positions; the corresponding output ports are used to output the value of the single-bit addition result on their respective positions; the carry signal output to the high position in the highest level single-bit full adder Used to output the carry result on the highest bit.

7. The multi-bit adder according to claim 6, wherein: It is used to input two multi-bit addends A1 to A n and B1~B n , generate multi-bit addition results S1~S n And the carry signal output to the high bit The control logic for implementing the operation is divided into three stages: charge clearing, preparation, and calculation. The process includes: ⅰ. Charge reset stage Set the control signal CLR of each single-bit full adder to a high level and CLRB to a low level. in The corresponding port is set to low level; II. Preparation The control signal CLR of each single-bit full adder is set to a low level, and the control signal CLRB is set to a high level. in The corresponding port still maintains a low level; ⅲ. Calculation stage The control signal CLR of each single-bit full adder is kept at a low level, and the control signal CLRB is kept at a high level; the two addends A and B on each bit are input synchronously through the corresponding ports on each single-bit full adder; the addition result representing each bit is output through the port corresponding to the signal S in each single-bit full adder, and the carry value of the highest bit of the operation result is transmitted through The corresponding port output.

8. A logic operation module, characterized in that: It is encapsulated by the multi-bit adder according to claim 6 or 7; the logic operation module includes pins including: 1 power supply terminal, which is used to connect the power supply VDD; 1 ground terminal, which is used to ground VSS; 2 control terminals, which are used to receive a set of mutually inverted control signals CLR and CLRB; 2n input terminals, which are used to input input signals A1 to A2 representing the values of each bit in two groups of n-bit addends. n and B1~B n ; n sum output terminals, which are used to output output signals S1 to S2 representing the values of each bit of the n-bit addition result. n ; 1 carry output terminal, which is used to output the carry result of the highest bit of the n-bit addition result to the next bit above value.

9. An accumulator, characterized in that: It uses multiple single-bit full adders based on capacitor charge coupling as described in any one of claims 1 to 5, or multiple multi-bit adders as described in claim 6 or 7 as adding units; and designs each of the adding units into an adder tree structure; thereby realizing accumulation operation of multiple single-bit addends or multi-bit addends.

10. A logic chip, characterized in that: It includes any one or more of the single-bit full adder based on capacitive charge coupling as described in any one of claims 1 to 5, the multi-bit adder as described in claim 6 or 7, and the accumulator as described in claim 9.

Images